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30#include "hw.h"
31#include "q35.h"
32
33
34
35
36
37static int q35_host_init(SysBusDevice *dev)
38{
39 PCIBus *b;
40 PCIHostState *pci = FROM_SYSBUS(PCIHostState, dev);
41 Q35PCIHost *s = Q35_HOST_DEVICE(&dev->qdev);
42
43 memory_region_init_io(&pci->conf_mem, &pci_host_conf_le_ops, pci,
44 "pci-conf-idx", 4);
45 sysbus_add_io(dev, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem);
46 sysbus_init_ioports(&pci->busdev, MCH_HOST_BRIDGE_CONFIG_ADDR, 4);
47
48 memory_region_init_io(&pci->data_mem, &pci_host_data_le_ops, pci,
49 "pci-conf-data", 4);
50 sysbus_add_io(dev, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem);
51 sysbus_init_ioports(&pci->busdev, MCH_HOST_BRIDGE_CONFIG_DATA, 4);
52
53 if (pcie_host_init(&s->host) < 0) {
54 return -1;
55 }
56 b = pci_bus_new(&s->host.pci.busdev.qdev, "pcie.0",
57 s->mch.pci_address_space, s->mch.address_space_io, 0);
58 s->host.pci.bus = b;
59 qdev_set_parent_bus(DEVICE(&s->mch), BUS(b));
60 qdev_init_nofail(DEVICE(&s->mch));
61
62 return 0;
63}
64
65static Property mch_props[] = {
66 DEFINE_PROP_UINT64("MCFG", Q35PCIHost, host.base_addr,
67 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
68 DEFINE_PROP_END_OF_LIST(),
69};
70
71static void q35_host_class_init(ObjectClass *klass, void *data)
72{
73 DeviceClass *dc = DEVICE_CLASS(klass);
74 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
75
76 k->init = q35_host_init;
77 dc->props = mch_props;
78}
79
80static void q35_host_initfn(Object *obj)
81{
82 Q35PCIHost *s = Q35_HOST_DEVICE(obj);
83
84 object_initialize(&s->mch, TYPE_MCH_PCI_DEVICE);
85 object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL);
86 qdev_prop_set_uint32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0));
87 qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false);
88}
89
90static const TypeInfo q35_host_info = {
91 .name = TYPE_Q35_HOST_DEVICE,
92 .parent = TYPE_PCIE_HOST_BRIDGE,
93 .instance_size = sizeof(Q35PCIHost),
94 .instance_init = q35_host_initfn,
95 .class_init = q35_host_class_init,
96};
97
98
99
100
101
102
103static void mch_update_pciexbar(MCHPCIState *mch)
104{
105 PCIDevice *pci_dev = &mch->d;
106 BusState *bus = qdev_get_parent_bus(&pci_dev->qdev);
107 DeviceState *qdev = bus->parent;
108 Q35PCIHost *s = Q35_HOST_DEVICE(qdev);
109
110 uint64_t pciexbar;
111 int enable;
112 uint64_t addr;
113 uint64_t addr_mask;
114 uint32_t length;
115
116 pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR);
117 enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN;
118 addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK;
119 switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) {
120 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M:
121 length = 256 * 1024 * 1024;
122 break;
123 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M:
124 length = 128 * 1024 * 1024;
125 addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK |
126 MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
127 break;
128 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M:
129 length = 64 * 1024 * 1024;
130 addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
131 break;
132 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD:
133 default:
134 enable = 0;
135 length = 0;
136 abort();
137 break;
138 }
139 addr = pciexbar & addr_mask;
140 pcie_host_mmcfg_update(&s->host, enable, addr, length);
141}
142
143
144static void mch_update_pam(MCHPCIState *mch)
145{
146 int i;
147
148 memory_region_transaction_begin();
149 for (i = 0; i < 13; i++) {
150 pam_update(&mch->pam_regions[i], i,
151 mch->d.config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]);
152 }
153 memory_region_transaction_commit();
154}
155
156
157static void mch_update_smram(MCHPCIState *mch)
158{
159 memory_region_transaction_begin();
160 smram_update(&mch->smram_region, mch->d.config[MCH_HOST_BRDIGE_SMRAM],
161 mch->smm_enabled);
162 memory_region_transaction_commit();
163}
164
165static void mch_set_smm(int smm, void *arg)
166{
167 MCHPCIState *mch = arg;
168
169 memory_region_transaction_begin();
170 smram_set_smm(&mch->smm_enabled, smm, mch->d.config[MCH_HOST_BRDIGE_SMRAM],
171 &mch->smram_region);
172 memory_region_transaction_commit();
173}
174
175static void mch_write_config(PCIDevice *d,
176 uint32_t address, uint32_t val, int len)
177{
178 MCHPCIState *mch = MCH_PCI_DEVICE(d);
179
180
181 pci_default_write_config(d, address, val, len);
182
183 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0,
184 MCH_HOST_BRIDGE_PAM_SIZE)) {
185 mch_update_pam(mch);
186 }
187
188 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR,
189 MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) {
190 mch_update_pciexbar(mch);
191 }
192
193 if (ranges_overlap(address, len, MCH_HOST_BRDIGE_SMRAM,
194 MCH_HOST_BRDIGE_SMRAM_SIZE)) {
195 mch_update_smram(mch);
196 }
197}
198
199static void mch_update(MCHPCIState *mch)
200{
201 mch_update_pciexbar(mch);
202 mch_update_pam(mch);
203 mch_update_smram(mch);
204}
205
206static int mch_post_load(void *opaque, int version_id)
207{
208 MCHPCIState *mch = opaque;
209 mch_update(mch);
210 return 0;
211}
212
213static const VMStateDescription vmstate_mch = {
214 .name = "mch",
215 .version_id = 1,
216 .minimum_version_id = 1,
217 .minimum_version_id_old = 1,
218 .post_load = mch_post_load,
219 .fields = (VMStateField []) {
220 VMSTATE_PCI_DEVICE(d, MCHPCIState),
221 VMSTATE_UINT8(smm_enabled, MCHPCIState),
222 VMSTATE_END_OF_LIST()
223 }
224};
225
226static void mch_reset(DeviceState *qdev)
227{
228 PCIDevice *d = PCI_DEVICE(qdev);
229 MCHPCIState *mch = MCH_PCI_DEVICE(d);
230
231 pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR,
232 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT);
233
234 d->config[MCH_HOST_BRDIGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT;
235
236 mch_update(mch);
237}
238
239static int mch_init(PCIDevice *d)
240{
241 int i;
242 hwaddr pci_hole64_size;
243 MCHPCIState *mch = MCH_PCI_DEVICE(d);
244
245
246 memory_region_init_alias(&mch->pci_hole, "pci-hole",
247 mch->pci_address_space,
248 mch->below_4g_mem_size,
249 0x100000000ULL - mch->below_4g_mem_size);
250 memory_region_add_subregion(mch->system_memory, mch->below_4g_mem_size,
251 &mch->pci_hole);
252 pci_hole64_size = (sizeof(hwaddr) == 4 ? 0 :
253 ((uint64_t)1 << 62));
254 memory_region_init_alias(&mch->pci_hole_64bit, "pci-hole64",
255 mch->pci_address_space,
256 0x100000000ULL + mch->above_4g_mem_size,
257 pci_hole64_size);
258 if (pci_hole64_size) {
259 memory_region_add_subregion(mch->system_memory,
260 0x100000000ULL + mch->above_4g_mem_size,
261 &mch->pci_hole_64bit);
262 }
263
264 cpu_smm_register(&mch_set_smm, mch);
265 memory_region_init_alias(&mch->smram_region, "smram-region",
266 mch->pci_address_space, 0xa0000, 0x20000);
267 memory_region_add_subregion_overlap(mch->system_memory, 0xa0000,
268 &mch->smram_region, 1);
269 memory_region_set_enabled(&mch->smram_region, false);
270 init_pam(mch->ram_memory, mch->system_memory, mch->pci_address_space,
271 &mch->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
272 for (i = 0; i < 12; ++i) {
273 init_pam(mch->ram_memory, mch->system_memory, mch->pci_address_space,
274 &mch->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
275 PAM_EXPAN_SIZE);
276 }
277 return 0;
278}
279
280static void mch_class_init(ObjectClass *klass, void *data)
281{
282 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
283 DeviceClass *dc = DEVICE_CLASS(klass);
284
285 k->init = mch_init;
286 k->config_write = mch_write_config;
287 dc->reset = mch_reset;
288 dc->desc = "Host bridge";
289 dc->vmsd = &vmstate_mch;
290 k->vendor_id = PCI_VENDOR_ID_INTEL;
291 k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH;
292 k->revision = MCH_HOST_BRIDGE_REVISION_DEFUALT;
293 k->class_id = PCI_CLASS_BRIDGE_HOST;
294}
295
296static const TypeInfo mch_info = {
297 .name = TYPE_MCH_PCI_DEVICE,
298 .parent = TYPE_PCI_DEVICE,
299 .instance_size = sizeof(MCHPCIState),
300 .class_init = mch_class_init,
301};
302
303static void q35_register(void)
304{
305 type_register_static(&mch_info);
306 type_register_static(&q35_host_info);
307}
308
309type_init(q35_register);
310
