qemu/hw/display/pl110.c
<<
>>
Prefs
   1/*
   2 * Arm PrimeCell PL110 Color LCD Controller
   3 *
   4 * Copyright (c) 2005-2009 CodeSourcery.
   5 * Written by Paul Brook
   6 *
   7 * This code is licensed under the GNU LGPL
   8 */
   9
  10#include "hw/sysbus.h"
  11#include "ui/console.h"
  12#include "framebuffer.h"
  13#include "ui/pixel_ops.h"
  14
  15#define PL110_CR_EN   0x001
  16#define PL110_CR_BGR  0x100
  17#define PL110_CR_BEBO 0x200
  18#define PL110_CR_BEPO 0x400
  19#define PL110_CR_PWR  0x800
  20
  21enum pl110_bppmode
  22{
  23    BPP_1,
  24    BPP_2,
  25    BPP_4,
  26    BPP_8,
  27    BPP_16,
  28    BPP_32,
  29    BPP_16_565, /* PL111 only */
  30    BPP_12      /* PL111 only */
  31};
  32
  33
  34/* The Versatile/PB uses a slightly modified PL110 controller.  */
  35enum pl110_version
  36{
  37    PL110,
  38    PL110_VERSATILE,
  39    PL111
  40};
  41
  42typedef struct {
  43    SysBusDevice busdev;
  44    MemoryRegion iomem;
  45    QemuConsole *con;
  46
  47    int version;
  48    uint32_t timing[4];
  49    uint32_t cr;
  50    uint32_t upbase;
  51    uint32_t lpbase;
  52    uint32_t int_status;
  53    uint32_t int_mask;
  54    int cols;
  55    int rows;
  56    enum pl110_bppmode bpp;
  57    int invalidate;
  58    uint32_t mux_ctrl;
  59    uint32_t palette[256];
  60    uint32_t raw_palette[128];
  61    qemu_irq irq;
  62} pl110_state;
  63
  64static int vmstate_pl110_post_load(void *opaque, int version_id);
  65
  66static const VMStateDescription vmstate_pl110 = {
  67    .name = "pl110",
  68    .version_id = 2,
  69    .minimum_version_id = 1,
  70    .post_load = vmstate_pl110_post_load,
  71    .fields = (VMStateField[]) {
  72        VMSTATE_INT32(version, pl110_state),
  73        VMSTATE_UINT32_ARRAY(timing, pl110_state, 4),
  74        VMSTATE_UINT32(cr, pl110_state),
  75        VMSTATE_UINT32(upbase, pl110_state),
  76        VMSTATE_UINT32(lpbase, pl110_state),
  77        VMSTATE_UINT32(int_status, pl110_state),
  78        VMSTATE_UINT32(int_mask, pl110_state),
  79        VMSTATE_INT32(cols, pl110_state),
  80        VMSTATE_INT32(rows, pl110_state),
  81        VMSTATE_UINT32(bpp, pl110_state),
  82        VMSTATE_INT32(invalidate, pl110_state),
  83        VMSTATE_UINT32_ARRAY(palette, pl110_state, 256),
  84        VMSTATE_UINT32_ARRAY(raw_palette, pl110_state, 128),
  85        VMSTATE_UINT32_V(mux_ctrl, pl110_state, 2),
  86        VMSTATE_END_OF_LIST()
  87    }
  88};
  89
  90static const unsigned char pl110_id[] =
  91{ 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
  92
  93/* The Arm documentation (DDI0224C) says the CLDC on the Versatile board
  94   has a different ID.  However Linux only looks for the normal ID.  */
  95#if 0
  96static const unsigned char pl110_versatile_id[] =
  97{ 0x93, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
  98#else
  99#define pl110_versatile_id pl110_id
 100#endif
 101
 102static const unsigned char pl111_id[] = {
 103    0x11, 0x11, 0x24, 0x00, 0x0d, 0xf0, 0x05, 0xb1
 104};
 105
 106/* Indexed by pl110_version */
 107static const unsigned char *idregs[] = {
 108    pl110_id,
 109    pl110_versatile_id,
 110    pl111_id
 111};
 112
 113#define BITS 8
 114#include "pl110_template.h"
 115#define BITS 15
 116#include "pl110_template.h"
 117#define BITS 16
 118#include "pl110_template.h"
 119#define BITS 24
 120#include "pl110_template.h"
 121#define BITS 32
 122#include "pl110_template.h"
 123
 124static int pl110_enabled(pl110_state *s)
 125{
 126  return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR);
 127}
 128
 129static void pl110_update_display(void *opaque)
 130{
 131    pl110_state *s = (pl110_state *)opaque;
 132    DisplaySurface *surface = qemu_console_surface(s->con);
 133    drawfn* fntable;
 134    drawfn fn;
 135    int dest_width;
 136    int src_width;
 137    int bpp_offset;
 138    int first;
 139    int last;
 140
 141    if (!pl110_enabled(s))
 142        return;
 143
 144    switch (surface_bits_per_pixel(surface)) {
 145    case 0:
 146        return;
 147    case 8:
 148        fntable = pl110_draw_fn_8;
 149        dest_width = 1;
 150        break;
 151    case 15:
 152        fntable = pl110_draw_fn_15;
 153        dest_width = 2;
 154        break;
 155    case 16:
 156        fntable = pl110_draw_fn_16;
 157        dest_width = 2;
 158        break;
 159    case 24:
 160        fntable = pl110_draw_fn_24;
 161        dest_width = 3;
 162        break;
 163    case 32:
 164        fntable = pl110_draw_fn_32;
 165        dest_width = 4;
 166        break;
 167    default:
 168        fprintf(stderr, "pl110: Bad color depth\n");
 169        exit(1);
 170    }
 171    if (s->cr & PL110_CR_BGR)
 172        bpp_offset = 0;
 173    else
 174        bpp_offset = 24;
 175
 176    if ((s->version != PL111) && (s->bpp == BPP_16)) {
 177        /* The PL110's native 16 bit mode is 5551; however
 178         * most boards with a PL110 implement an external
 179         * mux which allows bits to be reshuffled to give
 180         * 565 format. The mux is typically controlled by
 181         * an external system register.
 182         * This is controlled by a GPIO input pin
 183         * so boards can wire it up to their register.
 184         *
 185         * The PL111 straightforwardly implements both
 186         * 5551 and 565 under control of the bpp field
 187         * in the LCDControl register.
 188         */
 189        switch (s->mux_ctrl) {
 190        case 3: /* 565 BGR */
 191            bpp_offset = (BPP_16_565 - BPP_16);
 192            break;
 193        case 1: /* 5551 */
 194            break;
 195        case 0: /* 888; also if we have loaded vmstate from an old version */
 196        case 2: /* 565 RGB */
 197        default:
 198            /* treat as 565 but honour BGR bit */
 199            bpp_offset += (BPP_16_565 - BPP_16);
 200            break;
 201        }
 202    }
 203
 204    if (s->cr & PL110_CR_BEBO)
 205        fn = fntable[s->bpp + 8 + bpp_offset];
 206    else if (s->cr & PL110_CR_BEPO)
 207        fn = fntable[s->bpp + 16 + bpp_offset];
 208    else
 209        fn = fntable[s->bpp + bpp_offset];
 210
 211    src_width = s->cols;
 212    switch (s->bpp) {
 213    case BPP_1:
 214        src_width >>= 3;
 215        break;
 216    case BPP_2:
 217        src_width >>= 2;
 218        break;
 219    case BPP_4:
 220        src_width >>= 1;
 221        break;
 222    case BPP_8:
 223        break;
 224    case BPP_16:
 225    case BPP_16_565:
 226    case BPP_12:
 227        src_width <<= 1;
 228        break;
 229    case BPP_32:
 230        src_width <<= 2;
 231        break;
 232    }
 233    dest_width *= s->cols;
 234    first = 0;
 235    framebuffer_update_display(surface, sysbus_address_space(&s->busdev),
 236                               s->upbase, s->cols, s->rows,
 237                               src_width, dest_width, 0,
 238                               s->invalidate,
 239                               fn, s->palette,
 240                               &first, &last);
 241    if (first >= 0) {
 242        dpy_gfx_update(s->con, 0, first, s->cols, last - first + 1);
 243    }
 244    s->invalidate = 0;
 245}
 246
 247static void pl110_invalidate_display(void * opaque)
 248{
 249    pl110_state *s = (pl110_state *)opaque;
 250    s->invalidate = 1;
 251    if (pl110_enabled(s)) {
 252        qemu_console_resize(s->con, s->cols, s->rows);
 253    }
 254}
 255
 256static void pl110_update_palette(pl110_state *s, int n)
 257{
 258    DisplaySurface *surface = qemu_console_surface(s->con);
 259    int i;
 260    uint32_t raw;
 261    unsigned int r, g, b;
 262
 263    raw = s->raw_palette[n];
 264    n <<= 1;
 265    for (i = 0; i < 2; i++) {
 266        r = (raw & 0x1f) << 3;
 267        raw >>= 5;
 268        g = (raw & 0x1f) << 3;
 269        raw >>= 5;
 270        b = (raw & 0x1f) << 3;
 271        /* The I bit is ignored.  */
 272        raw >>= 6;
 273        switch (surface_bits_per_pixel(surface)) {
 274        case 8:
 275            s->palette[n] = rgb_to_pixel8(r, g, b);
 276            break;
 277        case 15:
 278            s->palette[n] = rgb_to_pixel15(r, g, b);
 279            break;
 280        case 16:
 281            s->palette[n] = rgb_to_pixel16(r, g, b);
 282            break;
 283        case 24:
 284        case 32:
 285            s->palette[n] = rgb_to_pixel32(r, g, b);
 286            break;
 287        }
 288        n++;
 289    }
 290}
 291
 292static void pl110_resize(pl110_state *s, int width, int height)
 293{
 294    if (width != s->cols || height != s->rows) {
 295        if (pl110_enabled(s)) {
 296            qemu_console_resize(s->con, width, height);
 297        }
 298    }
 299    s->cols = width;
 300    s->rows = height;
 301}
 302
 303/* Update interrupts.  */
 304static void pl110_update(pl110_state *s)
 305{
 306  /* TODO: Implement interrupts.  */
 307}
 308
 309static uint64_t pl110_read(void *opaque, hwaddr offset,
 310                           unsigned size)
 311{
 312    pl110_state *s = (pl110_state *)opaque;
 313
 314    if (offset >= 0xfe0 && offset < 0x1000) {
 315        return idregs[s->version][(offset - 0xfe0) >> 2];
 316    }
 317    if (offset >= 0x200 && offset < 0x400) {
 318        return s->raw_palette[(offset - 0x200) >> 2];
 319    }
 320    switch (offset >> 2) {
 321    case 0: /* LCDTiming0 */
 322        return s->timing[0];
 323    case 1: /* LCDTiming1 */
 324        return s->timing[1];
 325    case 2: /* LCDTiming2 */
 326        return s->timing[2];
 327    case 3: /* LCDTiming3 */
 328        return s->timing[3];
 329    case 4: /* LCDUPBASE */
 330        return s->upbase;
 331    case 5: /* LCDLPBASE */
 332        return s->lpbase;
 333    case 6: /* LCDIMSC */
 334        if (s->version != PL110) {
 335            return s->cr;
 336        }
 337        return s->int_mask;
 338    case 7: /* LCDControl */
 339        if (s->version != PL110) {
 340            return s->int_mask;
 341        }
 342        return s->cr;
 343    case 8: /* LCDRIS */
 344        return s->int_status;
 345    case 9: /* LCDMIS */
 346        return s->int_status & s->int_mask;
 347    case 11: /* LCDUPCURR */
 348        /* TODO: Implement vertical refresh.  */
 349        return s->upbase;
 350    case 12: /* LCDLPCURR */
 351        return s->lpbase;
 352    default:
 353        qemu_log_mask(LOG_GUEST_ERROR,
 354                      "pl110_read: Bad offset %x\n", (int)offset);
 355        return 0;
 356    }
 357}
 358
 359static void pl110_write(void *opaque, hwaddr offset,
 360                        uint64_t val, unsigned size)
 361{
 362    pl110_state *s = (pl110_state *)opaque;
 363    int n;
 364
 365    /* For simplicity invalidate the display whenever a control register
 366       is written to.  */
 367    s->invalidate = 1;
 368    if (offset >= 0x200 && offset < 0x400) {
 369        /* Palette.  */
 370        n = (offset - 0x200) >> 2;
 371        s->raw_palette[(offset - 0x200) >> 2] = val;
 372        pl110_update_palette(s, n);
 373        return;
 374    }
 375    switch (offset >> 2) {
 376    case 0: /* LCDTiming0 */
 377        s->timing[0] = val;
 378        n = ((val & 0xfc) + 4) * 4;
 379        pl110_resize(s, n, s->rows);
 380        break;
 381    case 1: /* LCDTiming1 */
 382        s->timing[1] = val;
 383        n = (val & 0x3ff) + 1;
 384        pl110_resize(s, s->cols, n);
 385        break;
 386    case 2: /* LCDTiming2 */
 387        s->timing[2] = val;
 388        break;
 389    case 3: /* LCDTiming3 */
 390        s->timing[3] = val;
 391        break;
 392    case 4: /* LCDUPBASE */
 393        s->upbase = val;
 394        break;
 395    case 5: /* LCDLPBASE */
 396        s->lpbase = val;
 397        break;
 398    case 6: /* LCDIMSC */
 399        if (s->version != PL110) {
 400            goto control;
 401        }
 402    imsc:
 403        s->int_mask = val;
 404        pl110_update(s);
 405        break;
 406    case 7: /* LCDControl */
 407        if (s->version != PL110) {
 408            goto imsc;
 409        }
 410    control:
 411        s->cr = val;
 412        s->bpp = (val >> 1) & 7;
 413        if (pl110_enabled(s)) {
 414            qemu_console_resize(s->con, s->cols, s->rows);
 415        }
 416        break;
 417    case 10: /* LCDICR */
 418        s->int_status &= ~val;
 419        pl110_update(s);
 420        break;
 421    default:
 422        qemu_log_mask(LOG_GUEST_ERROR,
 423                      "pl110_write: Bad offset %x\n", (int)offset);
 424    }
 425}
 426
 427static const MemoryRegionOps pl110_ops = {
 428    .read = pl110_read,
 429    .write = pl110_write,
 430    .endianness = DEVICE_NATIVE_ENDIAN,
 431};
 432
 433static void pl110_mux_ctrl_set(void *opaque, int line, int level)
 434{
 435    pl110_state *s = (pl110_state *)opaque;
 436    s->mux_ctrl = level;
 437}
 438
 439static int vmstate_pl110_post_load(void *opaque, int version_id)
 440{
 441    pl110_state *s = opaque;
 442    /* Make sure we redraw, and at the right size */
 443    pl110_invalidate_display(s);
 444    return 0;
 445}
 446
 447static const GraphicHwOps pl110_gfx_ops = {
 448    .invalidate  = pl110_invalidate_display,
 449    .gfx_update  = pl110_update_display,
 450};
 451
 452static int pl110_init(SysBusDevice *dev)
 453{
 454    pl110_state *s = FROM_SYSBUS(pl110_state, dev);
 455
 456    memory_region_init_io(&s->iomem, &pl110_ops, s, "pl110", 0x1000);
 457    sysbus_init_mmio(dev, &s->iomem);
 458    sysbus_init_irq(dev, &s->irq);
 459    qdev_init_gpio_in(&s->busdev.qdev, pl110_mux_ctrl_set, 1);
 460    s->con = graphic_console_init(DEVICE(dev), &pl110_gfx_ops, s);
 461    return 0;
 462}
 463
 464static int pl110_versatile_init(SysBusDevice *dev)
 465{
 466    pl110_state *s = FROM_SYSBUS(pl110_state, dev);
 467    s->version = PL110_VERSATILE;
 468    return pl110_init(dev);
 469}
 470
 471static int pl111_init(SysBusDevice *dev)
 472{
 473    pl110_state *s = FROM_SYSBUS(pl110_state, dev);
 474    s->version = PL111;
 475    return pl110_init(dev);
 476}
 477
 478static void pl110_class_init(ObjectClass *klass, void *data)
 479{
 480    DeviceClass *dc = DEVICE_CLASS(klass);
 481    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 482
 483    k->init = pl110_init;
 484    dc->no_user = 1;
 485    dc->vmsd = &vmstate_pl110;
 486}
 487
 488static const TypeInfo pl110_info = {
 489    .name          = "pl110",
 490    .parent        = TYPE_SYS_BUS_DEVICE,
 491    .instance_size = sizeof(pl110_state),
 492    .class_init    = pl110_class_init,
 493};
 494
 495static void pl110_versatile_class_init(ObjectClass *klass, void *data)
 496{
 497    DeviceClass *dc = DEVICE_CLASS(klass);
 498    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 499
 500    k->init = pl110_versatile_init;
 501    dc->no_user = 1;
 502    dc->vmsd = &vmstate_pl110;
 503}
 504
 505static const TypeInfo pl110_versatile_info = {
 506    .name          = "pl110_versatile",
 507    .parent        = TYPE_SYS_BUS_DEVICE,
 508    .instance_size = sizeof(pl110_state),
 509    .class_init    = pl110_versatile_class_init,
 510};
 511
 512static void pl111_class_init(ObjectClass *klass, void *data)
 513{
 514    DeviceClass *dc = DEVICE_CLASS(klass);
 515    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 516
 517    k->init = pl111_init;
 518    dc->no_user = 1;
 519    dc->vmsd = &vmstate_pl110;
 520}
 521
 522static const TypeInfo pl111_info = {
 523    .name          = "pl111",
 524    .parent        = TYPE_SYS_BUS_DEVICE,
 525    .instance_size = sizeof(pl110_state),
 526    .class_init    = pl111_class_init,
 527};
 528
 529static void pl110_register_types(void)
 530{
 531    type_register_static(&pl110_info);
 532    type_register_static(&pl110_versatile_info);
 533    type_register_static(&pl111_info);
 534}
 535
 536type_init(pl110_register_types)
 537