LXR qemu/target-mips/cpu.c

   1/*
   2 * QEMU MIPS CPU
   3 *
   4 * Copyright (c) 2012 SUSE LINUX Products GmbH
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2.1 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see
  18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19 */
  20
  21#include "cpu.h"
  22#include "qemu-common.h"
  23
  24
  25/* CPUClass::reset() */
  26static void mips_cpu_reset(CPUState *s)
  27{
  28    MIPSCPU *cpu = MIPS_CPU(s);
  29    MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
  30    CPUMIPSState *env = &cpu->env;
  31
  32    if (qemu_loglevel_mask(CPU_LOG_RESET)) {
  33        qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
  34        log_cpu_state(env, 0);
  35    }
  36
  37    mcc->parent_reset(s);
  38
  39    memset(env, 0, offsetof(CPUMIPSState, breakpoints));
  40    tlb_flush(env, 1);
  41
  42    cpu_state_reset(env);
  43}
  44
  45static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
  46{
  47    MIPSCPU *cpu = MIPS_CPU(dev);
  48    MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev);
  49
  50    cpu_reset(CPU(cpu));
  51    qemu_init_vcpu(&cpu->env);
  52
  53    mcc->parent_realize(dev, errp);
  54}
  55
  56static void mips_cpu_initfn(Object *obj)
  57{
  58    CPUState *cs = CPU(obj);
  59    MIPSCPU *cpu = MIPS_CPU(obj);
  60    CPUMIPSState *env = &cpu->env;
  61
  62    cs->env_ptr = env;
  63    cpu_exec_init(env);
  64
  65    if (tcg_enabled()) {
  66        mips_tcg_init();
  67    }
  68}
  69
  70static void mips_cpu_class_init(ObjectClass *c, void *data)
  71{
  72    MIPSCPUClass *mcc = MIPS_CPU_CLASS(c);
  73    CPUClass *cc = CPU_CLASS(c);
  74    DeviceClass *dc = DEVICE_CLASS(c);
  75
  76    mcc->parent_realize = dc->realize;
  77    dc->realize = mips_cpu_realizefn;
  78
  79    mcc->parent_reset = cc->reset;
  80    cc->reset = mips_cpu_reset;
  81
  82    cc->do_interrupt = mips_cpu_do_interrupt;
  83}
  84
  85static const TypeInfo mips_cpu_type_info = {
  86    .name = TYPE_MIPS_CPU,
  87    .parent = TYPE_CPU,
  88    .instance_size = sizeof(MIPSCPU),
  89    .instance_init = mips_cpu_initfn,
  90    .abstract = false,
  91    .class_size = sizeof(MIPSCPUClass),
  92    .class_init = mips_cpu_class_init,
  93};
  94
  95static void mips_cpu_register_types(void)
  96{
  97    type_register_static(&mips_cpu_type_info);
  98}
  99
 100type_init(mips_cpu_register_types)
 101