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28#include "cpu.h"
29#include "exec/exec-all.h"
30#include "exec/gdbstub.h"
31#include "qemu/host-utils.h"
32#if !defined(CONFIG_USER_ONLY)
33#include "hw/loader.h"
34#endif
35
36static struct XtensaConfigList *xtensa_cores;
37
38void xtensa_register_core(XtensaConfigList *node)
39{
40 node->next = xtensa_cores;
41 xtensa_cores = node;
42}
43
44static uint32_t check_hw_breakpoints(CPUXtensaState *env)
45{
46 unsigned i;
47
48 for (i = 0; i < env->config->ndbreak; ++i) {
49 if (env->cpu_watchpoint[i] &&
50 env->cpu_watchpoint[i]->flags & BP_WATCHPOINT_HIT) {
51 return DEBUGCAUSE_DB | (i << DEBUGCAUSE_DBNUM_SHIFT);
52 }
53 }
54 return 0;
55}
56
57void xtensa_breakpoint_handler(CPUXtensaState *env)
58{
59 if (env->watchpoint_hit) {
60 if (env->watchpoint_hit->flags & BP_CPU) {
61 uint32_t cause;
62
63 env->watchpoint_hit = NULL;
64 cause = check_hw_breakpoints(env);
65 if (cause) {
66 debug_exception_env(env, cause);
67 }
68 cpu_resume_from_signal(env, NULL);
69 }
70 }
71}
72
73XtensaCPU *cpu_xtensa_init(const char *cpu_model)
74{
75 XtensaCPU *cpu;
76 CPUXtensaState *env;
77 const XtensaConfig *config = NULL;
78 XtensaConfigList *core = xtensa_cores;
79
80 for (; core; core = core->next)
81 if (strcmp(core->config->name, cpu_model) == 0) {
82 config = core->config;
83 break;
84 }
85
86 if (config == NULL) {
87 return NULL;
88 }
89
90 cpu = XTENSA_CPU(object_new(TYPE_XTENSA_CPU));
91 env = &cpu->env;
92 env->config = config;
93
94 xtensa_irq_init(env);
95
96 object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
97
98 return cpu;
99}
100
101
102void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf)
103{
104 XtensaConfigList *core = xtensa_cores;
105 cpu_fprintf(f, "Available CPUs:\n");
106 for (; core; core = core->next) {
107 cpu_fprintf(f, " %s\n", core->config->name);
108 }
109}
110
111hwaddr cpu_get_phys_page_debug(CPUXtensaState *env, target_ulong addr)
112{
113 uint32_t paddr;
114 uint32_t page_size;
115 unsigned access;
116
117 if (xtensa_get_physical_addr(env, false, addr, 0, 0,
118 &paddr, &page_size, &access) == 0) {
119 return paddr;
120 }
121 if (xtensa_get_physical_addr(env, false, addr, 2, 0,
122 &paddr, &page_size, &access) == 0) {
123 return paddr;
124 }
125 return ~0;
126}
127
128static uint32_t relocated_vector(CPUXtensaState *env, uint32_t vector)
129{
130 if (xtensa_option_enabled(env->config,
131 XTENSA_OPTION_RELOCATABLE_VECTOR)) {
132 return vector - env->config->vecbase + env->sregs[VECBASE];
133 } else {
134 return vector;
135 }
136}
137
138
139
140
141
142
143
144static void handle_interrupt(CPUXtensaState *env)
145{
146 int level = env->pending_irq_level;
147
148 if (level > xtensa_get_cintlevel(env) &&
149 level <= env->config->nlevel &&
150 (env->config->level_mask[level] &
151 env->sregs[INTSET] &
152 env->sregs[INTENABLE])) {
153 if (level > 1) {
154 env->sregs[EPC1 + level - 1] = env->pc;
155 env->sregs[EPS2 + level - 2] = env->sregs[PS];
156 env->sregs[PS] =
157 (env->sregs[PS] & ~PS_INTLEVEL) | level | PS_EXCM;
158 env->pc = relocated_vector(env,
159 env->config->interrupt_vector[level]);
160 } else {
161 env->sregs[EXCCAUSE] = LEVEL1_INTERRUPT_CAUSE;
162
163 if (env->sregs[PS] & PS_EXCM) {
164 if (env->config->ndepc) {
165 env->sregs[DEPC] = env->pc;
166 } else {
167 env->sregs[EPC1] = env->pc;
168 }
169 env->exception_index = EXC_DOUBLE;
170 } else {
171 env->sregs[EPC1] = env->pc;
172 env->exception_index =
173 (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL;
174 }
175 env->sregs[PS] |= PS_EXCM;
176 }
177 env->exception_taken = 1;
178 }
179}
180
181void xtensa_cpu_do_interrupt(CPUState *cs)
182{
183 XtensaCPU *cpu = XTENSA_CPU(cs);
184 CPUXtensaState *env = &cpu->env;
185
186 if (env->exception_index == EXC_IRQ) {
187 qemu_log_mask(CPU_LOG_INT,
188 "%s(EXC_IRQ) level = %d, cintlevel = %d, "
189 "pc = %08x, a0 = %08x, ps = %08x, "
190 "intset = %08x, intenable = %08x, "
191 "ccount = %08x\n",
192 __func__, env->pending_irq_level, xtensa_get_cintlevel(env),
193 env->pc, env->regs[0], env->sregs[PS],
194 env->sregs[INTSET], env->sregs[INTENABLE],
195 env->sregs[CCOUNT]);
196 handle_interrupt(env);
197 }
198
199 switch (env->exception_index) {
200 case EXC_WINDOW_OVERFLOW4:
201 case EXC_WINDOW_UNDERFLOW4:
202 case EXC_WINDOW_OVERFLOW8:
203 case EXC_WINDOW_UNDERFLOW8:
204 case EXC_WINDOW_OVERFLOW12:
205 case EXC_WINDOW_UNDERFLOW12:
206 case EXC_KERNEL:
207 case EXC_USER:
208 case EXC_DOUBLE:
209 case EXC_DEBUG:
210 qemu_log_mask(CPU_LOG_INT, "%s(%d) "
211 "pc = %08x, a0 = %08x, ps = %08x, ccount = %08x\n",
212 __func__, env->exception_index,
213 env->pc, env->regs[0], env->sregs[PS], env->sregs[CCOUNT]);
214 if (env->config->exception_vector[env->exception_index]) {
215 env->pc = relocated_vector(env,
216 env->config->exception_vector[env->exception_index]);
217 env->exception_taken = 1;
218 } else {
219 qemu_log("%s(pc = %08x) bad exception_index: %d\n",
220 __func__, env->pc, env->exception_index);
221 }
222 break;
223
224 case EXC_IRQ:
225 break;
226
227 default:
228 qemu_log("%s(pc = %08x) unknown exception_index: %d\n",
229 __func__, env->pc, env->exception_index);
230 break;
231 }
232 check_interrupts(env);
233}
234
235static void reset_tlb_mmu_all_ways(CPUXtensaState *env,
236 const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
237{
238 unsigned wi, ei;
239
240 for (wi = 0; wi < tlb->nways; ++wi) {
241 for (ei = 0; ei < tlb->way_size[wi]; ++ei) {
242 entry[wi][ei].asid = 0;
243 entry[wi][ei].variable = true;
244 }
245 }
246}
247
248static void reset_tlb_mmu_ways56(CPUXtensaState *env,
249 const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
250{
251 if (!tlb->varway56) {
252 static const xtensa_tlb_entry way5[] = {
253 {
254 .vaddr = 0xd0000000,
255 .paddr = 0,
256 .asid = 1,
257 .attr = 7,
258 .variable = false,
259 }, {
260 .vaddr = 0xd8000000,
261 .paddr = 0,
262 .asid = 1,
263 .attr = 3,
264 .variable = false,
265 }
266 };
267 static const xtensa_tlb_entry way6[] = {
268 {
269 .vaddr = 0xe0000000,
270 .paddr = 0xf0000000,
271 .asid = 1,
272 .attr = 7,
273 .variable = false,
274 }, {
275 .vaddr = 0xf0000000,
276 .paddr = 0xf0000000,
277 .asid = 1,
278 .attr = 3,
279 .variable = false,
280 }
281 };
282 memcpy(entry[5], way5, sizeof(way5));
283 memcpy(entry[6], way6, sizeof(way6));
284 } else {
285 uint32_t ei;
286 for (ei = 0; ei < 8; ++ei) {
287 entry[6][ei].vaddr = ei << 29;
288 entry[6][ei].paddr = ei << 29;
289 entry[6][ei].asid = 1;
290 entry[6][ei].attr = 3;
291 }
292 }
293}
294
295static void reset_tlb_region_way0(CPUXtensaState *env,
296 xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE])
297{
298 unsigned ei;
299
300 for (ei = 0; ei < 8; ++ei) {
301 entry[0][ei].vaddr = ei << 29;
302 entry[0][ei].paddr = ei << 29;
303 entry[0][ei].asid = 1;
304 entry[0][ei].attr = 2;
305 entry[0][ei].variable = true;
306 }
307}
308
309void reset_mmu(CPUXtensaState *env)
310{
311 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
312 env->sregs[RASID] = 0x04030201;
313 env->sregs[ITLBCFG] = 0;
314 env->sregs[DTLBCFG] = 0;
315 env->autorefill_idx = 0;
316 reset_tlb_mmu_all_ways(env, &env->config->itlb, env->itlb);
317 reset_tlb_mmu_all_ways(env, &env->config->dtlb, env->dtlb);
318 reset_tlb_mmu_ways56(env, &env->config->itlb, env->itlb);
319 reset_tlb_mmu_ways56(env, &env->config->dtlb, env->dtlb);
320 } else {
321 reset_tlb_region_way0(env, env->itlb);
322 reset_tlb_region_way0(env, env->dtlb);
323 }
324}
325
326static unsigned get_ring(const CPUXtensaState *env, uint8_t asid)
327{
328 unsigned i;
329 for (i = 0; i < 4; ++i) {
330 if (((env->sregs[RASID] >> i * 8) & 0xff) == asid) {
331 return i;
332 }
333 }
334 return 0xff;
335}
336
337
338
339
340
341
342
343
344
345
346int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
347 uint32_t *pwi, uint32_t *pei, uint8_t *pring)
348{
349 const xtensa_tlb *tlb = dtlb ?
350 &env->config->dtlb : &env->config->itlb;
351 const xtensa_tlb_entry (*entry)[MAX_TLB_WAY_SIZE] = dtlb ?
352 env->dtlb : env->itlb;
353
354 int nhits = 0;
355 unsigned wi;
356
357 for (wi = 0; wi < tlb->nways; ++wi) {
358 uint32_t vpn;
359 uint32_t ei;
360 split_tlb_entry_spec_way(env, addr, dtlb, &vpn, wi, &ei);
361 if (entry[wi][ei].vaddr == vpn && entry[wi][ei].asid) {
362 unsigned ring = get_ring(env, entry[wi][ei].asid);
363 if (ring < 4) {
364 if (++nhits > 1) {
365 return dtlb ?
366 LOAD_STORE_TLB_MULTI_HIT_CAUSE :
367 INST_TLB_MULTI_HIT_CAUSE;
368 }
369 *pwi = wi;
370 *pei = ei;
371 *pring = ring;
372 }
373 }
374 }
375 return nhits ? 0 :
376 (dtlb ? LOAD_STORE_TLB_MISS_CAUSE : INST_TLB_MISS_CAUSE);
377}
378
379
380
381
382
383static unsigned mmu_attr_to_access(uint32_t attr)
384{
385 unsigned access = 0;
386
387 if (attr < 12) {
388 access |= PAGE_READ;
389 if (attr & 0x1) {
390 access |= PAGE_EXEC;
391 }
392 if (attr & 0x2) {
393 access |= PAGE_WRITE;
394 }
395
396 switch (attr & 0xc) {
397 case 0:
398 access |= PAGE_CACHE_BYPASS;
399 break;
400
401 case 4:
402 access |= PAGE_CACHE_WB;
403 break;
404
405 case 8:
406 access |= PAGE_CACHE_WT;
407 break;
408 }
409 } else if (attr == 13) {
410 access |= PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE;
411 }
412 return access;
413}
414
415
416
417
418
419static unsigned region_attr_to_access(uint32_t attr)
420{
421 static const unsigned access[16] = {
422 [0] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT,
423 [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT,
424 [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS,
425 [3] = PAGE_EXEC | PAGE_CACHE_WB,
426 [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
427 [5] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
428 [14] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE,
429 };
430
431 return access[attr & 0xf];
432}
433
434
435
436
437
438static unsigned cacheattr_attr_to_access(uint32_t attr)
439{
440 static const unsigned access[16] = {
441 [0] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT,
442 [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT,
443 [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS,
444 [3] = PAGE_EXEC | PAGE_CACHE_WB,
445 [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB,
446 [14] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE,
447 };
448
449 return access[attr & 0xf];
450}
451
452static bool is_access_granted(unsigned access, int is_write)
453{
454 switch (is_write) {
455 case 0:
456 return access & PAGE_READ;
457
458 case 1:
459 return access & PAGE_WRITE;
460
461 case 2:
462 return access & PAGE_EXEC;
463
464 default:
465 return 0;
466 }
467}
468
469static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte);
470
471static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb,
472 uint32_t vaddr, int is_write, int mmu_idx,
473 uint32_t *paddr, uint32_t *page_size, unsigned *access,
474 bool may_lookup_pt)
475{
476 bool dtlb = is_write != 2;
477 uint32_t wi;
478 uint32_t ei;
479 uint8_t ring;
480 uint32_t vpn;
481 uint32_t pte;
482 const xtensa_tlb_entry *entry = NULL;
483 xtensa_tlb_entry tmp_entry;
484 int ret = xtensa_tlb_lookup(env, vaddr, dtlb, &wi, &ei, &ring);
485
486 if ((ret == INST_TLB_MISS_CAUSE || ret == LOAD_STORE_TLB_MISS_CAUSE) &&
487 may_lookup_pt && get_pte(env, vaddr, &pte) == 0) {
488 ring = (pte >> 4) & 0x3;
489 wi = 0;
490 split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, wi, &ei);
491
492 if (update_tlb) {
493 wi = ++env->autorefill_idx & 0x3;
494 xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, pte);
495 env->sregs[EXCVADDR] = vaddr;
496 qemu_log("%s: autorefill(%08x): %08x -> %08x\n",
497 __func__, vaddr, vpn, pte);
498 } else {
499 xtensa_tlb_set_entry_mmu(env, &tmp_entry, dtlb, wi, ei, vpn, pte);
500 entry = &tmp_entry;
501 }
502 ret = 0;
503 }
504 if (ret != 0) {
505 return ret;
506 }
507
508 if (entry == NULL) {
509 entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
510 }
511
512 if (ring < mmu_idx) {
513 return dtlb ?
514 LOAD_STORE_PRIVILEGE_CAUSE :
515 INST_FETCH_PRIVILEGE_CAUSE;
516 }
517
518 *access = mmu_attr_to_access(entry->attr) &
519 ~(dtlb ? PAGE_EXEC : PAGE_READ | PAGE_WRITE);
520 if (!is_access_granted(*access, is_write)) {
521 return dtlb ?
522 (is_write ?
523 STORE_PROHIBITED_CAUSE :
524 LOAD_PROHIBITED_CAUSE) :
525 INST_FETCH_PROHIBITED_CAUSE;
526 }
527
528 *paddr = entry->paddr | (vaddr & ~xtensa_tlb_get_addr_mask(env, dtlb, wi));
529 *page_size = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1;
530
531 return 0;
532}
533
534static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte)
535{
536 uint32_t paddr;
537 uint32_t page_size;
538 unsigned access;
539 uint32_t pt_vaddr =
540 (env->sregs[PTEVADDR] | (vaddr >> 10)) & 0xfffffffc;
541 int ret = get_physical_addr_mmu(env, false, pt_vaddr, 0, 0,
542 &paddr, &page_size, &access, false);
543
544 qemu_log("%s: trying autorefill(%08x) -> %08x\n", __func__,
545 vaddr, ret ? ~0 : paddr);
546
547 if (ret == 0) {
548 *pte = ldl_phys(paddr);
549 }
550 return ret;
551}
552
553static int get_physical_addr_region(CPUXtensaState *env,
554 uint32_t vaddr, int is_write, int mmu_idx,
555 uint32_t *paddr, uint32_t *page_size, unsigned *access)
556{
557 bool dtlb = is_write != 2;
558 uint32_t wi = 0;
559 uint32_t ei = (vaddr >> 29) & 0x7;
560 const xtensa_tlb_entry *entry =
561 xtensa_tlb_get_entry(env, dtlb, wi, ei);
562
563 *access = region_attr_to_access(entry->attr);
564 if (!is_access_granted(*access, is_write)) {
565 return dtlb ?
566 (is_write ?
567 STORE_PROHIBITED_CAUSE :
568 LOAD_PROHIBITED_CAUSE) :
569 INST_FETCH_PROHIBITED_CAUSE;
570 }
571
572 *paddr = entry->paddr | (vaddr & ~REGION_PAGE_MASK);
573 *page_size = ~REGION_PAGE_MASK + 1;
574
575 return 0;
576}
577
578
579
580
581
582
583
584int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
585 uint32_t vaddr, int is_write, int mmu_idx,
586 uint32_t *paddr, uint32_t *page_size, unsigned *access)
587{
588 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
589 return get_physical_addr_mmu(env, update_tlb,
590 vaddr, is_write, mmu_idx, paddr, page_size, access, true);
591 } else if (xtensa_option_bits_enabled(env->config,
592 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
593 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION))) {
594 return get_physical_addr_region(env, vaddr, is_write, mmu_idx,
595 paddr, page_size, access);
596 } else {
597 *paddr = vaddr;
598 *page_size = TARGET_PAGE_SIZE;
599 *access = cacheattr_attr_to_access(
600 env->sregs[CACHEATTR] >> ((vaddr & 0xe0000000) >> 27));
601 return 0;
602 }
603}
604
605static void dump_tlb(FILE *f, fprintf_function cpu_fprintf,
606 CPUXtensaState *env, bool dtlb)
607{
608 unsigned wi, ei;
609 const xtensa_tlb *conf =
610 dtlb ? &env->config->dtlb : &env->config->itlb;
611 unsigned (*attr_to_access)(uint32_t) =
612 xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) ?
613 mmu_attr_to_access : region_attr_to_access;
614
615 for (wi = 0; wi < conf->nways; ++wi) {
616 uint32_t sz = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1;
617 const char *sz_text;
618 bool print_header = true;
619
620 if (sz >= 0x100000) {
621 sz >>= 20;
622 sz_text = "MB";
623 } else {
624 sz >>= 10;
625 sz_text = "KB";
626 }
627
628 for (ei = 0; ei < conf->way_size[wi]; ++ei) {
629 const xtensa_tlb_entry *entry =
630 xtensa_tlb_get_entry(env, dtlb, wi, ei);
631
632 if (entry->asid) {
633 static const char * const cache_text[8] = {
634 [PAGE_CACHE_BYPASS >> PAGE_CACHE_SHIFT] = "Bypass",
635 [PAGE_CACHE_WT >> PAGE_CACHE_SHIFT] = "WT",
636 [PAGE_CACHE_WB >> PAGE_CACHE_SHIFT] = "WB",
637 [PAGE_CACHE_ISOLATE >> PAGE_CACHE_SHIFT] = "Isolate",
638 };
639 unsigned access = attr_to_access(entry->attr);
640 unsigned cache_idx = (access & PAGE_CACHE_MASK) >>
641 PAGE_CACHE_SHIFT;
642
643 if (print_header) {
644 print_header = false;
645 cpu_fprintf(f, "Way %u (%d %s)\n", wi, sz, sz_text);
646 cpu_fprintf(f,
647 "\tVaddr Paddr ASID Attr RWX Cache\n"
648 "\t---------- ---------- ---- ---- --- -------\n");
649 }
650 cpu_fprintf(f,
651 "\t0x%08x 0x%08x 0x%02x 0x%02x %c%c%c %-7s\n",
652 entry->vaddr,
653 entry->paddr,
654 entry->asid,
655 entry->attr,
656 (access & PAGE_READ) ? 'R' : '-',
657 (access & PAGE_WRITE) ? 'W' : '-',
658 (access & PAGE_EXEC) ? 'X' : '-',
659 cache_text[cache_idx] ? cache_text[cache_idx] :
660 "Invalid");
661 }
662 }
663 }
664}
665
666void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env)
667{
668 if (xtensa_option_bits_enabled(env->config,
669 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
670 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION) |
671 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU))) {
672
673 cpu_fprintf(f, "ITLB:\n");
674 dump_tlb(f, cpu_fprintf, env, false);
675 cpu_fprintf(f, "\nDTLB:\n");
676 dump_tlb(f, cpu_fprintf, env, true);
677 } else {
678 cpu_fprintf(f, "No TLB for this CPU core\n");
679 }
680}
681
