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63#include <hw/hw.h>
64#include <hw/pci/msi.h>
65#include <hw/i386/pc.h>
66#include <hw/pci/pci.h>
67#include <hw/isa/isa.h>
68#include "block/block.h"
69#include "sysemu/dma.h"
70
71#include <hw/ide/pci.h>
72#include <hw/ide/ahci.h>
73
74#define ICH9_SATA_CAP_OFFSET 0xA8
75
76#define ICH9_IDP_BAR 4
77#define ICH9_MEM_BAR 5
78
79#define ICH9_IDP_INDEX 0x10
80#define ICH9_IDP_INDEX_LOG2 0x04
81
82static const VMStateDescription vmstate_ich9_ahci = {
83 .name = "ich9_ahci",
84 .unmigratable = 1,
85 .version_id = 1,
86 .fields = (VMStateField []) {
87 VMSTATE_PCI_DEVICE(parent_obj, AHCIPCIState),
88 VMSTATE_AHCI(ahci, AHCIPCIState),
89 VMSTATE_END_OF_LIST()
90 },
91};
92
93static void pci_ich9_reset(DeviceState *dev)
94{
95 AHCIPCIState *d = ICH_AHCI(dev);
96
97 ahci_reset(&d->ahci);
98}
99
100static int pci_ich9_ahci_init(PCIDevice *dev)
101{
102 struct AHCIPCIState *d;
103 int sata_cap_offset;
104 uint8_t *sata_cap;
105 d = ICH_AHCI(dev);
106
107 ahci_init(&d->ahci, DEVICE(dev), pci_get_address_space(dev), 6);
108
109 pci_config_set_prog_interface(dev->config, AHCI_PROGMODE_MAJOR_REV_1);
110
111 dev->config[PCI_CACHE_LINE_SIZE] = 0x08;
112 dev->config[PCI_LATENCY_TIMER] = 0x00;
113 pci_config_set_interrupt_pin(dev->config, 1);
114
115
116 dev->config[0x90] = 1 << 6;
117
118 msi_init(dev, 0x50, 1, true, false);
119 d->ahci.irq = dev->irq[0];
120
121 pci_register_bar(dev, ICH9_IDP_BAR, PCI_BASE_ADDRESS_SPACE_IO,
122 &d->ahci.idp);
123 pci_register_bar(dev, ICH9_MEM_BAR, PCI_BASE_ADDRESS_SPACE_MEMORY,
124 &d->ahci.mem);
125
126 sata_cap_offset = pci_add_capability(dev, PCI_CAP_ID_SATA,
127 ICH9_SATA_CAP_OFFSET, SATA_CAP_SIZE);
128 if (sata_cap_offset < 0) {
129 return sata_cap_offset;
130 }
131
132 sata_cap = dev->config + sata_cap_offset;
133 pci_set_word(sata_cap + SATA_CAP_REV, 0x10);
134 pci_set_long(sata_cap + SATA_CAP_BAR,
135 (ICH9_IDP_BAR + 0x4) | (ICH9_IDP_INDEX_LOG2 << 4));
136 d->ahci.idp_offset = ICH9_IDP_INDEX;
137
138 return 0;
139}
140
141static void pci_ich9_uninit(PCIDevice *dev)
142{
143 struct AHCIPCIState *d;
144 d = ICH_AHCI(dev);
145
146 msi_uninit(dev);
147 ahci_uninit(&d->ahci);
148}
149
150static void ich_ahci_class_init(ObjectClass *klass, void *data)
151{
152 DeviceClass *dc = DEVICE_CLASS(klass);
153 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
154
155 k->init = pci_ich9_ahci_init;
156 k->exit = pci_ich9_uninit;
157 k->vendor_id = PCI_VENDOR_ID_INTEL;
158 k->device_id = PCI_DEVICE_ID_INTEL_82801IR;
159 k->revision = 0x02;
160 k->class_id = PCI_CLASS_STORAGE_SATA;
161 dc->vmsd = &vmstate_ich9_ahci;
162 dc->reset = pci_ich9_reset;
163 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
164}
165
166static const TypeInfo ich_ahci_info = {
167 .name = TYPE_ICH9_AHCI,
168 .parent = TYPE_PCI_DEVICE,
169 .instance_size = sizeof(AHCIPCIState),
170 .class_init = ich_ahci_class_init,
171};
172
173static void ich_ahci_register_types(void)
174{
175 type_register_static(&ich_ahci_info);
176}
177
178type_init(ich_ahci_register_types)
179
