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24#include "hw/hw.h"
25#include "hw/sysbus.h"
26#include "sysemu/sysemu.h"
27#include "trace.h"
28#include "qemu/error-report.h"
29#include "sysemu/blockdev.h"
30#include "hw/sd.h"
31
32enum {
33 ENABLE_CMD_TX = (1<<0),
34 ENABLE_CMD_RX = (1<<1),
35 ENABLE_DAT_TX = (1<<2),
36 ENABLE_DAT_RX = (1<<3),
37};
38
39enum {
40 PENDING_CMD_TX = (1<<0),
41 PENDING_CMD_RX = (1<<1),
42 PENDING_DAT_TX = (1<<2),
43 PENDING_DAT_RX = (1<<3),
44};
45
46enum {
47 START_CMD_TX = (1<<0),
48 START_DAT_RX = (1<<1),
49};
50
51enum {
52 R_CLK2XDIV = 0,
53 R_ENABLE,
54 R_PENDING,
55 R_START,
56 R_CMD,
57 R_DAT,
58 R_MAX
59};
60
61#define TYPE_MILKYMIST_MEMCARD "milkymist-memcard"
62#define MILKYMIST_MEMCARD(obj) \
63 OBJECT_CHECK(MilkymistMemcardState, (obj), TYPE_MILKYMIST_MEMCARD)
64
65struct MilkymistMemcardState {
66 SysBusDevice parent_obj;
67
68 MemoryRegion regs_region;
69 SDState *card;
70
71 int command_write_ptr;
72 int response_read_ptr;
73 int response_len;
74 int ignore_next_cmd;
75 int enabled;
76 uint8_t command[6];
77 uint8_t response[17];
78 uint32_t regs[R_MAX];
79};
80typedef struct MilkymistMemcardState MilkymistMemcardState;
81
82static void update_pending_bits(MilkymistMemcardState *s)
83{
84
85 s->regs[R_PENDING] = 0;
86
87 if (s->regs[R_ENABLE] & ENABLE_CMD_RX) {
88 s->regs[R_PENDING] |= PENDING_CMD_RX;
89 }
90 if (s->regs[R_ENABLE] & ENABLE_DAT_RX) {
91 s->regs[R_PENDING] |= PENDING_DAT_RX;
92 }
93}
94
95static void memcard_sd_command(MilkymistMemcardState *s)
96{
97 SDRequest req;
98
99 req.cmd = s->command[0] & 0x3f;
100 req.arg = (s->command[1] << 24) | (s->command[2] << 16)
101 | (s->command[3] << 8) | s->command[4];
102 req.crc = s->command[5];
103
104 s->response[0] = req.cmd;
105 s->response_len = sd_do_command(s->card, &req, s->response+1);
106 s->response_read_ptr = 0;
107
108 if (s->response_len == 16) {
109
110 s->response[0] = 0x3f;
111 s->response_len += 1;
112 } else if (s->response_len == 4) {
113
114 s->response[5] = 0;
115 s->response_len += 2;
116 }
117
118 if (req.cmd == 0) {
119
120
121 s->ignore_next_cmd = 1;
122 }
123}
124
125static uint64_t memcard_read(void *opaque, hwaddr addr,
126 unsigned size)
127{
128 MilkymistMemcardState *s = opaque;
129 uint32_t r = 0;
130
131 addr >>= 2;
132 switch (addr) {
133 case R_CMD:
134 if (!s->enabled) {
135 r = 0xff;
136 } else {
137 r = s->response[s->response_read_ptr++];
138 if (s->response_read_ptr > s->response_len) {
139 error_report("milkymist_memcard: "
140 "read more cmd bytes than available. Clipping.");
141 s->response_read_ptr = 0;
142 }
143 }
144 break;
145 case R_DAT:
146 if (!s->enabled) {
147 r = 0xffffffff;
148 } else {
149 r = 0;
150 r |= sd_read_data(s->card) << 24;
151 r |= sd_read_data(s->card) << 16;
152 r |= sd_read_data(s->card) << 8;
153 r |= sd_read_data(s->card);
154 }
155 break;
156 case R_CLK2XDIV:
157 case R_ENABLE:
158 case R_PENDING:
159 case R_START:
160 r = s->regs[addr];
161 break;
162
163 default:
164 error_report("milkymist_memcard: read access to unknown register 0x"
165 TARGET_FMT_plx, addr << 2);
166 break;
167 }
168
169 trace_milkymist_memcard_memory_read(addr << 2, r);
170
171 return r;
172}
173
174static void memcard_write(void *opaque, hwaddr addr, uint64_t value,
175 unsigned size)
176{
177 MilkymistMemcardState *s = opaque;
178
179 trace_milkymist_memcard_memory_write(addr, value);
180
181 addr >>= 2;
182 switch (addr) {
183 case R_PENDING:
184
185 s->regs[R_PENDING] &= ~(value & (PENDING_CMD_RX | PENDING_DAT_RX));
186 update_pending_bits(s);
187 break;
188 case R_CMD:
189 if (!s->enabled) {
190 break;
191 }
192 if (s->ignore_next_cmd) {
193 s->ignore_next_cmd = 0;
194 break;
195 }
196 s->command[s->command_write_ptr] = value & 0xff;
197 s->command_write_ptr = (s->command_write_ptr + 1) % 6;
198 if (s->command_write_ptr == 0) {
199 memcard_sd_command(s);
200 }
201 break;
202 case R_DAT:
203 if (!s->enabled) {
204 break;
205 }
206 sd_write_data(s->card, (value >> 24) & 0xff);
207 sd_write_data(s->card, (value >> 16) & 0xff);
208 sd_write_data(s->card, (value >> 8) & 0xff);
209 sd_write_data(s->card, value & 0xff);
210 break;
211 case R_ENABLE:
212 s->regs[addr] = value;
213 update_pending_bits(s);
214 break;
215 case R_CLK2XDIV:
216 case R_START:
217 s->regs[addr] = value;
218 break;
219
220 default:
221 error_report("milkymist_memcard: write access to unknown register 0x"
222 TARGET_FMT_plx, addr << 2);
223 break;
224 }
225}
226
227static const MemoryRegionOps memcard_mmio_ops = {
228 .read = memcard_read,
229 .write = memcard_write,
230 .valid = {
231 .min_access_size = 4,
232 .max_access_size = 4,
233 },
234 .endianness = DEVICE_NATIVE_ENDIAN,
235};
236
237static void milkymist_memcard_reset(DeviceState *d)
238{
239 MilkymistMemcardState *s = MILKYMIST_MEMCARD(d);
240 int i;
241
242 s->command_write_ptr = 0;
243 s->response_read_ptr = 0;
244 s->response_len = 0;
245
246 for (i = 0; i < R_MAX; i++) {
247 s->regs[i] = 0;
248 }
249}
250
251static int milkymist_memcard_init(SysBusDevice *dev)
252{
253 MilkymistMemcardState *s = MILKYMIST_MEMCARD(dev);
254 DriveInfo *dinfo;
255
256 dinfo = drive_get_next(IF_SD);
257 s->card = sd_init(dinfo ? dinfo->bdrv : NULL, false);
258 s->enabled = dinfo ? bdrv_is_inserted(dinfo->bdrv) : 0;
259
260 memory_region_init_io(&s->regs_region, OBJECT(s), &memcard_mmio_ops, s,
261 "milkymist-memcard", R_MAX * 4);
262 sysbus_init_mmio(dev, &s->regs_region);
263
264 return 0;
265}
266
267static const VMStateDescription vmstate_milkymist_memcard = {
268 .name = "milkymist-memcard",
269 .version_id = 1,
270 .minimum_version_id = 1,
271 .minimum_version_id_old = 1,
272 .fields = (VMStateField[]) {
273 VMSTATE_INT32(command_write_ptr, MilkymistMemcardState),
274 VMSTATE_INT32(response_read_ptr, MilkymistMemcardState),
275 VMSTATE_INT32(response_len, MilkymistMemcardState),
276 VMSTATE_INT32(ignore_next_cmd, MilkymistMemcardState),
277 VMSTATE_INT32(enabled, MilkymistMemcardState),
278 VMSTATE_UINT8_ARRAY(command, MilkymistMemcardState, 6),
279 VMSTATE_UINT8_ARRAY(response, MilkymistMemcardState, 17),
280 VMSTATE_UINT32_ARRAY(regs, MilkymistMemcardState, R_MAX),
281 VMSTATE_END_OF_LIST()
282 }
283};
284
285static void milkymist_memcard_class_init(ObjectClass *klass, void *data)
286{
287 DeviceClass *dc = DEVICE_CLASS(klass);
288 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
289
290 k->init = milkymist_memcard_init;
291 dc->reset = milkymist_memcard_reset;
292 dc->vmsd = &vmstate_milkymist_memcard;
293}
294
295static const TypeInfo milkymist_memcard_info = {
296 .name = TYPE_MILKYMIST_MEMCARD,
297 .parent = TYPE_SYS_BUS_DEVICE,
298 .instance_size = sizeof(MilkymistMemcardState),
299 .class_init = milkymist_memcard_class_init,
300};
301
302static void milkymist_memcard_register_types(void)
303{
304 type_register_static(&milkymist_memcard_info);
305}
306
307type_init(milkymist_memcard_register_types)
308
