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22#include "cpu.h"
23#include "qemu-common.h"
24#include "migration/vmstate.h"
25
26
27static void superh_cpu_set_pc(CPUState *cs, vaddr value)
28{
29 SuperHCPU *cpu = SUPERH_CPU(cs);
30
31 cpu->env.pc = value;
32}
33
34static void superh_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
35{
36 SuperHCPU *cpu = SUPERH_CPU(cs);
37
38 cpu->env.pc = tb->pc;
39 cpu->env.flags = tb->flags;
40}
41
42
43static void superh_cpu_reset(CPUState *s)
44{
45 SuperHCPU *cpu = SUPERH_CPU(s);
46 SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu);
47 CPUSH4State *env = &cpu->env;
48
49 scc->parent_reset(s);
50
51 memset(env, 0, offsetof(CPUSH4State, breakpoints));
52 tlb_flush(env, 1);
53
54 env->pc = 0xA0000000;
55#if defined(CONFIG_USER_ONLY)
56 env->fpscr = FPSCR_PR;
57 set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
58#else
59 env->sr = SR_MD | SR_RB | SR_BL | SR_I3 | SR_I2 | SR_I1 | SR_I0;
60 env->fpscr = FPSCR_DN | FPSCR_RM_ZERO;
61 set_float_rounding_mode(float_round_to_zero, &env->fp_status);
62 set_flush_to_zero(1, &env->fp_status);
63#endif
64 set_default_nan_mode(1, &env->fp_status);
65}
66
67typedef struct SuperHCPUListState {
68 fprintf_function cpu_fprintf;
69 FILE *file;
70} SuperHCPUListState;
71
72
73static gint superh_cpu_list_compare(gconstpointer a, gconstpointer b)
74{
75 ObjectClass *class_a = (ObjectClass *)a;
76 ObjectClass *class_b = (ObjectClass *)b;
77 const char *name_a, *name_b;
78
79 name_a = object_class_get_name(class_a);
80 name_b = object_class_get_name(class_b);
81 return strcmp(name_a, name_b);
82}
83
84static void superh_cpu_list_entry(gpointer data, gpointer user_data)
85{
86 ObjectClass *oc = data;
87 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
88 SuperHCPUListState *s = user_data;
89
90 (*s->cpu_fprintf)(s->file, "%s\n",
91 scc->name);
92}
93
94void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf)
95{
96 SuperHCPUListState s = {
97 .cpu_fprintf = cpu_fprintf,
98 .file = f,
99 };
100 GSList *list;
101
102 list = object_class_get_list(TYPE_SUPERH_CPU, false);
103 list = g_slist_sort(list, superh_cpu_list_compare);
104 g_slist_foreach(list, superh_cpu_list_entry, &s);
105 g_slist_free(list);
106}
107
108static gint superh_cpu_name_compare(gconstpointer a, gconstpointer b)
109{
110 const SuperHCPUClass *scc = SUPERH_CPU_CLASS(a);
111 const char *name = b;
112
113 return strcasecmp(scc->name, name);
114}
115
116static ObjectClass *superh_cpu_class_by_name(const char *cpu_model)
117{
118 ObjectClass *oc;
119 GSList *list, *item;
120
121 if (cpu_model == NULL) {
122 return NULL;
123 }
124 if (strcasecmp(cpu_model, "any") == 0) {
125 return object_class_by_name(TYPE_SH7750R_CPU);
126 }
127
128 oc = object_class_by_name(cpu_model);
129 if (oc != NULL && object_class_dynamic_cast(oc, TYPE_SUPERH_CPU) != NULL
130 && !object_class_is_abstract(oc)) {
131 return oc;
132 }
133
134 oc = NULL;
135 list = object_class_get_list(TYPE_SUPERH_CPU, false);
136 item = g_slist_find_custom(list, cpu_model, superh_cpu_name_compare);
137 if (item != NULL) {
138 oc = item->data;
139 }
140 g_slist_free(list);
141 return oc;
142}
143
144SuperHCPU *cpu_sh4_init(const char *cpu_model)
145{
146 SuperHCPU *cpu;
147 CPUSH4State *env;
148 ObjectClass *oc;
149
150 oc = superh_cpu_class_by_name(cpu_model);
151 if (oc == NULL) {
152 return NULL;
153 }
154 cpu = SUPERH_CPU(object_new(object_class_get_name(oc)));
155 env = &cpu->env;
156 env->cpu_model_str = cpu_model;
157
158 object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
159
160 return cpu;
161}
162
163static void sh7750r_cpu_initfn(Object *obj)
164{
165 SuperHCPU *cpu = SUPERH_CPU(obj);
166 CPUSH4State *env = &cpu->env;
167
168 env->id = SH_CPU_SH7750R;
169 env->features = SH_FEATURE_BCR3_AND_BCR4;
170}
171
172static void sh7750r_class_init(ObjectClass *oc, void *data)
173{
174 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
175
176 scc->name = "SH7750R";
177 scc->pvr = 0x00050000;
178 scc->prr = 0x00000100;
179 scc->cvr = 0x00110000;
180}
181
182static const TypeInfo sh7750r_type_info = {
183 .name = TYPE_SH7750R_CPU,
184 .parent = TYPE_SUPERH_CPU,
185 .class_init = sh7750r_class_init,
186 .instance_init = sh7750r_cpu_initfn,
187};
188
189static void sh7751r_cpu_initfn(Object *obj)
190{
191 SuperHCPU *cpu = SUPERH_CPU(obj);
192 CPUSH4State *env = &cpu->env;
193
194 env->id = SH_CPU_SH7751R;
195 env->features = SH_FEATURE_BCR3_AND_BCR4;
196}
197
198static void sh7751r_class_init(ObjectClass *oc, void *data)
199{
200 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
201
202 scc->name = "SH7751R";
203 scc->pvr = 0x04050005;
204 scc->prr = 0x00000113;
205 scc->cvr = 0x00110000;
206}
207
208static const TypeInfo sh7751r_type_info = {
209 .name = TYPE_SH7751R_CPU,
210 .parent = TYPE_SUPERH_CPU,
211 .class_init = sh7751r_class_init,
212 .instance_init = sh7751r_cpu_initfn,
213};
214
215static void sh7785_cpu_initfn(Object *obj)
216{
217 SuperHCPU *cpu = SUPERH_CPU(obj);
218 CPUSH4State *env = &cpu->env;
219
220 env->id = SH_CPU_SH7785;
221 env->features = SH_FEATURE_SH4A;
222}
223
224static void sh7785_class_init(ObjectClass *oc, void *data)
225{
226 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
227
228 scc->name = "SH7785";
229 scc->pvr = 0x10300700;
230 scc->prr = 0x00000200;
231 scc->cvr = 0x71440211;
232}
233
234static const TypeInfo sh7785_type_info = {
235 .name = TYPE_SH7785_CPU,
236 .parent = TYPE_SUPERH_CPU,
237 .class_init = sh7785_class_init,
238 .instance_init = sh7785_cpu_initfn,
239};
240
241static void superh_cpu_realizefn(DeviceState *dev, Error **errp)
242{
243 CPUState *cs = CPU(dev);
244 SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev);
245
246 cpu_reset(cs);
247 qemu_init_vcpu(cs);
248
249 scc->parent_realize(dev, errp);
250}
251
252static void superh_cpu_initfn(Object *obj)
253{
254 CPUState *cs = CPU(obj);
255 SuperHCPU *cpu = SUPERH_CPU(obj);
256 CPUSH4State *env = &cpu->env;
257
258 cs->env_ptr = env;
259 cpu_exec_init(env);
260
261 env->movcal_backup_tail = &(env->movcal_backup);
262
263 if (tcg_enabled()) {
264 sh4_translate_init();
265 }
266}
267
268static const VMStateDescription vmstate_sh_cpu = {
269 .name = "cpu",
270 .unmigratable = 1,
271};
272
273static void superh_cpu_class_init(ObjectClass *oc, void *data)
274{
275 DeviceClass *dc = DEVICE_CLASS(oc);
276 CPUClass *cc = CPU_CLASS(oc);
277 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
278
279 scc->parent_realize = dc->realize;
280 dc->realize = superh_cpu_realizefn;
281
282 scc->parent_reset = cc->reset;
283 cc->reset = superh_cpu_reset;
284
285 cc->class_by_name = superh_cpu_class_by_name;
286 cc->do_interrupt = superh_cpu_do_interrupt;
287 cc->dump_state = superh_cpu_dump_state;
288 cc->set_pc = superh_cpu_set_pc;
289 cc->synchronize_from_tb = superh_cpu_synchronize_from_tb;
290 cc->gdb_read_register = superh_cpu_gdb_read_register;
291 cc->gdb_write_register = superh_cpu_gdb_write_register;
292#ifndef CONFIG_USER_ONLY
293 cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
294#endif
295 dc->vmsd = &vmstate_sh_cpu;
296 cc->gdb_num_core_regs = 59;
297}
298
299static const TypeInfo superh_cpu_type_info = {
300 .name = TYPE_SUPERH_CPU,
301 .parent = TYPE_CPU,
302 .instance_size = sizeof(SuperHCPU),
303 .instance_init = superh_cpu_initfn,
304 .abstract = true,
305 .class_size = sizeof(SuperHCPUClass),
306 .class_init = superh_cpu_class_init,
307};
308
309static void superh_cpu_register_types(void)
310{
311 type_register_static(&superh_cpu_type_info);
312 type_register_static(&sh7750r_type_info);
313 type_register_static(&sh7751r_type_info);
314 type_register_static(&sh7785_type_info);
315}
316
317type_init(superh_cpu_register_types)
318
