LXR qemu/hw/char/imx

   1/*
   2 * IMX31 UARTS
   3 *
   4 * Copyright (c) 2008 OKL
   5 * Originally Written by Hans Jiang
   6 * Copyright (c) 2011 NICTA Pty Ltd.
   7 *
   8 * This work is licensed under the terms of the GNU GPL, version 2 or later.
   9 * See the COPYING file in the top-level directory.
  10 *
  11 * This is a `bare-bones' implementation of the IMX series serial ports.
  12 * TODO:
  13 *  -- implement FIFOs.  The real hardware has 32 word transmit
  14 *                       and receive FIFOs; we currently use a 1-char buffer
  15 *  -- implement DMA
  16 *  -- implement BAUD-rate and modem lines, for when the backend
  17 *     is a real serial device.
  18 */
  19
  20#include "hw/hw.h"
  21#include "hw/sysbus.h"
  22#include "sysemu/sysemu.h"
  23#include "sysemu/char.h"
  24#include "hw/arm/imx.h"
  25
  26//#define DEBUG_SERIAL 1
  27#ifdef DEBUG_SERIAL
  28#define DPRINTF(fmt, args...) \
  29do { printf("imx_serial: " fmt , ##args); } while (0)
  30#else
  31#define DPRINTF(fmt, args...) do {} while (0)
  32#endif
  33
  34/*
  35 * Define to 1 for messages about attempts to
  36 * access unimplemented registers or similar.
  37 */
  38//#define DEBUG_IMPLEMENTATION 1
  39#ifdef DEBUG_IMPLEMENTATION
  40#  define IPRINTF(fmt, args...) \
  41    do  { fprintf(stderr, "imx_serial: " fmt, ##args); } while (0)
  42#else
  43#  define IPRINTF(fmt, args...) do {} while (0)
  44#endif
  45
  46#define TYPE_IMX_SERIAL "imx-serial"
  47#define IMX_SERIAL(obj) OBJECT_CHECK(IMXSerialState, (obj), TYPE_IMX_SERIAL)
  48
  49typedef struct IMXSerialState {
  50    SysBusDevice parent_obj;
  51
  52    MemoryRegion iomem;
  53    int32_t readbuff;
  54
  55    uint32_t usr1;
  56    uint32_t usr2;
  57    uint32_t ucr1;
  58    uint32_t ucr2;
  59    uint32_t uts1;
  60
  61    /*
  62     * The registers below are implemented just so that the
  63     * guest OS sees what it has written
  64     */
  65    uint32_t onems;
  66    uint32_t ufcr;
  67    uint32_t ubmr;
  68    uint32_t ubrc;
  69    uint32_t ucr3;
  70
  71    qemu_irq irq;
  72    CharDriverState *chr;
  73} IMXSerialState;
  74
  75static const VMStateDescription vmstate_imx_serial = {
  76    .name = "imx-serial",
  77    .version_id = 1,
  78    .minimum_version_id = 1,
  79    .minimum_version_id_old = 1,
  80    .fields = (VMStateField[]) {
  81        VMSTATE_INT32(readbuff, IMXSerialState),
  82        VMSTATE_UINT32(usr1, IMXSerialState),
  83        VMSTATE_UINT32(usr2, IMXSerialState),
  84        VMSTATE_UINT32(ucr1, IMXSerialState),
  85        VMSTATE_UINT32(uts1, IMXSerialState),
  86        VMSTATE_UINT32(onems, IMXSerialState),
  87        VMSTATE_UINT32(ufcr, IMXSerialState),
  88        VMSTATE_UINT32(ubmr, IMXSerialState),
  89        VMSTATE_UINT32(ubrc, IMXSerialState),
  90        VMSTATE_UINT32(ucr3, IMXSerialState),
  91        VMSTATE_END_OF_LIST()
  92    },
  93};
  94
  95
  96#define URXD_CHARRDY    (1<<15)   /* character read is valid */
  97#define URXD_ERR        (1<<14)   /* Character has error */
  98#define URXD_BRK        (1<<11)   /* Break received */
  99
 100#define USR1_PARTYER    (1<<15)   /* Parity Error */
 101#define USR1_RTSS       (1<<14)   /* RTS pin status */
 102#define USR1_TRDY       (1<<13)   /* Tx ready */
 103#define USR1_RTSD       (1<<12)   /* RTS delta: pin changed state */
 104#define USR1_ESCF       (1<<11)   /* Escape sequence interrupt */
 105#define USR1_FRAMERR    (1<<10)   /* Framing error  */
 106#define USR1_RRDY       (1<<9)    /* receiver ready */
 107#define USR1_AGTIM      (1<<8)    /* Aging timer interrupt */
 108#define USR1_DTRD       (1<<7)    /* DTR changed */
 109#define USR1_RXDS       (1<<6)    /* Receiver is idle */
 110#define USR1_AIRINT     (1<<5)    /* Aysnch IR interrupt */
 111#define USR1_AWAKE      (1<<4)    /* Falling edge detected on RXd pin */
 112
 113#define USR2_ADET       (1<<15)   /* Autobaud complete */
 114#define USR2_TXFE       (1<<14)   /* Transmit FIFO empty */
 115#define USR2_DTRF       (1<<13)   /* DTR/DSR transition */
 116#define USR2_IDLE       (1<<12)   /* UART has been idle for too long */
 117#define USR2_ACST       (1<<11)   /* Autobaud counter stopped */
 118#define USR2_RIDELT     (1<<10)   /* Ring Indicator delta */
 119#define USR2_RIIN       (1<<9)    /* Ring Indicator Input */
 120#define USR2_IRINT      (1<<8)    /* Serial Infrared Interrupt */
 121#define USR2_WAKE       (1<<7)    /* Start bit detected */
 122#define USR2_DCDDELT    (1<<6)    /* Data Carrier Detect delta */
 123#define USR2_DCDIN      (1<<5)    /* Data Carrier Detect Input */
 124#define USR2_RTSF       (1<<4)    /* RTS transition */
 125#define USR2_TXDC       (1<<3)    /* Transmission complete */
 126#define USR2_BRCD       (1<<2)    /* Break condition detected */
 127#define USR2_ORE        (1<<1)    /* Overrun error */
 128#define USR2_RDR        (1<<0)    /* Receive data ready */
 129
 130#define UCR1_TRDYEN     (1<<13)   /* Tx Ready Interrupt Enable */
 131#define UCR1_RRDYEN     (1<<9)    /* Rx Ready Interrupt Enable */
 132#define UCR1_TXMPTYEN   (1<<6)    /* Tx Empty Interrupt Enable */
 133#define UCR1_UARTEN     (1<<0)    /* UART Enable */
 134
 135#define UCR2_TXEN       (1<<2)    /* Transmitter enable */
 136#define UCR2_RXEN       (1<<1)    /* Receiver enable */
 137#define UCR2_SRST       (1<<0)    /* Reset complete */
 138
 139#define UTS1_TXEMPTY    (1<<6)
 140#define UTS1_RXEMPTY    (1<<5)
 141#define UTS1_TXFULL     (1<<4)
 142#define UTS1_RXFULL     (1<<3)
 143
 144static void imx_update(IMXSerialState *s)
 145{
 146    uint32_t flags;
 147
 148    flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY);
 149    if (!(s->ucr1 & UCR1_TXMPTYEN)) {
 150        flags &= ~USR1_TRDY;
 151    }
 152
 153    qemu_set_irq(s->irq, !!flags);
 154}
 155
 156static void imx_serial_reset(IMXSerialState *s)
 157{
 158
 159    s->usr1 = USR1_TRDY | USR1_RXDS;
 160    /*
 161     * Fake attachment of a terminal: assert RTS.
 162     */
 163    s->usr1 |= USR1_RTSS;
 164    s->usr2 = USR2_TXFE | USR2_TXDC | USR2_DCDIN;
 165    s->uts1 = UTS1_RXEMPTY | UTS1_TXEMPTY;
 166    s->ucr1 = 0;
 167    s->ucr2 = UCR2_SRST;
 168    s->ucr3 = 0x700;
 169    s->ubmr = 0;
 170    s->ubrc = 4;
 171    s->readbuff = URXD_ERR;
 172}
 173
 174static void imx_serial_reset_at_boot(DeviceState *dev)
 175{
 176    IMXSerialState *s = IMX_SERIAL(dev);
 177
 178    imx_serial_reset(s);
 179
 180    /*
 181     * enable the uart on boot, so messages from the linux decompresser
 182     * are visible.  On real hardware this is done by the boot rom
 183     * before anything else is loaded.
 184     */
 185    s->ucr1 = UCR1_UARTEN;
 186    s->ucr2 = UCR2_TXEN;
 187
 188}
 189
 190static uint64_t imx_serial_read(void *opaque, hwaddr offset,
 191                                unsigned size)
 192{
 193    IMXSerialState *s = (IMXSerialState *)opaque;
 194    uint32_t c;
 195
 196    DPRINTF("read(offset=%x)\n", offset >> 2);
 197    switch (offset >> 2) {
 198    case 0x0: /* URXD */
 199        c = s->readbuff;
 200        if (!(s->uts1 & UTS1_RXEMPTY)) {
 201            /* Character is valid */
 202            c |= URXD_CHARRDY;
 203            s->usr1 &= ~USR1_RRDY;
 204            s->usr2 &= ~USR2_RDR;
 205            s->uts1 |= UTS1_RXEMPTY;
 206            imx_update(s);
 207            qemu_chr_accept_input(s->chr);
 208        }
 209        return c;
 210
 211    case 0x20: /* UCR1 */
 212        return s->ucr1;
 213
 214    case 0x21: /* UCR2 */
 215        return s->ucr2;
 216
 217    case 0x25: /* USR1 */
 218        return s->usr1;
 219
 220    case 0x26: /* USR2 */
 221        return s->usr2;
 222
 223    case 0x2A: /* BRM Modulator */
 224        return s->ubmr;
 225
 226    case 0x2B: /* Baud Rate Count */
 227        return s->ubrc;
 228
 229    case 0x2d: /* Test register */
 230        return s->uts1;
 231
 232    case 0x24: /* UFCR */
 233        return s->ufcr;
 234
 235    case 0x2c:
 236        return s->onems;
 237
 238    case 0x22: /* UCR3 */
 239        return s->ucr3;
 240
 241    case 0x23: /* UCR4 */
 242    case 0x29: /* BRM Incremental */
 243        return 0x0; /* TODO */
 244
 245    default:
 246        IPRINTF("imx_serial_read: bad offset: 0x%x\n", (int)offset);
 247        return 0;
 248    }
 249}
 250
 251static void imx_serial_write(void *opaque, hwaddr offset,
 252                      uint64_t value, unsigned size)
 253{
 254    IMXSerialState *s = (IMXSerialState *)opaque;
 255    unsigned char ch;
 256
 257    DPRINTF("write(offset=%x, value = %x) to %s\n",
 258            offset >> 2,
 259            (unsigned int)value, s->chr ? s->chr->label : "NODEV");
 260
 261    switch (offset >> 2) {
 262    case 0x10: /* UTXD */
 263        ch = value;
 264        if (s->ucr2 & UCR2_TXEN) {
 265            if (s->chr) {
 266                qemu_chr_fe_write(s->chr, &ch, 1);
 267            }
 268            s->usr1 &= ~USR1_TRDY;
 269            imx_update(s);
 270            s->usr1 |= USR1_TRDY;
 271            imx_update(s);
 272        }
 273        break;
 274
 275    case 0x20: /* UCR1 */
 276        s->ucr1 = value & 0xffff;
 277        DPRINTF("write(ucr1=%x)\n", (unsigned int)value);
 278        imx_update(s);
 279        break;
 280
 281    case 0x21: /* UCR2 */
 282        /*
 283         * Only a few bits in control register 2 are implemented as yet.
 284         * If it's intended to use a real serial device as a back-end, this
 285         * register will have to be implemented more fully.
 286         */
 287        if (!(value & UCR2_SRST)) {
 288            imx_serial_reset(s);
 289            imx_update(s);
 290            value |= UCR2_SRST;
 291        }
 292        if (value & UCR2_RXEN) {
 293            if (!(s->ucr2 & UCR2_RXEN)) {
 294                qemu_chr_accept_input(s->chr);
 295            }
 296        }
 297        s->ucr2 = value & 0xffff;
 298        break;
 299
 300    case 0x25: /* USR1 */
 301        value &= USR1_AWAKE | USR1_AIRINT | USR1_DTRD | USR1_AGTIM |
 302            USR1_FRAMERR | USR1_ESCF | USR1_RTSD | USR1_PARTYER;
 303        s->usr1 &= ~value;
 304        break;
 305
 306    case 0x26: /* USR2 */
 307       /*
 308        * Writing 1 to some bits clears them; all other
 309        * values are ignored
 310        */
 311        value &= USR2_ADET | USR2_DTRF | USR2_IDLE | USR2_ACST |
 312            USR2_RIDELT | USR2_IRINT | USR2_WAKE |
 313            USR2_DCDDELT | USR2_RTSF | USR2_BRCD | USR2_ORE;
 314        s->usr2 &= ~value;
 315        break;
 316
 317        /*
 318         * Linux expects to see what it writes to these registers
 319         * We don't currently alter the baud rate
 320         */
 321    case 0x29: /* UBIR */
 322        s->ubrc = value & 0xffff;
 323        break;
 324
 325    case 0x2a: /* UBMR */
 326        s->ubmr = value & 0xffff;
 327        break;
 328
 329    case 0x2c: /* One ms reg */
 330        s->onems = value & 0xffff;
 331        break;
 332
 333    case 0x24: /* FIFO control register */
 334        s->ufcr = value & 0xffff;
 335        break;
 336
 337    case 0x22: /* UCR3 */
 338        s->ucr3 = value & 0xffff;
 339        break;
 340
 341    case 0x2d: /* UTS1 */
 342    case 0x23: /* UCR4 */
 343        IPRINTF("Unimplemented Register %x written to\n", offset >> 2);
 344        /* TODO */
 345        break;
 346
 347    default:
 348        IPRINTF("imx_serial_write: Bad offset 0x%x\n", (int)offset);
 349    }
 350}
 351
 352static int imx_can_receive(void *opaque)
 353{
 354    IMXSerialState *s = (IMXSerialState *)opaque;
 355    return !(s->usr1 & USR1_RRDY);
 356}
 357
 358static void imx_put_data(void *opaque, uint32_t value)
 359{
 360    IMXSerialState *s = (IMXSerialState *)opaque;
 361    DPRINTF("received char\n");
 362    s->usr1 |= USR1_RRDY;
 363    s->usr2 |= USR2_RDR;
 364    s->uts1 &= ~UTS1_RXEMPTY;
 365    s->readbuff = value;
 366    imx_update(s);
 367}
 368
 369static void imx_receive(void *opaque, const uint8_t *buf, int size)
 370{
 371    imx_put_data(opaque, *buf);
 372}
 373
 374static void imx_event(void *opaque, int event)
 375{
 376    if (event == CHR_EVENT_BREAK) {
 377        imx_put_data(opaque, URXD_BRK);
 378    }
 379}
 380
 381
 382static const struct MemoryRegionOps imx_serial_ops = {
 383    .read = imx_serial_read,
 384    .write = imx_serial_write,
 385    .endianness = DEVICE_NATIVE_ENDIAN,
 386};
 387
 388static int imx_serial_init(SysBusDevice *dev)
 389{
 390    IMXSerialState *s = IMX_SERIAL(dev);
 391
 392
 393    memory_region_init_io(&s->iomem, OBJECT(s), &imx_serial_ops, s,
 394                          "imx-serial", 0x1000);
 395    sysbus_init_mmio(dev, &s->iomem);
 396    sysbus_init_irq(dev, &s->irq);
 397
 398    if (s->chr) {
 399        qemu_chr_add_handlers(s->chr, imx_can_receive, imx_receive,
 400                              imx_event, s);
 401    } else {
 402        DPRINTF("No char dev for uart at 0x%lx\n",
 403                (unsigned long)s->iomem.ram_addr);
 404    }
 405
 406    return 0;
 407}
 408
 409void imx_serial_create(int uart, const hwaddr addr, qemu_irq irq)
 410{
 411    DeviceState *dev;
 412    SysBusDevice *bus;
 413    CharDriverState *chr;
 414    const char chr_name[] = "serial";
 415    char label[ARRAY_SIZE(chr_name) + 1];
 416
 417    dev = qdev_create(NULL, TYPE_IMX_SERIAL);
 418
 419    if (uart >= MAX_SERIAL_PORTS) {
 420        hw_error("Cannot assign uart %d: QEMU supports only %d ports\n",
 421                 uart, MAX_SERIAL_PORTS);
 422    }
 423    chr = serial_hds[uart];
 424    if (!chr) {
 425        snprintf(label, ARRAY_SIZE(label), "%s%d", chr_name, uart);
 426        chr = qemu_chr_new(label, "null", NULL);
 427        if (!(chr)) {
 428            hw_error("Can't assign serial port to imx-uart%d.\n", uart);
 429        }
 430    }
 431
 432    qdev_prop_set_chr(dev, "chardev", chr);
 433    bus = SYS_BUS_DEVICE(dev);
 434    qdev_init_nofail(dev);
 435    if (addr != (hwaddr)-1) {
 436        sysbus_mmio_map(bus, 0, addr);
 437    }
 438    sysbus_connect_irq(bus, 0, irq);
 439
 440}
 441
 442
 443static Property imx32_serial_properties[] = {
 444    DEFINE_PROP_CHR("chardev", IMXSerialState, chr),
 445    DEFINE_PROP_END_OF_LIST(),
 446};
 447
 448static void imx_serial_class_init(ObjectClass *klass, void *data)
 449{
 450    DeviceClass *dc = DEVICE_CLASS(klass);
 451    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 452
 453    k->init = imx_serial_init;
 454    dc->vmsd = &vmstate_imx_serial;
 455    dc->reset = imx_serial_reset_at_boot;
 456    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
 457    dc->desc = "i.MX series UART";
 458    dc->props = imx32_serial_properties;
 459}
 460
 461static const TypeInfo imx_serial_info = {
 462    .name = TYPE_IMX_SERIAL,
 463    .parent = TYPE_SYS_BUS_DEVICE,
 464    .instance_size = sizeof(IMXSerialState),
 465    .class_init = imx_serial_class_init,
 466};
 467
 468static void imx_serial_register_types(void)
 469{
 470    type_register_static(&imx_serial_info);
 471}
 472
 473type_init(imx_serial_register_types)
 474