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25#include "hw/hw.h"
26#include "hw/i386/pc.h"
27#include "hw/pci/pci.h"
28#include "hw/pci/pci_host.h"
29#include "hw/isa/isa.h"
30#include "hw/sysbus.h"
31#include "qemu/range.h"
32#include "hw/xen/xen.h"
33#include "hw/pci-host/pam.h"
34#include "sysemu/sysemu.h"
35#include "hw/i386/ioapic.h"
36#include "qapi/visitor.h"
37
38
39
40
41
42
43#define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost"
44#define I440FX_PCI_HOST_BRIDGE(obj) \
45 OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX_PCI_HOST_BRIDGE)
46
47typedef struct I440FXState {
48 PCIHostState parent_obj;
49 PcPciInfo pci_info;
50 uint64_t pci_hole64_size;
51 uint32_t short_root_bus;
52} I440FXState;
53
54#define PIIX_NUM_PIC_IRQS 16
55#define PIIX_NUM_PIRQS 4ULL
56#define XEN_PIIX_NUM_PIRQS 128ULL
57#define PIIX_PIRQC 0x60
58
59
60
61
62
63#define RCR_IOPORT 0xcf9
64
65typedef struct PIIX3State {
66 PCIDevice dev;
67
68
69
70
71
72
73
74
75
76
77#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
78#error "unable to encode pic state in 64bit in pic_levels."
79#endif
80 uint64_t pic_levels;
81
82 qemu_irq *pic;
83
84
85 int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
86
87
88 uint8_t rcr;
89
90
91 MemoryRegion rcr_mem;
92} PIIX3State;
93
94#define TYPE_I440FX_PCI_DEVICE "i440FX"
95#define I440FX_PCI_DEVICE(obj) \
96 OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE)
97
98struct PCII440FXState {
99
100 PCIDevice parent_obj;
101
102
103 MemoryRegion *system_memory;
104 MemoryRegion *pci_address_space;
105 MemoryRegion *ram_memory;
106 MemoryRegion pci_hole;
107 MemoryRegion pci_hole_64bit;
108 PAMMemoryRegion pam_regions[13];
109 MemoryRegion smram_region;
110 uint8_t smm_enabled;
111};
112
113
114#define I440FX_PAM 0x59
115#define I440FX_PAM_SIZE 7
116#define I440FX_SMRAM 0x72
117
118static void piix3_set_irq(void *opaque, int pirq, int level);
119static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
120static void piix3_write_config_xen(PCIDevice *dev,
121 uint32_t address, uint32_t val, int len);
122
123
124
125
126static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
127{
128 int slot_addend;
129 slot_addend = (pci_dev->devfn >> 3) - 1;
130 return (pci_intx + slot_addend) & 3;
131}
132
133static void i440fx_update_memory_mappings(PCII440FXState *d)
134{
135 int i;
136 PCIDevice *pd = PCI_DEVICE(d);
137
138 memory_region_transaction_begin();
139 for (i = 0; i < 13; i++) {
140 pam_update(&d->pam_regions[i], i,
141 pd->config[I440FX_PAM + ((i + 1) / 2)]);
142 }
143 smram_update(&d->smram_region, pd->config[I440FX_SMRAM], d->smm_enabled);
144 memory_region_transaction_commit();
145}
146
147static void i440fx_set_smm(int val, void *arg)
148{
149 PCII440FXState *d = arg;
150 PCIDevice *pd = PCI_DEVICE(d);
151
152 memory_region_transaction_begin();
153 smram_set_smm(&d->smm_enabled, val, pd->config[I440FX_SMRAM],
154 &d->smram_region);
155 memory_region_transaction_commit();
156}
157
158
159static void i440fx_write_config(PCIDevice *dev,
160 uint32_t address, uint32_t val, int len)
161{
162 PCII440FXState *d = I440FX_PCI_DEVICE(dev);
163
164
165 pci_default_write_config(dev, address, val, len);
166 if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
167 range_covers_byte(address, len, I440FX_SMRAM)) {
168 i440fx_update_memory_mappings(d);
169 }
170}
171
172static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
173{
174 PCII440FXState *d = opaque;
175 PCIDevice *pd = PCI_DEVICE(d);
176 int ret, i;
177
178 ret = pci_device_load(pd, f);
179 if (ret < 0)
180 return ret;
181 i440fx_update_memory_mappings(d);
182 qemu_get_8s(f, &d->smm_enabled);
183
184 if (version_id == 2) {
185 for (i = 0; i < PIIX_NUM_PIRQS; i++) {
186 qemu_get_be32(f);
187 }
188 }
189
190 return 0;
191}
192
193static int i440fx_post_load(void *opaque, int version_id)
194{
195 PCII440FXState *d = opaque;
196
197 i440fx_update_memory_mappings(d);
198 return 0;
199}
200
201static const VMStateDescription vmstate_i440fx = {
202 .name = "I440FX",
203 .version_id = 3,
204 .minimum_version_id = 3,
205 .minimum_version_id_old = 1,
206 .load_state_old = i440fx_load_old,
207 .post_load = i440fx_post_load,
208 .fields = (VMStateField []) {
209 VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
210 VMSTATE_UINT8(smm_enabled, PCII440FXState),
211 VMSTATE_END_OF_LIST()
212 }
213};
214
215static void i440fx_pcihost_get_pci_hole_start(Object *obj, Visitor *v,
216 void *opaque, const char *name,
217 Error **errp)
218{
219 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
220 uint32_t value = s->pci_info.w32.begin;
221
222 visit_type_uint32(v, &value, name, errp);
223}
224
225static void i440fx_pcihost_get_pci_hole_end(Object *obj, Visitor *v,
226 void *opaque, const char *name,
227 Error **errp)
228{
229 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
230 uint32_t value = s->pci_info.w32.end;
231
232 visit_type_uint32(v, &value, name, errp);
233}
234
235static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v,
236 void *opaque, const char *name,
237 Error **errp)
238{
239 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
240
241 visit_type_uint64(v, &s->pci_info.w64.begin, name, errp);
242}
243
244static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v,
245 void *opaque, const char *name,
246 Error **errp)
247{
248 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
249
250 visit_type_uint64(v, &s->pci_info.w64.end, name, errp);
251}
252
253static void i440fx_pcihost_initfn(Object *obj)
254{
255 PCIHostState *s = PCI_HOST_BRIDGE(obj);
256 I440FXState *d = I440FX_PCI_HOST_BRIDGE(obj);
257
258 memory_region_init_io(&s->conf_mem, obj, &pci_host_conf_le_ops, s,
259 "pci-conf-idx", 4);
260 memory_region_init_io(&s->data_mem, obj, &pci_host_data_le_ops, s,
261 "pci-conf-data", 4);
262
263 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "int",
264 i440fx_pcihost_get_pci_hole_start,
265 NULL, NULL, NULL, NULL);
266
267 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "int",
268 i440fx_pcihost_get_pci_hole_end,
269 NULL, NULL, NULL, NULL);
270
271 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "int",
272 i440fx_pcihost_get_pci_hole64_start,
273 NULL, NULL, NULL, NULL);
274
275 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "int",
276 i440fx_pcihost_get_pci_hole64_end,
277 NULL, NULL, NULL, NULL);
278
279 d->pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS;
280}
281
282static void i440fx_pcihost_realize(DeviceState *dev, Error **errp)
283{
284 PCIHostState *s = PCI_HOST_BRIDGE(dev);
285 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
286
287 sysbus_add_io(sbd, 0xcf8, &s->conf_mem);
288 sysbus_init_ioports(sbd, 0xcf8, 4);
289
290 sysbus_add_io(sbd, 0xcfc, &s->data_mem);
291 sysbus_init_ioports(sbd, 0xcfc, 4);
292}
293
294static int i440fx_initfn(PCIDevice *dev)
295{
296 PCII440FXState *d = I440FX_PCI_DEVICE(dev);
297
298 dev->config[I440FX_SMRAM] = 0x02;
299
300 cpu_smm_register(&i440fx_set_smm, d);
301 return 0;
302}
303
304PCIBus *i440fx_init(PCII440FXState **pi440fx_state,
305 int *piix3_devfn,
306 ISABus **isa_bus, qemu_irq *pic,
307 MemoryRegion *address_space_mem,
308 MemoryRegion *address_space_io,
309 ram_addr_t ram_size,
310 hwaddr pci_hole_start,
311 hwaddr pci_hole_size,
312 ram_addr_t above_4g_mem_size,
313 MemoryRegion *pci_address_space,
314 MemoryRegion *ram_memory)
315{
316 DeviceState *dev;
317 PCIBus *b;
318 PCIDevice *d;
319 PCIHostState *s;
320 PIIX3State *piix3;
321 PCII440FXState *f;
322 unsigned i;
323 I440FXState *i440fx;
324 uint64_t pci_hole64_size;
325
326 dev = qdev_create(NULL, TYPE_I440FX_PCI_HOST_BRIDGE);
327 s = PCI_HOST_BRIDGE(dev);
328 b = pci_bus_new(dev, NULL, pci_address_space,
329 address_space_io, 0, TYPE_PCI_BUS);
330 s->bus = b;
331 object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL);
332 qdev_init_nofail(dev);
333
334 d = pci_create_simple(b, 0, TYPE_I440FX_PCI_DEVICE);
335 *pi440fx_state = I440FX_PCI_DEVICE(d);
336 f = *pi440fx_state;
337 f->system_memory = address_space_mem;
338 f->pci_address_space = pci_address_space;
339 f->ram_memory = ram_memory;
340
341 i440fx = I440FX_PCI_HOST_BRIDGE(dev);
342
343
344 if (ram_size <= 0x80000000) {
345 i440fx->pci_info.w32.begin = 0x80000000;
346 } else if (ram_size <= 0xc0000000) {
347 i440fx->pci_info.w32.begin = 0xc0000000;
348 } else {
349 i440fx->pci_info.w32.begin = 0xe0000000;
350 }
351
352 memory_region_init_alias(&f->pci_hole, OBJECT(d), "pci-hole", f->pci_address_space,
353 pci_hole_start, pci_hole_size);
354 memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole);
355
356 pci_hole64_size = pci_host_get_hole64_size(i440fx->pci_hole64_size);
357
358 pc_init_pci64_hole(&i440fx->pci_info, 0x100000000ULL + above_4g_mem_size,
359 pci_hole64_size);
360 memory_region_init_alias(&f->pci_hole_64bit, OBJECT(d), "pci-hole64",
361 f->pci_address_space,
362 i440fx->pci_info.w64.begin,
363 pci_hole64_size);
364 if (pci_hole64_size) {
365 memory_region_add_subregion(f->system_memory,
366 i440fx->pci_info.w64.begin,
367 &f->pci_hole_64bit);
368 }
369 memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region",
370 f->pci_address_space, 0xa0000, 0x20000);
371 memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
372 &f->smram_region, 1);
373 memory_region_set_enabled(&f->smram_region, false);
374 init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
375 &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
376 for (i = 0; i < 12; ++i) {
377 init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
378 &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
379 PAM_EXPAN_SIZE);
380 }
381
382
383
384
385
386 if (xen_enabled()) {
387 piix3 = DO_UPCAST(PIIX3State, dev,
388 pci_create_simple_multifunction(b, -1, true, "PIIX3-xen"));
389 pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
390 piix3, XEN_PIIX_NUM_PIRQS);
391 } else {
392 piix3 = DO_UPCAST(PIIX3State, dev,
393 pci_create_simple_multifunction(b, -1, true, "PIIX3"));
394 pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
395 PIIX_NUM_PIRQS);
396 pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq);
397 }
398 piix3->pic = pic;
399 *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
400
401 *piix3_devfn = piix3->dev.devfn;
402
403 ram_size = ram_size / 8 / 1024 / 1024;
404 if (ram_size > 255) {
405 ram_size = 255;
406 }
407 d->config[0x57] = ram_size;
408
409 i440fx_update_memory_mappings(f);
410
411 return b;
412}
413
414
415static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
416{
417 qemu_set_irq(piix3->pic[pic_irq],
418 !!(piix3->pic_levels &
419 (((1ULL << PIIX_NUM_PIRQS) - 1) <<
420 (pic_irq * PIIX_NUM_PIRQS))));
421}
422
423static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
424{
425 int pic_irq;
426 uint64_t mask;
427
428 pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
429 if (pic_irq >= PIIX_NUM_PIC_IRQS) {
430 return;
431 }
432
433 mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
434 piix3->pic_levels &= ~mask;
435 piix3->pic_levels |= mask * !!level;
436
437 piix3_set_irq_pic(piix3, pic_irq);
438}
439
440static void piix3_set_irq(void *opaque, int pirq, int level)
441{
442 PIIX3State *piix3 = opaque;
443 piix3_set_irq_level(piix3, pirq, level);
444}
445
446static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
447{
448 PIIX3State *piix3 = opaque;
449 int irq = piix3->dev.config[PIIX_PIRQC + pin];
450 PCIINTxRoute route;
451
452 if (irq < PIIX_NUM_PIC_IRQS) {
453 route.mode = PCI_INTX_ENABLED;
454 route.irq = irq;
455 } else {
456 route.mode = PCI_INTX_DISABLED;
457 route.irq = -1;
458 }
459 return route;
460}
461
462
463static void piix3_update_irq_levels(PIIX3State *piix3)
464{
465 int pirq;
466
467 piix3->pic_levels = 0;
468 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
469 piix3_set_irq_level(piix3, pirq,
470 pci_bus_get_irq_level(piix3->dev.bus, pirq));
471 }
472}
473
474static void piix3_write_config(PCIDevice *dev,
475 uint32_t address, uint32_t val, int len)
476{
477 pci_default_write_config(dev, address, val, len);
478 if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
479 PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev);
480 int pic_irq;
481
482 pci_bus_fire_intx_routing_notifier(piix3->dev.bus);
483 piix3_update_irq_levels(piix3);
484 for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
485 piix3_set_irq_pic(piix3, pic_irq);
486 }
487 }
488}
489
490static void piix3_write_config_xen(PCIDevice *dev,
491 uint32_t address, uint32_t val, int len)
492{
493 xen_piix_pci_write_config_client(address, val, len);
494 piix3_write_config(dev, address, val, len);
495}
496
497static void piix3_reset(void *opaque)
498{
499 PIIX3State *d = opaque;
500 uint8_t *pci_conf = d->dev.config;
501
502 pci_conf[0x04] = 0x07;
503 pci_conf[0x05] = 0x00;
504 pci_conf[0x06] = 0x00;
505 pci_conf[0x07] = 0x02;
506 pci_conf[0x4c] = 0x4d;
507 pci_conf[0x4e] = 0x03;
508 pci_conf[0x4f] = 0x00;
509 pci_conf[0x60] = 0x80;
510 pci_conf[0x61] = 0x80;
511 pci_conf[0x62] = 0x80;
512 pci_conf[0x63] = 0x80;
513 pci_conf[0x69] = 0x02;
514 pci_conf[0x70] = 0x80;
515 pci_conf[0x76] = 0x0c;
516 pci_conf[0x77] = 0x0c;
517 pci_conf[0x78] = 0x02;
518 pci_conf[0x79] = 0x00;
519 pci_conf[0x80] = 0x00;
520 pci_conf[0x82] = 0x00;
521 pci_conf[0xa0] = 0x08;
522 pci_conf[0xa2] = 0x00;
523 pci_conf[0xa3] = 0x00;
524 pci_conf[0xa4] = 0x00;
525 pci_conf[0xa5] = 0x00;
526 pci_conf[0xa6] = 0x00;
527 pci_conf[0xa7] = 0x00;
528 pci_conf[0xa8] = 0x0f;
529 pci_conf[0xaa] = 0x00;
530 pci_conf[0xab] = 0x00;
531 pci_conf[0xac] = 0x00;
532 pci_conf[0xae] = 0x00;
533
534 d->pic_levels = 0;
535 d->rcr = 0;
536}
537
538static int piix3_post_load(void *opaque, int version_id)
539{
540 PIIX3State *piix3 = opaque;
541 piix3_update_irq_levels(piix3);
542 return 0;
543}
544
545static void piix3_pre_save(void *opaque)
546{
547 int i;
548 PIIX3State *piix3 = opaque;
549
550 for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
551 piix3->pci_irq_levels_vmstate[i] =
552 pci_bus_get_irq_level(piix3->dev.bus, i);
553 }
554}
555
556static bool piix3_rcr_needed(void *opaque)
557{
558 PIIX3State *piix3 = opaque;
559
560 return (piix3->rcr != 0);
561}
562
563static const VMStateDescription vmstate_piix3_rcr = {
564 .name = "PIIX3/rcr",
565 .version_id = 1,
566 .minimum_version_id = 1,
567 .fields = (VMStateField []) {
568 VMSTATE_UINT8(rcr, PIIX3State),
569 VMSTATE_END_OF_LIST()
570 }
571};
572
573static const VMStateDescription vmstate_piix3 = {
574 .name = "PIIX3",
575 .version_id = 3,
576 .minimum_version_id = 2,
577 .minimum_version_id_old = 2,
578 .post_load = piix3_post_load,
579 .pre_save = piix3_pre_save,
580 .fields = (VMStateField[]) {
581 VMSTATE_PCI_DEVICE(dev, PIIX3State),
582 VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
583 PIIX_NUM_PIRQS, 3),
584 VMSTATE_END_OF_LIST()
585 },
586 .subsections = (VMStateSubsection[]) {
587 {
588 .vmsd = &vmstate_piix3_rcr,
589 .needed = piix3_rcr_needed,
590 },
591 { 0 }
592 }
593};
594
595
596static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
597{
598 PIIX3State *d = opaque;
599
600 if (val & 4) {
601 qemu_system_reset_request();
602 return;
603 }
604 d->rcr = val & 2;
605}
606
607static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
608{
609 PIIX3State *d = opaque;
610
611 return d->rcr;
612}
613
614static const MemoryRegionOps rcr_ops = {
615 .read = rcr_read,
616 .write = rcr_write,
617 .endianness = DEVICE_LITTLE_ENDIAN
618};
619
620static int piix3_initfn(PCIDevice *dev)
621{
622 PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
623
624 isa_bus_new(DEVICE(d), pci_address_space_io(dev));
625
626 memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
627 "piix3-reset-control", 1);
628 memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT,
629 &d->rcr_mem, 1);
630
631 qemu_register_reset(piix3_reset, d);
632 return 0;
633}
634
635static void piix3_class_init(ObjectClass *klass, void *data)
636{
637 DeviceClass *dc = DEVICE_CLASS(klass);
638 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
639
640 dc->desc = "ISA bridge";
641 dc->vmsd = &vmstate_piix3;
642 dc->no_user = 1,
643 k->no_hotplug = 1;
644 k->init = piix3_initfn;
645 k->config_write = piix3_write_config;
646 k->vendor_id = PCI_VENDOR_ID_INTEL;
647
648 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
649 k->class_id = PCI_CLASS_BRIDGE_ISA;
650}
651
652static const TypeInfo piix3_info = {
653 .name = "PIIX3",
654 .parent = TYPE_PCI_DEVICE,
655 .instance_size = sizeof(PIIX3State),
656 .class_init = piix3_class_init,
657};
658
659static void piix3_xen_class_init(ObjectClass *klass, void *data)
660{
661 DeviceClass *dc = DEVICE_CLASS(klass);
662 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
663
664 dc->desc = "ISA bridge";
665 dc->vmsd = &vmstate_piix3;
666 dc->no_user = 1;
667 k->no_hotplug = 1;
668 k->init = piix3_initfn;
669 k->config_write = piix3_write_config_xen;
670 k->vendor_id = PCI_VENDOR_ID_INTEL;
671
672 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
673 k->class_id = PCI_CLASS_BRIDGE_ISA;
674};
675
676static const TypeInfo piix3_xen_info = {
677 .name = "PIIX3-xen",
678 .parent = TYPE_PCI_DEVICE,
679 .instance_size = sizeof(PIIX3State),
680 .class_init = piix3_xen_class_init,
681};
682
683static void i440fx_class_init(ObjectClass *klass, void *data)
684{
685 DeviceClass *dc = DEVICE_CLASS(klass);
686 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
687
688 k->no_hotplug = 1;
689 k->init = i440fx_initfn;
690 k->config_write = i440fx_write_config;
691 k->vendor_id = PCI_VENDOR_ID_INTEL;
692 k->device_id = PCI_DEVICE_ID_INTEL_82441;
693 k->revision = 0x02;
694 k->class_id = PCI_CLASS_BRIDGE_HOST;
695 dc->desc = "Host bridge";
696 dc->no_user = 1;
697 dc->vmsd = &vmstate_i440fx;
698}
699
700static const TypeInfo i440fx_info = {
701 .name = TYPE_I440FX_PCI_DEVICE,
702 .parent = TYPE_PCI_DEVICE,
703 .instance_size = sizeof(PCII440FXState),
704 .class_init = i440fx_class_init,
705};
706
707static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge,
708 PCIBus *rootbus)
709{
710 I440FXState *s = I440FX_PCI_HOST_BRIDGE(host_bridge);
711
712
713 if (s->short_root_bus) {
714 return "0000";
715 }
716 return "0000:00";
717}
718
719static Property i440fx_props[] = {
720 DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, I440FXState,
721 pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE),
722 DEFINE_PROP_UINT32("short_root_bus", I440FXState, short_root_bus, 1),
723 DEFINE_PROP_END_OF_LIST(),
724};
725
726static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
727{
728 DeviceClass *dc = DEVICE_CLASS(klass);
729 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
730
731 hc->root_bus_path = i440fx_pcihost_root_bus_path;
732 dc->realize = i440fx_pcihost_realize;
733 dc->fw_name = "pci";
734 dc->no_user = 1;
735 dc->props = i440fx_props;
736}
737
738static const TypeInfo i440fx_pcihost_info = {
739 .name = TYPE_I440FX_PCI_HOST_BRIDGE,
740 .parent = TYPE_PCI_HOST_BRIDGE,
741 .instance_size = sizeof(I440FXState),
742 .instance_init = i440fx_pcihost_initfn,
743 .class_init = i440fx_pcihost_class_init,
744};
745
746static void i440fx_register_types(void)
747{
748 type_register_static(&i440fx_info);
749 type_register_static(&piix3_info);
750 type_register_static(&piix3_xen_info);
751 type_register_static(&i440fx_pcihost_info);
752}
753
754type_init(i440fx_register_types)
755
