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30#include "hw/hw.h"
31#include "hw/pci-host/q35.h"
32#include "qapi/visitor.h"
33
34
35
36
37
38static void q35_host_realize(DeviceState *dev, Error **errp)
39{
40 PCIHostState *pci = PCI_HOST_BRIDGE(dev);
41 Q35PCIHost *s = Q35_HOST_DEVICE(dev);
42 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
43
44 sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem);
45 sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4);
46
47 sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem);
48 sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4);
49
50 if (pcie_host_init(PCIE_HOST_BRIDGE(s)) < 0) {
51 error_setg(errp, "failed to initialize pcie host");
52 return;
53 }
54 pci->bus = pci_bus_new(DEVICE(s), "pcie.0",
55 s->mch.pci_address_space, s->mch.address_space_io,
56 0, TYPE_PCIE_BUS);
57 qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus));
58 qdev_init_nofail(DEVICE(&s->mch));
59}
60
61static const char *q35_host_root_bus_path(PCIHostState *host_bridge,
62 PCIBus *rootbus)
63{
64 Q35PCIHost *s = Q35_HOST_DEVICE(host_bridge);
65
66
67 if (s->mch.short_root_bus) {
68 return "0000";
69 }
70 return "0000:00";
71}
72
73static void q35_host_get_pci_hole_start(Object *obj, Visitor *v,
74 void *opaque, const char *name,
75 Error **errp)
76{
77 Q35PCIHost *s = Q35_HOST_DEVICE(obj);
78 uint32_t value = s->mch.pci_info.w32.begin;
79
80 visit_type_uint32(v, &value, name, errp);
81}
82
83static void q35_host_get_pci_hole_end(Object *obj, Visitor *v,
84 void *opaque, const char *name,
85 Error **errp)
86{
87 Q35PCIHost *s = Q35_HOST_DEVICE(obj);
88 uint32_t value = s->mch.pci_info.w32.end;
89
90 visit_type_uint32(v, &value, name, errp);
91}
92
93static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v,
94 void *opaque, const char *name,
95 Error **errp)
96{
97 Q35PCIHost *s = Q35_HOST_DEVICE(obj);
98
99 visit_type_uint64(v, &s->mch.pci_info.w64.begin, name, errp);
100}
101
102static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v,
103 void *opaque, const char *name,
104 Error **errp)
105{
106 Q35PCIHost *s = Q35_HOST_DEVICE(obj);
107
108 visit_type_uint64(v, &s->mch.pci_info.w64.end, name, errp);
109}
110
111static Property mch_props[] = {
112 DEFINE_PROP_UINT64("MCFG", Q35PCIHost, parent_obj.base_addr,
113 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
114 DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost,
115 mch.pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE),
116 DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 1),
117 DEFINE_PROP_END_OF_LIST(),
118};
119
120static void q35_host_class_init(ObjectClass *klass, void *data)
121{
122 DeviceClass *dc = DEVICE_CLASS(klass);
123 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
124
125 hc->root_bus_path = q35_host_root_bus_path;
126 dc->realize = q35_host_realize;
127 dc->props = mch_props;
128 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
129 dc->fw_name = "pci";
130}
131
132static void q35_host_initfn(Object *obj)
133{
134 Q35PCIHost *s = Q35_HOST_DEVICE(obj);
135 PCIHostState *phb = PCI_HOST_BRIDGE(obj);
136
137 memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb,
138 "pci-conf-idx", 4);
139 memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb,
140 "pci-conf-data", 4);
141
142 object_initialize(&s->mch, TYPE_MCH_PCI_DEVICE);
143 object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL);
144 qdev_prop_set_uint32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0));
145 qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false);
146
147 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "int",
148 q35_host_get_pci_hole_start,
149 NULL, NULL, NULL, NULL);
150
151 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "int",
152 q35_host_get_pci_hole_end,
153 NULL, NULL, NULL, NULL);
154
155 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "int",
156 q35_host_get_pci_hole64_start,
157 NULL, NULL, NULL, NULL);
158
159 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "int",
160 q35_host_get_pci_hole64_end,
161 NULL, NULL, NULL, NULL);
162
163
164
165
166
167
168 s->mch.pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT +
169 MCH_HOST_BRIDGE_PCIEXBAR_MAX;
170 s->mch.pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS;
171}
172
173static const TypeInfo q35_host_info = {
174 .name = TYPE_Q35_HOST_DEVICE,
175 .parent = TYPE_PCIE_HOST_BRIDGE,
176 .instance_size = sizeof(Q35PCIHost),
177 .instance_init = q35_host_initfn,
178 .class_init = q35_host_class_init,
179};
180
181
182
183
184
185
186static void mch_update_pciexbar(MCHPCIState *mch)
187{
188 PCIDevice *pci_dev = PCI_DEVICE(mch);
189 BusState *bus = qdev_get_parent_bus(DEVICE(mch));
190 PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent);
191
192 uint64_t pciexbar;
193 int enable;
194 uint64_t addr;
195 uint64_t addr_mask;
196 uint32_t length;
197
198 pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR);
199 enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN;
200 addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK;
201 switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) {
202 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M:
203 length = 256 * 1024 * 1024;
204 break;
205 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M:
206 length = 128 * 1024 * 1024;
207 addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK |
208 MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
209 break;
210 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M:
211 length = 64 * 1024 * 1024;
212 addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
213 break;
214 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD:
215 default:
216 enable = 0;
217 length = 0;
218 abort();
219 break;
220 }
221 addr = pciexbar & addr_mask;
222 pcie_host_mmcfg_update(pehb, enable, addr, length);
223}
224
225
226static void mch_update_pam(MCHPCIState *mch)
227{
228 PCIDevice *pd = PCI_DEVICE(mch);
229 int i;
230
231 memory_region_transaction_begin();
232 for (i = 0; i < 13; i++) {
233 pam_update(&mch->pam_regions[i], i,
234 pd->config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]);
235 }
236 memory_region_transaction_commit();
237}
238
239
240static void mch_update_smram(MCHPCIState *mch)
241{
242 PCIDevice *pd = PCI_DEVICE(mch);
243
244 memory_region_transaction_begin();
245 smram_update(&mch->smram_region, pd->config[MCH_HOST_BRDIGE_SMRAM],
246 mch->smm_enabled);
247 memory_region_transaction_commit();
248}
249
250static void mch_set_smm(int smm, void *arg)
251{
252 MCHPCIState *mch = arg;
253 PCIDevice *pd = PCI_DEVICE(mch);
254
255 memory_region_transaction_begin();
256 smram_set_smm(&mch->smm_enabled, smm, pd->config[MCH_HOST_BRDIGE_SMRAM],
257 &mch->smram_region);
258 memory_region_transaction_commit();
259}
260
261static void mch_write_config(PCIDevice *d,
262 uint32_t address, uint32_t val, int len)
263{
264 MCHPCIState *mch = MCH_PCI_DEVICE(d);
265
266
267 pci_default_write_config(d, address, val, len);
268
269 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0,
270 MCH_HOST_BRIDGE_PAM_SIZE)) {
271 mch_update_pam(mch);
272 }
273
274 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR,
275 MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) {
276 mch_update_pciexbar(mch);
277 }
278
279 if (ranges_overlap(address, len, MCH_HOST_BRDIGE_SMRAM,
280 MCH_HOST_BRDIGE_SMRAM_SIZE)) {
281 mch_update_smram(mch);
282 }
283}
284
285static void mch_update(MCHPCIState *mch)
286{
287 mch_update_pciexbar(mch);
288 mch_update_pam(mch);
289 mch_update_smram(mch);
290}
291
292static int mch_post_load(void *opaque, int version_id)
293{
294 MCHPCIState *mch = opaque;
295 mch_update(mch);
296 return 0;
297}
298
299static const VMStateDescription vmstate_mch = {
300 .name = "mch",
301 .version_id = 1,
302 .minimum_version_id = 1,
303 .minimum_version_id_old = 1,
304 .post_load = mch_post_load,
305 .fields = (VMStateField []) {
306 VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState),
307 VMSTATE_UINT8(smm_enabled, MCHPCIState),
308 VMSTATE_END_OF_LIST()
309 }
310};
311
312static void mch_reset(DeviceState *qdev)
313{
314 PCIDevice *d = PCI_DEVICE(qdev);
315 MCHPCIState *mch = MCH_PCI_DEVICE(d);
316
317 pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR,
318 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT);
319
320 d->config[MCH_HOST_BRDIGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT;
321
322 mch_update(mch);
323}
324
325static int mch_init(PCIDevice *d)
326{
327 int i;
328 MCHPCIState *mch = MCH_PCI_DEVICE(d);
329 uint64_t pci_hole64_size;
330
331
332 memory_region_init_alias(&mch->pci_hole, OBJECT(mch), "pci-hole",
333 mch->pci_address_space,
334 mch->below_4g_mem_size,
335 0x100000000ULL - mch->below_4g_mem_size);
336 memory_region_add_subregion(mch->system_memory, mch->below_4g_mem_size,
337 &mch->pci_hole);
338
339 pci_hole64_size = pci_host_get_hole64_size(mch->pci_hole64_size);
340 pc_init_pci64_hole(&mch->pci_info, 0x100000000ULL + mch->above_4g_mem_size,
341 pci_hole64_size);
342 memory_region_init_alias(&mch->pci_hole_64bit, OBJECT(mch), "pci-hole64",
343 mch->pci_address_space,
344 mch->pci_info.w64.begin,
345 pci_hole64_size);
346 if (pci_hole64_size) {
347 memory_region_add_subregion(mch->system_memory,
348 mch->pci_info.w64.begin,
349 &mch->pci_hole_64bit);
350 }
351
352 cpu_smm_register(&mch_set_smm, mch);
353 memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region",
354 mch->pci_address_space, 0xa0000, 0x20000);
355 memory_region_add_subregion_overlap(mch->system_memory, 0xa0000,
356 &mch->smram_region, 1);
357 memory_region_set_enabled(&mch->smram_region, false);
358 init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, mch->pci_address_space,
359 &mch->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
360 for (i = 0; i < 12; ++i) {
361 init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, mch->pci_address_space,
362 &mch->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
363 PAM_EXPAN_SIZE);
364 }
365 return 0;
366}
367
368static void mch_class_init(ObjectClass *klass, void *data)
369{
370 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
371 DeviceClass *dc = DEVICE_CLASS(klass);
372
373 k->init = mch_init;
374 k->config_write = mch_write_config;
375 dc->reset = mch_reset;
376 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
377 dc->desc = "Host bridge";
378 dc->vmsd = &vmstate_mch;
379 k->vendor_id = PCI_VENDOR_ID_INTEL;
380 k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH;
381 k->revision = MCH_HOST_BRIDGE_REVISION_DEFUALT;
382 k->class_id = PCI_CLASS_BRIDGE_HOST;
383}
384
385static const TypeInfo mch_info = {
386 .name = TYPE_MCH_PCI_DEVICE,
387 .parent = TYPE_PCI_DEVICE,
388 .instance_size = sizeof(MCHPCIState),
389 .class_init = mch_class_init,
390};
391
392static void q35_register(void)
393{
394 type_register_static(&mch_info);
395 type_register_static(&q35_host_info);
396}
397
398type_init(q35_register);
399
