1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22#include <inttypes.h>
23
24#include "qemu-common.h"
25#include "qemu/timer.h"
26#include "sysemu/watchdog.h"
27#include "hw/hw.h"
28#include "hw/pci/pci.h"
29
30
31
32#ifdef I6300ESB_DEBUG
33#define i6300esb_debug(fs,...) \
34 fprintf(stderr,"i6300esb: %s: "fs,__func__,##__VA_ARGS__)
35#else
36#define i6300esb_debug(fs,...)
37#endif
38
39
40#define ESB_CONFIG_REG 0x60
41#define ESB_LOCK_REG 0x68
42
43
44#define ESB_TIMER1_REG 0x00
45#define ESB_TIMER2_REG 0x04
46#define ESB_GINTSR_REG 0x08
47#define ESB_RELOAD_REG 0x0c
48
49
50#define ESB_WDT_FUNC (0x01 << 2)
51#define ESB_WDT_ENABLE (0x01 << 1)
52#define ESB_WDT_LOCK (0x01 << 0)
53
54
55#define ESB_WDT_REBOOT (0x01 << 5)
56#define ESB_WDT_FREQ (0x01 << 2)
57#define ESB_WDT_INTTYPE (0x11 << 0)
58
59
60#define ESB_WDT_RELOAD (0x01 << 8)
61
62
63#define ESB_UNLOCK1 0x80
64#define ESB_UNLOCK2 0x86
65
66
67struct I6300State {
68 PCIDevice dev;
69 MemoryRegion io_mem;
70
71 int reboot_enabled;
72
73
74
75 int clock_scale;
76#define CLOCK_SCALE_1KHZ 0
77#define CLOCK_SCALE_1MHZ 1
78
79 int int_type;
80#define INT_TYPE_IRQ 0
81#define INT_TYPE_SMI 2
82#define INT_TYPE_DISABLED 3
83
84 int free_run;
85 int locked;
86 int enabled;
87
88 QEMUTimer *timer;
89
90 uint32_t timer1_preload;
91 uint32_t timer2_preload;
92 int stage;
93
94 int unlock_state;
95
96
97
98
99 int previous_reboot_flag;
100
101
102};
103
104typedef struct I6300State I6300State;
105
106
107
108
109static void i6300esb_restart_timer(I6300State *d, int stage)
110{
111 int64_t timeout;
112
113 if (!d->enabled)
114 return;
115
116 d->stage = stage;
117
118 if (d->stage <= 1)
119 timeout = d->timer1_preload;
120 else
121 timeout = d->timer2_preload;
122
123 if (d->clock_scale == CLOCK_SCALE_1KHZ)
124 timeout <<= 15;
125 else
126 timeout <<= 5;
127
128
129 timeout = get_ticks_per_sec() * timeout / 33000000;
130
131 i6300esb_debug("stage %d, timeout %" PRIi64 "\n", d->stage, timeout);
132
133 qemu_mod_timer(d->timer, qemu_get_clock_ns(vm_clock) + timeout);
134}
135
136
137static void i6300esb_disable_timer(I6300State *d)
138{
139 i6300esb_debug("timer disabled\n");
140
141 qemu_del_timer(d->timer);
142}
143
144static void i6300esb_reset(DeviceState *dev)
145{
146 PCIDevice *pdev = PCI_DEVICE(dev);
147 I6300State *d = DO_UPCAST(I6300State, dev, pdev);
148
149 i6300esb_debug("I6300State = %p\n", d);
150
151 i6300esb_disable_timer(d);
152
153
154
155 d->reboot_enabled = 1;
156 d->clock_scale = CLOCK_SCALE_1KHZ;
157 d->int_type = INT_TYPE_IRQ;
158 d->free_run = 0;
159 d->locked = 0;
160 d->enabled = 0;
161 d->timer1_preload = 0xfffff;
162 d->timer2_preload = 0xfffff;
163 d->stage = 1;
164 d->unlock_state = 0;
165}
166
167
168
169
170
171
172
173
174static void i6300esb_timer_expired(void *vp)
175{
176 I6300State *d = vp;
177
178 i6300esb_debug("stage %d\n", d->stage);
179
180 if (d->stage == 1) {
181
182 switch (d->int_type) {
183 case INT_TYPE_IRQ:
184 fprintf(stderr, "i6300esb_timer_expired: I would send APIC 1 INT 10 here if I knew how (XXX)\n");
185 break;
186 case INT_TYPE_SMI:
187 fprintf(stderr, "i6300esb_timer_expired: I would send SMI here if I knew how (XXX)\n");
188 break;
189 }
190
191
192 i6300esb_restart_timer(d, 2);
193 } else {
194
195 if (d->reboot_enabled) {
196 d->previous_reboot_flag = 1;
197 watchdog_perform_action();
198 i6300esb_reset(&d->dev.qdev);
199 }
200
201
202 if (d->free_run)
203 i6300esb_restart_timer(d, 1);
204 }
205}
206
207static void i6300esb_config_write(PCIDevice *dev, uint32_t addr,
208 uint32_t data, int len)
209{
210 I6300State *d = DO_UPCAST(I6300State, dev, dev);
211 int old;
212
213 i6300esb_debug("addr = %x, data = %x, len = %d\n", addr, data, len);
214
215 if (addr == ESB_CONFIG_REG && len == 2) {
216 d->reboot_enabled = (data & ESB_WDT_REBOOT) == 0;
217 d->clock_scale =
218 (data & ESB_WDT_FREQ) != 0 ? CLOCK_SCALE_1MHZ : CLOCK_SCALE_1KHZ;
219 d->int_type = (data & ESB_WDT_INTTYPE);
220 } else if (addr == ESB_LOCK_REG && len == 1) {
221 if (!d->locked) {
222 d->locked = (data & ESB_WDT_LOCK) != 0;
223 d->free_run = (data & ESB_WDT_FUNC) != 0;
224 old = d->enabled;
225 d->enabled = (data & ESB_WDT_ENABLE) != 0;
226 if (!old && d->enabled)
227 i6300esb_restart_timer(d, 1);
228 else if (!d->enabled)
229 i6300esb_disable_timer(d);
230 }
231 } else {
232 pci_default_write_config(dev, addr, data, len);
233 }
234}
235
236static uint32_t i6300esb_config_read(PCIDevice *dev, uint32_t addr, int len)
237{
238 I6300State *d = DO_UPCAST(I6300State, dev, dev);
239 uint32_t data;
240
241 i6300esb_debug ("addr = %x, len = %d\n", addr, len);
242
243 if (addr == ESB_CONFIG_REG && len == 2) {
244 data =
245 (d->reboot_enabled ? 0 : ESB_WDT_REBOOT) |
246 (d->clock_scale == CLOCK_SCALE_1MHZ ? ESB_WDT_FREQ : 0) |
247 d->int_type;
248 return data;
249 } else if (addr == ESB_LOCK_REG && len == 1) {
250 data =
251 (d->free_run ? ESB_WDT_FUNC : 0) |
252 (d->locked ? ESB_WDT_LOCK : 0) |
253 (d->enabled ? ESB_WDT_ENABLE : 0);
254 return data;
255 } else {
256 return pci_default_read_config(dev, addr, len);
257 }
258}
259
260static uint32_t i6300esb_mem_readb(void *vp, hwaddr addr)
261{
262 i6300esb_debug ("addr = %x\n", (int) addr);
263
264 return 0;
265}
266
267static uint32_t i6300esb_mem_readw(void *vp, hwaddr addr)
268{
269 uint32_t data = 0;
270 I6300State *d = vp;
271
272 i6300esb_debug("addr = %x\n", (int) addr);
273
274 if (addr == 0xc) {
275
276
277
278
279 data = d->previous_reboot_flag ? 0x1200 : 0;
280 }
281
282 return data;
283}
284
285static uint32_t i6300esb_mem_readl(void *vp, hwaddr addr)
286{
287 i6300esb_debug("addr = %x\n", (int) addr);
288
289 return 0;
290}
291
292static void i6300esb_mem_writeb(void *vp, hwaddr addr, uint32_t val)
293{
294 I6300State *d = vp;
295
296 i6300esb_debug("addr = %x, val = %x\n", (int) addr, val);
297
298 if (addr == 0xc && val == 0x80)
299 d->unlock_state = 1;
300 else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
301 d->unlock_state = 2;
302}
303
304static void i6300esb_mem_writew(void *vp, hwaddr addr, uint32_t val)
305{
306 I6300State *d = vp;
307
308 i6300esb_debug("addr = %x, val = %x\n", (int) addr, val);
309
310 if (addr == 0xc && val == 0x80)
311 d->unlock_state = 1;
312 else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
313 d->unlock_state = 2;
314 else {
315 if (d->unlock_state == 2) {
316 if (addr == 0xc) {
317 if ((val & 0x100) != 0)
318
319
320
321 i6300esb_restart_timer(d, 1);
322
323
324
325
326
327 if ((val & 0x200) != 0 || (val & 0x1000) != 0) {
328 d->previous_reboot_flag = 0;
329 }
330 }
331
332 d->unlock_state = 0;
333 }
334 }
335}
336
337static void i6300esb_mem_writel(void *vp, hwaddr addr, uint32_t val)
338{
339 I6300State *d = vp;
340
341 i6300esb_debug ("addr = %x, val = %x\n", (int) addr, val);
342
343 if (addr == 0xc && val == 0x80)
344 d->unlock_state = 1;
345 else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
346 d->unlock_state = 2;
347 else {
348 if (d->unlock_state == 2) {
349 if (addr == 0)
350 d->timer1_preload = val & 0xfffff;
351 else if (addr == 4)
352 d->timer2_preload = val & 0xfffff;
353
354 d->unlock_state = 0;
355 }
356 }
357}
358
359static const MemoryRegionOps i6300esb_ops = {
360 .old_mmio = {
361 .read = {
362 i6300esb_mem_readb,
363 i6300esb_mem_readw,
364 i6300esb_mem_readl,
365 },
366 .write = {
367 i6300esb_mem_writeb,
368 i6300esb_mem_writew,
369 i6300esb_mem_writel,
370 },
371 },
372 .endianness = DEVICE_NATIVE_ENDIAN,
373};
374
375static const VMStateDescription vmstate_i6300esb = {
376 .name = "i6300esb_wdt",
377
378
379
380
381
382
383
384
385
386
387
388
389
390 .version_id = 10000,
391 .minimum_version_id = 1,
392 .minimum_version_id_old = 1,
393 .fields = (VMStateField []) {
394 VMSTATE_PCI_DEVICE(dev, I6300State),
395 VMSTATE_INT32(reboot_enabled, I6300State),
396 VMSTATE_INT32(clock_scale, I6300State),
397 VMSTATE_INT32(int_type, I6300State),
398 VMSTATE_INT32(free_run, I6300State),
399 VMSTATE_INT32(locked, I6300State),
400 VMSTATE_INT32(enabled, I6300State),
401 VMSTATE_TIMER(timer, I6300State),
402 VMSTATE_UINT32(timer1_preload, I6300State),
403 VMSTATE_UINT32(timer2_preload, I6300State),
404 VMSTATE_INT32(stage, I6300State),
405 VMSTATE_INT32(unlock_state, I6300State),
406 VMSTATE_INT32(previous_reboot_flag, I6300State),
407 VMSTATE_END_OF_LIST()
408 }
409};
410
411static int i6300esb_init(PCIDevice *dev)
412{
413 I6300State *d = DO_UPCAST(I6300State, dev, dev);
414
415 i6300esb_debug("I6300State = %p\n", d);
416
417 d->timer = qemu_new_timer_ns(vm_clock, i6300esb_timer_expired, d);
418 d->previous_reboot_flag = 0;
419
420 memory_region_init_io(&d->io_mem, OBJECT(d), &i6300esb_ops, d,
421 "i6300esb", 0x10);
422 pci_register_bar(&d->dev, 0, 0, &d->io_mem);
423
424
425 return 0;
426}
427
428static void i6300esb_exit(PCIDevice *dev)
429{
430 I6300State *d = DO_UPCAST(I6300State, dev, dev);
431
432 memory_region_destroy(&d->io_mem);
433}
434
435static WatchdogTimerModel model = {
436 .wdt_name = "i6300esb",
437 .wdt_description = "Intel 6300ESB",
438};
439
440static void i6300esb_class_init(ObjectClass *klass, void *data)
441{
442 DeviceClass *dc = DEVICE_CLASS(klass);
443 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
444
445 k->config_read = i6300esb_config_read;
446 k->config_write = i6300esb_config_write;
447 k->init = i6300esb_init;
448 k->exit = i6300esb_exit;
449 k->vendor_id = PCI_VENDOR_ID_INTEL;
450 k->device_id = PCI_DEVICE_ID_INTEL_ESB_9;
451 k->class_id = PCI_CLASS_SYSTEM_OTHER;
452 dc->reset = i6300esb_reset;
453 dc->vmsd = &vmstate_i6300esb;
454 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
455}
456
457static const TypeInfo i6300esb_info = {
458 .name = "i6300esb",
459 .parent = TYPE_PCI_DEVICE,
460 .instance_size = sizeof(I6300State),
461 .class_init = i6300esb_class_init,
462};
463
464static void i6300esb_register_types(void)
465{
466 watchdog_add_model(&model);
467 type_register_static(&i6300esb_info);
468}
469
470type_init(i6300esb_register_types)
471