LXR qemu/target-mips/helper.c

   1/*
   2 *  MIPS emulation helpers for qemu.
   3 *
   4 *  Copyright (c) 2004-2005 Jocelyn Mayer
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19#include <stdarg.h>
  20#include <stdlib.h>
  21#include <stdio.h>
  22#include <string.h>
  23#include <inttypes.h>
  24#include <signal.h>
  25
  26#include "cpu.h"
  27
  28enum {
  29    TLBRET_DIRTY = -4,
  30    TLBRET_INVALID = -3,
  31    TLBRET_NOMATCH = -2,
  32    TLBRET_BADADDR = -1,
  33    TLBRET_MATCH = 0
  34};
  35
  36#if !defined(CONFIG_USER_ONLY)
  37
  38/* no MMU emulation */
  39int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
  40                        target_ulong address, int rw, int access_type)
  41{
  42    *physical = address;
  43    *prot = PAGE_READ | PAGE_WRITE;
  44    return TLBRET_MATCH;
  45}
  46
  47/* fixed mapping MMU emulation */
  48int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
  49                           target_ulong address, int rw, int access_type)
  50{
  51    if (address <= (int32_t)0x7FFFFFFFUL) {
  52        if (!(env->CP0_Status & (1 << CP0St_ERL)))
  53            *physical = address + 0x40000000UL;
  54        else
  55            *physical = address;
  56    } else if (address <= (int32_t)0xBFFFFFFFUL)
  57        *physical = address & 0x1FFFFFFF;
  58    else
  59        *physical = address;
  60
  61    *prot = PAGE_READ | PAGE_WRITE;
  62    return TLBRET_MATCH;
  63}
  64
  65/* MIPS32/MIPS64 R4000-style MMU emulation */
  66int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
  67                     target_ulong address, int rw, int access_type)
  68{
  69    uint8_t ASID = env->CP0_EntryHi & 0xFF;
  70    int i;
  71
  72    for (i = 0; i < env->tlb->tlb_in_use; i++) {
  73        r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
  74        /* 1k pages are not supported. */
  75        target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
  76        target_ulong tag = address & ~mask;
  77        target_ulong VPN = tlb->VPN & ~mask;
  78#if defined(TARGET_MIPS64)
  79        tag &= env->SEGMask;
  80#endif
  81
  82        /* Check ASID, virtual page number & size */
  83        if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
  84            /* TLB match */
  85            int n = !!(address & mask & ~(mask >> 1));
  86            /* Check access rights */
  87            if (!(n ? tlb->V1 : tlb->V0))
  88                return TLBRET_INVALID;
  89            if (rw == 0 || (n ? tlb->D1 : tlb->D0)) {
  90                *physical = tlb->PFN[n] | (address & (mask >> 1));
  91                *prot = PAGE_READ;
  92                if (n ? tlb->D1 : tlb->D0)
  93                    *prot |= PAGE_WRITE;
  94                return TLBRET_MATCH;
  95            }
  96            return TLBRET_DIRTY;
  97        }
  98    }
  99    return TLBRET_NOMATCH;
 100}
 101
 102static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
 103                                int *prot, target_ulong address,
 104                                int rw, int access_type)
 105{
 106    /* User mode can only access useg/xuseg */
 107    int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
 108    int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM;
 109    int kernel_mode = !user_mode && !supervisor_mode;
 110#if defined(TARGET_MIPS64)
 111    int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 112    int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 113    int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 114#endif
 115    int ret = TLBRET_MATCH;
 116
 117#if 0
 118    qemu_log("user mode %d h %08x\n", user_mode, env->hflags);
 119#endif
 120
 121    if (address <= (int32_t)0x7FFFFFFFUL) {
 122        /* useg */
 123        if (env->CP0_Status & (1 << CP0St_ERL)) {
 124            *physical = address & 0xFFFFFFFF;
 125            *prot = PAGE_READ | PAGE_WRITE;
 126        } else {
 127            ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
 128        }
 129#if defined(TARGET_MIPS64)
 130    } else if (address < 0x4000000000000000ULL) {
 131        /* xuseg */
 132        if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
 133            ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
 134        } else {
 135            ret = TLBRET_BADADDR;
 136        }
 137    } else if (address < 0x8000000000000000ULL) {
 138        /* xsseg */
 139        if ((supervisor_mode || kernel_mode) &&
 140            SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
 141            ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
 142        } else {
 143            ret = TLBRET_BADADDR;
 144        }
 145    } else if (address < 0xC000000000000000ULL) {
 146        /* xkphys */
 147        if (kernel_mode && KX &&
 148            (address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
 149            *physical = address & env->PAMask;
 150            *prot = PAGE_READ | PAGE_WRITE;
 151        } else {
 152            ret = TLBRET_BADADDR;
 153        }
 154    } else if (address < 0xFFFFFFFF80000000ULL) {
 155        /* xkseg */
 156        if (kernel_mode && KX &&
 157            address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
 158            ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
 159        } else {
 160            ret = TLBRET_BADADDR;
 161        }
 162#endif
 163    } else if (address < (int32_t)0xA0000000UL) {
 164        /* kseg0 */
 165        if (kernel_mode) {
 166            *physical = address - (int32_t)0x80000000UL;
 167            *prot = PAGE_READ | PAGE_WRITE;
 168        } else {
 169            ret = TLBRET_BADADDR;
 170        }
 171    } else if (address < (int32_t)0xC0000000UL) {
 172        /* kseg1 */
 173        if (kernel_mode) {
 174            *physical = address - (int32_t)0xA0000000UL;
 175            *prot = PAGE_READ | PAGE_WRITE;
 176        } else {
 177            ret = TLBRET_BADADDR;
 178        }
 179    } else if (address < (int32_t)0xE0000000UL) {
 180        /* sseg (kseg2) */
 181        if (supervisor_mode || kernel_mode) {
 182            ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
 183        } else {
 184            ret = TLBRET_BADADDR;
 185        }
 186    } else {
 187        /* kseg3 */
 188        /* XXX: debug segment is not emulated */
 189        if (kernel_mode) {
 190            ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
 191        } else {
 192            ret = TLBRET_BADADDR;
 193        }
 194    }
 195#if 0
 196    qemu_log(TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n",
 197            address, rw, access_type, *physical, *prot, ret);
 198#endif
 199
 200    return ret;
 201}
 202#endif
 203
 204static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
 205                                int rw, int tlb_error)
 206{
 207    int exception = 0, error_code = 0;
 208
 209    switch (tlb_error) {
 210    default:
 211    case TLBRET_BADADDR:
 212        /* Reference to kernel address from user mode or supervisor mode */
 213        /* Reference to supervisor address from user mode */
 214        if (rw)
 215            exception = EXCP_AdES;
 216        else
 217            exception = EXCP_AdEL;
 218        break;
 219    case TLBRET_NOMATCH:
 220        /* No TLB match for a mapped address */
 221        if (rw)
 222            exception = EXCP_TLBS;
 223        else
 224            exception = EXCP_TLBL;
 225        error_code = 1;
 226        break;
 227    case TLBRET_INVALID:
 228        /* TLB match with no valid bit */
 229        if (rw)
 230            exception = EXCP_TLBS;
 231        else
 232            exception = EXCP_TLBL;
 233        break;
 234    case TLBRET_DIRTY:
 235        /* TLB match but 'D' bit is cleared */
 236        exception = EXCP_LTLBL;
 237        break;
 238
 239    }
 240    /* Raise exception */
 241    env->CP0_BadVAddr = address;
 242    env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
 243                       ((address >> 9) & 0x007ffff0);
 244    env->CP0_EntryHi =
 245        (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
 246#if defined(TARGET_MIPS64)
 247    env->CP0_EntryHi &= env->SEGMask;
 248    env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
 249                        ((address & 0xC00000000000ULL) >> (55 - env->SEGBITS)) |
 250                        ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9);
 251#endif
 252    env->exception_index = exception;
 253    env->error_code = error_code;
 254}
 255
 256#if !defined(CONFIG_USER_ONLY)
 257hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 258{
 259    MIPSCPU *cpu = MIPS_CPU(cs);
 260    hwaddr phys_addr;
 261    int prot;
 262
 263    if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0,
 264                             ACCESS_INT) != 0) {
 265        return -1;
 266    }
 267    return phys_addr;
 268}
 269#endif
 270
 271int cpu_mips_handle_mmu_fault (CPUMIPSState *env, target_ulong address, int rw,
 272                               int mmu_idx)
 273{
 274#if !defined(CONFIG_USER_ONLY)
 275    hwaddr physical;
 276    int prot;
 277    int access_type;
 278#endif
 279    int ret = 0;
 280
 281#if 0
 282    log_cpu_state(CPU(mips_env_get_cpu(env)), 0);
 283#endif
 284    qemu_log("%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d mmu_idx %d\n",
 285              __func__, env->active_tc.PC, address, rw, mmu_idx);
 286
 287    rw &= 1;
 288
 289    /* data access */
 290#if !defined(CONFIG_USER_ONLY)
 291    /* XXX: put correct access by using cpu_restore_state()
 292       correctly */
 293    access_type = ACCESS_INT;
 294    ret = get_physical_address(env, &physical, &prot,
 295                               address, rw, access_type);
 296    qemu_log("%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_plx " prot %d\n",
 297              __func__, address, ret, physical, prot);
 298    if (ret == TLBRET_MATCH) {
 299        tlb_set_page(env, address & TARGET_PAGE_MASK,
 300                     physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
 301                     mmu_idx, TARGET_PAGE_SIZE);
 302        ret = 0;
 303    } else if (ret < 0)
 304#endif
 305    {
 306        raise_mmu_exception(env, address, rw, ret);
 307        ret = 1;
 308    }
 309
 310    return ret;
 311}
 312
 313#if !defined(CONFIG_USER_ONLY)
 314hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw)
 315{
 316    hwaddr physical;
 317    int prot;
 318    int access_type;
 319    int ret = 0;
 320
 321    rw &= 1;
 322
 323    /* data access */
 324    access_type = ACCESS_INT;
 325    ret = get_physical_address(env, &physical, &prot,
 326                               address, rw, access_type);
 327    if (ret != TLBRET_MATCH) {
 328        raise_mmu_exception(env, address, rw, ret);
 329        return -1LL;
 330    } else {
 331        return physical;
 332    }
 333}
 334#endif
 335
 336static const char * const excp_names[EXCP_LAST + 1] = {
 337    [EXCP_RESET] = "reset",
 338    [EXCP_SRESET] = "soft reset",
 339    [EXCP_DSS] = "debug single step",
 340    [EXCP_DINT] = "debug interrupt",
 341    [EXCP_NMI] = "non-maskable interrupt",
 342    [EXCP_MCHECK] = "machine check",
 343    [EXCP_EXT_INTERRUPT] = "interrupt",
 344    [EXCP_DFWATCH] = "deferred watchpoint",
 345    [EXCP_DIB] = "debug instruction breakpoint",
 346    [EXCP_IWATCH] = "instruction fetch watchpoint",
 347    [EXCP_AdEL] = "address error load",
 348    [EXCP_AdES] = "address error store",
 349    [EXCP_TLBF] = "TLB refill",
 350    [EXCP_IBE] = "instruction bus error",
 351    [EXCP_DBp] = "debug breakpoint",
 352    [EXCP_SYSCALL] = "syscall",
 353    [EXCP_BREAK] = "break",
 354    [EXCP_CpU] = "coprocessor unusable",
 355    [EXCP_RI] = "reserved instruction",
 356    [EXCP_OVERFLOW] = "arithmetic overflow",
 357    [EXCP_TRAP] = "trap",
 358    [EXCP_FPE] = "floating point",
 359    [EXCP_DDBS] = "debug data break store",
 360    [EXCP_DWATCH] = "data watchpoint",
 361    [EXCP_LTLBL] = "TLB modify",
 362    [EXCP_TLBL] = "TLB load",
 363    [EXCP_TLBS] = "TLB store",
 364    [EXCP_DBE] = "data bus error",
 365    [EXCP_DDBL] = "debug data break load",
 366    [EXCP_THREAD] = "thread",
 367    [EXCP_MDMX] = "MDMX",
 368    [EXCP_C2E] = "precise coprocessor 2",
 369    [EXCP_CACHE] = "cache error",
 370};
 371
 372target_ulong exception_resume_pc (CPUMIPSState *env)
 373{
 374    target_ulong bad_pc;
 375    target_ulong isa_mode;
 376
 377    isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
 378    bad_pc = env->active_tc.PC | isa_mode;
 379    if (env->hflags & MIPS_HFLAG_BMASK) {
 380        /* If the exception was raised from a delay slot, come back to
 381           the jump.  */
 382        bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
 383    }
 384
 385    return bad_pc;
 386}
 387
 388#if !defined(CONFIG_USER_ONLY)
 389static void set_hflags_for_handler (CPUMIPSState *env)
 390{
 391    /* Exception handlers are entered in 32-bit mode.  */
 392    env->hflags &= ~(MIPS_HFLAG_M16);
 393    /* ...except that microMIPS lets you choose.  */
 394    if (env->insn_flags & ASE_MICROMIPS) {
 395        env->hflags |= (!!(env->CP0_Config3
 396                           & (1 << CP0C3_ISA_ON_EXC))
 397                        << MIPS_HFLAG_M16_SHIFT);
 398    }
 399}
 400#endif
 401
 402void mips_cpu_do_interrupt(CPUState *cs)
 403{
 404    MIPSCPU *cpu = MIPS_CPU(cs);
 405    CPUMIPSState *env = &cpu->env;
 406#if !defined(CONFIG_USER_ONLY)
 407    target_ulong offset;
 408    int cause = -1;
 409    const char *name;
 410
 411    if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) {
 412        if (env->exception_index < 0 || env->exception_index > EXCP_LAST)
 413            name = "unknown";
 414        else
 415            name = excp_names[env->exception_index];
 416
 417        qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n",
 418                 __func__, env->active_tc.PC, env->CP0_EPC, name);
 419    }
 420    if (env->exception_index == EXCP_EXT_INTERRUPT &&
 421        (env->hflags & MIPS_HFLAG_DM))
 422        env->exception_index = EXCP_DINT;
 423    offset = 0x180;
 424    switch (env->exception_index) {
 425    case EXCP_DSS:
 426        env->CP0_Debug |= 1 << CP0DB_DSS;
 427        /* Debug single step cannot be raised inside a delay slot and
 428           resume will always occur on the next instruction
 429           (but we assume the pc has always been updated during
 430           code translation). */
 431        env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16);
 432        goto enter_debug_mode;
 433    case EXCP_DINT:
 434        env->CP0_Debug |= 1 << CP0DB_DINT;
 435        goto set_DEPC;
 436    case EXCP_DIB:
 437        env->CP0_Debug |= 1 << CP0DB_DIB;
 438        goto set_DEPC;
 439    case EXCP_DBp:
 440        env->CP0_Debug |= 1 << CP0DB_DBp;
 441        goto set_DEPC;
 442    case EXCP_DDBS:
 443        env->CP0_Debug |= 1 << CP0DB_DDBS;
 444        goto set_DEPC;
 445    case EXCP_DDBL:
 446        env->CP0_Debug |= 1 << CP0DB_DDBL;
 447    set_DEPC:
 448        env->CP0_DEPC = exception_resume_pc(env);
 449        env->hflags &= ~MIPS_HFLAG_BMASK;
 450 enter_debug_mode:
 451        env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
 452        env->hflags &= ~(MIPS_HFLAG_KSU);
 453        /* EJTAG probe trap enable is not implemented... */
 454        if (!(env->CP0_Status & (1 << CP0St_EXL)))
 455            env->CP0_Cause &= ~(1 << CP0Ca_BD);
 456        env->active_tc.PC = (int32_t)0xBFC00480;
 457        set_hflags_for_handler(env);
 458        break;
 459    case EXCP_RESET:
 460        cpu_reset(CPU(cpu));
 461        break;
 462    case EXCP_SRESET:
 463        env->CP0_Status |= (1 << CP0St_SR);
 464        memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo));
 465        goto set_error_EPC;
 466    case EXCP_NMI:
 467        env->CP0_Status |= (1 << CP0St_NMI);
 468 set_error_EPC:
 469        env->CP0_ErrorEPC = exception_resume_pc(env);
 470        env->hflags &= ~MIPS_HFLAG_BMASK;
 471        env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
 472        env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
 473        env->hflags &= ~(MIPS_HFLAG_KSU);
 474        if (!(env->CP0_Status & (1 << CP0St_EXL)))
 475            env->CP0_Cause &= ~(1 << CP0Ca_BD);
 476        env->active_tc.PC = (int32_t)0xBFC00000;
 477        set_hflags_for_handler(env);
 478        break;
 479    case EXCP_EXT_INTERRUPT:
 480        cause = 0;
 481        if (env->CP0_Cause & (1 << CP0Ca_IV))
 482            offset = 0x200;
 483
 484        if (env->CP0_Config3 & ((1 << CP0C3_VInt) | (1 << CP0C3_VEIC))) {
 485            /* Vectored Interrupts.  */
 486            unsigned int spacing;
 487            unsigned int vector;
 488            unsigned int pending = (env->CP0_Cause & CP0Ca_IP_mask) >> 8;
 489
 490            pending &= env->CP0_Status >> 8;
 491            /* Compute the Vector Spacing.  */
 492            spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & ((1 << 6) - 1);
 493            spacing <<= 5;
 494
 495            if (env->CP0_Config3 & (1 << CP0C3_VInt)) {
 496                /* For VInt mode, the MIPS computes the vector internally.  */
 497                for (vector = 7; vector > 0; vector--) {
 498                    if (pending & (1 << vector)) {
 499                        /* Found it.  */
 500                        break;
 501                    }
 502                }
 503            } else {
 504                /* For VEIC mode, the external interrupt controller feeds the
 505                   vector through the CP0Cause IP lines.  */
 506                vector = pending;
 507            }
 508            offset = 0x200 + vector * spacing;
 509        }
 510        goto set_EPC;
 511    case EXCP_LTLBL:
 512        cause = 1;
 513        goto set_EPC;
 514    case EXCP_TLBL:
 515        cause = 2;
 516        if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
 517#if defined(TARGET_MIPS64)
 518            int R = env->CP0_BadVAddr >> 62;
 519            int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 520            int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 521            int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 522
 523            if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
 524                (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
 525                offset = 0x080;
 526            else
 527#endif
 528                offset = 0x000;
 529        }
 530        goto set_EPC;
 531    case EXCP_TLBS:
 532        cause = 3;
 533        if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
 534#if defined(TARGET_MIPS64)
 535            int R = env->CP0_BadVAddr >> 62;
 536            int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 537            int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 538            int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 539
 540            if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
 541                (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
 542                offset = 0x080;
 543            else
 544#endif
 545                offset = 0x000;
 546        }
 547        goto set_EPC;
 548    case EXCP_AdEL:
 549        cause = 4;
 550        goto set_EPC;
 551    case EXCP_AdES:
 552        cause = 5;
 553        goto set_EPC;
 554    case EXCP_IBE:
 555        cause = 6;
 556        goto set_EPC;
 557    case EXCP_DBE:
 558        cause = 7;
 559        goto set_EPC;
 560    case EXCP_SYSCALL:
 561        cause = 8;
 562        goto set_EPC;
 563    case EXCP_BREAK:
 564        cause = 9;
 565        goto set_EPC;
 566    case EXCP_RI:
 567        cause = 10;
 568        goto set_EPC;
 569    case EXCP_CpU:
 570        cause = 11;
 571        env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
 572                         (env->error_code << CP0Ca_CE);
 573        goto set_EPC;
 574    case EXCP_OVERFLOW:
 575        cause = 12;
 576        goto set_EPC;
 577    case EXCP_TRAP:
 578        cause = 13;
 579        goto set_EPC;
 580    case EXCP_FPE:
 581        cause = 15;
 582        goto set_EPC;
 583    case EXCP_C2E:
 584        cause = 18;
 585        goto set_EPC;
 586    case EXCP_MDMX:
 587        cause = 22;
 588        goto set_EPC;
 589    case EXCP_DWATCH:
 590        cause = 23;
 591        /* XXX: TODO: manage defered watch exceptions */
 592        goto set_EPC;
 593    case EXCP_MCHECK:
 594        cause = 24;
 595        goto set_EPC;
 596    case EXCP_THREAD:
 597        cause = 25;
 598        goto set_EPC;
 599    case EXCP_DSPDIS:
 600        cause = 26;
 601        goto set_EPC;
 602    case EXCP_CACHE:
 603        cause = 30;
 604        if (env->CP0_Status & (1 << CP0St_BEV)) {
 605            offset = 0x100;
 606        } else {
 607            offset = 0x20000100;
 608        }
 609 set_EPC:
 610        if (!(env->CP0_Status & (1 << CP0St_EXL))) {
 611            env->CP0_EPC = exception_resume_pc(env);
 612            if (env->hflags & MIPS_HFLAG_BMASK) {
 613                env->CP0_Cause |= (1 << CP0Ca_BD);
 614            } else {
 615                env->CP0_Cause &= ~(1 << CP0Ca_BD);
 616            }
 617            env->CP0_Status |= (1 << CP0St_EXL);
 618            env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
 619            env->hflags &= ~(MIPS_HFLAG_KSU);
 620        }
 621        env->hflags &= ~MIPS_HFLAG_BMASK;
 622        if (env->CP0_Status & (1 << CP0St_BEV)) {
 623            env->active_tc.PC = (int32_t)0xBFC00200;
 624        } else {
 625            env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
 626        }
 627        env->active_tc.PC += offset;
 628        set_hflags_for_handler(env);
 629        env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
 630        break;
 631    default:
 632        qemu_log("Invalid MIPS exception %d. Exiting\n", env->exception_index);
 633        printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
 634        exit(1);
 635    }
 636    if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) {
 637        qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
 638                "    S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
 639                __func__, env->active_tc.PC, env->CP0_EPC, cause,
 640                env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
 641                env->CP0_DEPC);
 642    }
 643#endif
 644    env->exception_index = EXCP_NONE;
 645}
 646
 647#if !defined(CONFIG_USER_ONLY)
 648void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
 649{
 650    r4k_tlb_t *tlb;
 651    target_ulong addr;
 652    target_ulong end;
 653    uint8_t ASID = env->CP0_EntryHi & 0xFF;
 654    target_ulong mask;
 655
 656    tlb = &env->tlb->mmu.r4k.tlb[idx];
 657    /* The qemu TLB is flushed when the ASID changes, so no need to
 658       flush these entries again.  */
 659    if (tlb->G == 0 && tlb->ASID != ASID) {
 660        return;
 661    }
 662
 663    if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
 664        /* For tlbwr, we can shadow the discarded entry into
 665           a new (fake) TLB entry, as long as the guest can not
 666           tell that it's there.  */
 667        env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
 668        env->tlb->tlb_in_use++;
 669        return;
 670    }
 671
 672    /* 1k pages are not supported. */
 673    mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
 674    if (tlb->V0) {
 675        addr = tlb->VPN & ~mask;
 676#if defined(TARGET_MIPS64)
 677        if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
 678            addr |= 0x3FFFFF0000000000ULL;
 679        }
 680#endif
 681        end = addr | (mask >> 1);
 682        while (addr < end) {
 683            tlb_flush_page (env, addr);
 684            addr += TARGET_PAGE_SIZE;
 685        }
 686    }
 687    if (tlb->V1) {
 688        addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
 689#if defined(TARGET_MIPS64)
 690        if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
 691            addr |= 0x3FFFFF0000000000ULL;
 692        }
 693#endif
 694        end = addr | mask;
 695        while (addr - 1 < end) {
 696            tlb_flush_page (env, addr);
 697            addr += TARGET_PAGE_SIZE;
 698        }
 699    }
 700}
 701#endif
 702