1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26#include "hw/hw.h"
27#include "qapi/visitor.h"
28#include "hw/i386/pc.h"
29#include "hw/pci/pci.h"
30#include "qemu/timer.h"
31#include "sysemu/sysemu.h"
32#include "hw/acpi/acpi.h"
33#include "sysemu/kvm.h"
34#include "exec/address-spaces.h"
35
36#include "hw/i386/ich9.h"
37
38
39
40#ifdef DEBUG
41#define ICH9_DEBUG(fmt, ...) \
42do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0)
43#else
44#define ICH9_DEBUG(fmt, ...) do { } while (0)
45#endif
46
47static void pm_update_sci(ICH9LPCPMRegs *pm)
48{
49 int sci_level, pm1a_sts;
50
51 pm1a_sts = acpi_pm1_evt_get_sts(&pm->acpi_regs);
52
53 sci_level = (((pm1a_sts & pm->acpi_regs.pm1.evt.en) &
54 (ACPI_BITMASK_RT_CLOCK_ENABLE |
55 ACPI_BITMASK_POWER_BUTTON_ENABLE |
56 ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
57 ACPI_BITMASK_TIMER_ENABLE)) != 0);
58 qemu_set_irq(pm->irq, sci_level);
59
60
61 acpi_pm_tmr_update(&pm->acpi_regs,
62 (pm->acpi_regs.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
63 !(pm1a_sts & ACPI_BITMASK_TIMER_STATUS));
64}
65
66static void ich9_pm_update_sci_fn(ACPIREGS *regs)
67{
68 ICH9LPCPMRegs *pm = container_of(regs, ICH9LPCPMRegs, acpi_regs);
69 pm_update_sci(pm);
70}
71
72static uint64_t ich9_gpe_readb(void *opaque, hwaddr addr, unsigned width)
73{
74 ICH9LPCPMRegs *pm = opaque;
75 return acpi_gpe_ioport_readb(&pm->acpi_regs, addr);
76}
77
78static void ich9_gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
79 unsigned width)
80{
81 ICH9LPCPMRegs *pm = opaque;
82 acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val);
83}
84
85static const MemoryRegionOps ich9_gpe_ops = {
86 .read = ich9_gpe_readb,
87 .write = ich9_gpe_writeb,
88 .valid.min_access_size = 1,
89 .valid.max_access_size = 4,
90 .impl.min_access_size = 1,
91 .impl.max_access_size = 1,
92 .endianness = DEVICE_LITTLE_ENDIAN,
93};
94
95static uint64_t ich9_smi_readl(void *opaque, hwaddr addr, unsigned width)
96{
97 ICH9LPCPMRegs *pm = opaque;
98 switch (addr) {
99 case 0:
100 return pm->smi_en;
101 case 4:
102 return pm->smi_sts;
103 default:
104 return 0;
105 }
106}
107
108static void ich9_smi_writel(void *opaque, hwaddr addr, uint64_t val,
109 unsigned width)
110{
111 ICH9LPCPMRegs *pm = opaque;
112 switch (addr) {
113 case 0:
114 pm->smi_en = val;
115 break;
116 }
117}
118
119static const MemoryRegionOps ich9_smi_ops = {
120 .read = ich9_smi_readl,
121 .write = ich9_smi_writel,
122 .valid.min_access_size = 4,
123 .valid.max_access_size = 4,
124 .endianness = DEVICE_LITTLE_ENDIAN,
125};
126
127void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base)
128{
129 ICH9_DEBUG("to 0x%x\n", pm_io_base);
130
131 assert((pm_io_base & ICH9_PMIO_MASK) == 0);
132
133 pm->pm_io_base = pm_io_base;
134 memory_region_transaction_begin();
135 memory_region_set_enabled(&pm->io, pm->pm_io_base != 0);
136 memory_region_set_address(&pm->io, pm->pm_io_base);
137 memory_region_transaction_commit();
138}
139
140static int ich9_pm_post_load(void *opaque, int version_id)
141{
142 ICH9LPCPMRegs *pm = opaque;
143 uint32_t pm_io_base = pm->pm_io_base;
144 pm->pm_io_base = 0;
145 ich9_pm_iospace_update(pm, pm_io_base);
146 return 0;
147}
148
149#define VMSTATE_GPE_ARRAY(_field, _state) \
150 { \
151 .name = (stringify(_field)), \
152 .version_id = 0, \
153 .num = ICH9_PMIO_GPE0_LEN, \
154 .info = &vmstate_info_uint8, \
155 .size = sizeof(uint8_t), \
156 .flags = VMS_ARRAY | VMS_POINTER, \
157 .offset = vmstate_offset_pointer(_state, _field, uint8_t), \
158 }
159
160const VMStateDescription vmstate_ich9_pm = {
161 .name = "ich9_pm",
162 .version_id = 1,
163 .minimum_version_id = 1,
164 .minimum_version_id_old = 1,
165 .post_load = ich9_pm_post_load,
166 .fields = (VMStateField[]) {
167 VMSTATE_UINT16(acpi_regs.pm1.evt.sts, ICH9LPCPMRegs),
168 VMSTATE_UINT16(acpi_regs.pm1.evt.en, ICH9LPCPMRegs),
169 VMSTATE_UINT16(acpi_regs.pm1.cnt.cnt, ICH9LPCPMRegs),
170 VMSTATE_TIMER(acpi_regs.tmr.timer, ICH9LPCPMRegs),
171 VMSTATE_INT64(acpi_regs.tmr.overflow_time, ICH9LPCPMRegs),
172 VMSTATE_GPE_ARRAY(acpi_regs.gpe.sts, ICH9LPCPMRegs),
173 VMSTATE_GPE_ARRAY(acpi_regs.gpe.en, ICH9LPCPMRegs),
174 VMSTATE_UINT32(smi_en, ICH9LPCPMRegs),
175 VMSTATE_UINT32(smi_sts, ICH9LPCPMRegs),
176 VMSTATE_END_OF_LIST()
177 }
178};
179
180static void pm_reset(void *opaque)
181{
182 ICH9LPCPMRegs *pm = opaque;
183 ich9_pm_iospace_update(pm, 0);
184
185 acpi_pm1_evt_reset(&pm->acpi_regs);
186 acpi_pm1_cnt_reset(&pm->acpi_regs);
187 acpi_pm_tmr_reset(&pm->acpi_regs);
188 acpi_gpe_reset(&pm->acpi_regs);
189
190 if (kvm_enabled()) {
191
192
193 pm->smi_en |= ICH9_PMIO_SMI_EN_APMC_EN;
194 }
195
196 pm_update_sci(pm);
197}
198
199static void pm_powerdown_req(Notifier *n, void *opaque)
200{
201 ICH9LPCPMRegs *pm = container_of(n, ICH9LPCPMRegs, powerdown_notifier);
202
203 acpi_pm1_evt_power_down(&pm->acpi_regs);
204}
205
206void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
207 qemu_irq sci_irq)
208{
209 memory_region_init(&pm->io, OBJECT(lpc_pci), "ich9-pm", ICH9_PMIO_SIZE);
210 memory_region_set_enabled(&pm->io, false);
211 memory_region_add_subregion(pci_address_space_io(lpc_pci),
212 0, &pm->io);
213
214 acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io);
215 acpi_pm1_evt_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io);
216 acpi_pm1_cnt_init(&pm->acpi_regs, &pm->io, 2);
217
218 acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN);
219 memory_region_init_io(&pm->io_gpe, OBJECT(lpc_pci), &ich9_gpe_ops, pm,
220 "apci-gpe0", ICH9_PMIO_GPE0_LEN);
221 memory_region_add_subregion(&pm->io, ICH9_PMIO_GPE0_STS, &pm->io_gpe);
222
223 memory_region_init_io(&pm->io_smi, OBJECT(lpc_pci), &ich9_smi_ops, pm,
224 "apci-smi", 8);
225 memory_region_add_subregion(&pm->io, ICH9_PMIO_SMI_EN, &pm->io_smi);
226
227 pm->irq = sci_irq;
228 qemu_register_reset(pm_reset, pm);
229 pm->powerdown_notifier.notify = pm_powerdown_req;
230 qemu_register_powerdown_notifier(&pm->powerdown_notifier);
231}
232
233static void ich9_pm_get_gpe0_blk(Object *obj, Visitor *v,
234 void *opaque, const char *name,
235 Error **errp)
236{
237 ICH9LPCPMRegs *pm = opaque;
238 uint32_t value = pm->pm_io_base + ICH9_PMIO_GPE0_STS;
239
240 visit_type_uint32(v, &value, name, errp);
241}
242
243void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm, Error **errp)
244{
245 static const uint32_t gpe0_len = ICH9_PMIO_GPE0_LEN;
246
247 object_property_add_uint32_ptr(obj, ACPI_PM_PROP_PM_IO_BASE,
248 &pm->pm_io_base, errp);
249 object_property_add(obj, ACPI_PM_PROP_GPE0_BLK, "uint32",
250 ich9_pm_get_gpe0_blk,
251 NULL, NULL, pm, NULL);
252 object_property_add_uint32_ptr(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
253 &gpe0_len, errp);
254}
255
