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11#include "hw/hw.h"
12#include "hw/arm/pxa.h"
13#include "hw/sysbus.h"
14
15#define PXA255_DMA_NUM_CHANNELS 16
16#define PXA27X_DMA_NUM_CHANNELS 32
17
18#define PXA2XX_DMA_NUM_REQUESTS 75
19
20typedef struct {
21 uint32_t descr;
22 uint32_t src;
23 uint32_t dest;
24 uint32_t cmd;
25 uint32_t state;
26 int request;
27} PXA2xxDMAChannel;
28
29#define TYPE_PXA2XX_DMA "pxa2xx-dma"
30#define PXA2XX_DMA(obj) OBJECT_CHECK(PXA2xxDMAState, (obj), TYPE_PXA2XX_DMA)
31
32typedef struct PXA2xxDMAState {
33 SysBusDevice parent_obj;
34
35 MemoryRegion iomem;
36 qemu_irq irq;
37
38 uint32_t stopintr;
39 uint32_t eorintr;
40 uint32_t rasintr;
41 uint32_t startintr;
42 uint32_t endintr;
43
44 uint32_t align;
45 uint32_t pio;
46
47 int channels;
48 PXA2xxDMAChannel *chan;
49
50 uint8_t req[PXA2XX_DMA_NUM_REQUESTS];
51
52
53 int running;
54} PXA2xxDMAState;
55
56#define DCSR0 0x0000
57#define DCSR31 0x007c
58#define DALGN 0x00a0
59#define DPCSR 0x00a4
60#define DRQSR0 0x00e0
61#define DRQSR1 0x00e4
62#define DRQSR2 0x00e8
63#define DINT 0x00f0
64#define DRCMR0 0x0100
65#define DRCMR63 0x01fc
66#define D_CH0 0x0200
67#define DRCMR64 0x1100
68#define DRCMR74 0x1128
69
70
71#define DDADR 0x00
72#define DSADR 0x01
73#define DTADR 0x02
74#define DCMD 0x03
75
76
77#define DRCMR_CHLNUM 0x1f
78#define DRCMR_MAPVLD (1 << 7)
79#define DDADR_STOP (1 << 0)
80#define DDADR_BREN (1 << 1)
81#define DCMD_LEN 0x1fff
82#define DCMD_WIDTH(x) (1 << ((((x) >> 14) & 3) - 1))
83#define DCMD_SIZE(x) (4 << (((x) >> 16) & 3))
84#define DCMD_FLYBYT (1 << 19)
85#define DCMD_FLYBYS (1 << 20)
86#define DCMD_ENDIRQEN (1 << 21)
87#define DCMD_STARTIRQEN (1 << 22)
88#define DCMD_CMPEN (1 << 25)
89#define DCMD_FLOWTRG (1 << 28)
90#define DCMD_FLOWSRC (1 << 29)
91#define DCMD_INCTRGADDR (1 << 30)
92#define DCMD_INCSRCADDR (1 << 31)
93#define DCSR_BUSERRINTR (1 << 0)
94#define DCSR_STARTINTR (1 << 1)
95#define DCSR_ENDINTR (1 << 2)
96#define DCSR_STOPINTR (1 << 3)
97#define DCSR_RASINTR (1 << 4)
98#define DCSR_REQPEND (1 << 8)
99#define DCSR_EORINT (1 << 9)
100#define DCSR_CMPST (1 << 10)
101#define DCSR_MASKRUN (1 << 22)
102#define DCSR_RASIRQEN (1 << 23)
103#define DCSR_CLRCMPST (1 << 24)
104#define DCSR_SETCMPST (1 << 25)
105#define DCSR_EORSTOPEN (1 << 26)
106#define DCSR_EORJMPEN (1 << 27)
107#define DCSR_EORIRQEN (1 << 28)
108#define DCSR_STOPIRQEN (1 << 29)
109#define DCSR_NODESCFETCH (1 << 30)
110#define DCSR_RUN (1 << 31)
111
112static inline void pxa2xx_dma_update(PXA2xxDMAState *s, int ch)
113{
114 if (ch >= 0) {
115 if ((s->chan[ch].state & DCSR_STOPIRQEN) &&
116 (s->chan[ch].state & DCSR_STOPINTR))
117 s->stopintr |= 1 << ch;
118 else
119 s->stopintr &= ~(1 << ch);
120
121 if ((s->chan[ch].state & DCSR_EORIRQEN) &&
122 (s->chan[ch].state & DCSR_EORINT))
123 s->eorintr |= 1 << ch;
124 else
125 s->eorintr &= ~(1 << ch);
126
127 if ((s->chan[ch].state & DCSR_RASIRQEN) &&
128 (s->chan[ch].state & DCSR_RASINTR))
129 s->rasintr |= 1 << ch;
130 else
131 s->rasintr &= ~(1 << ch);
132
133 if (s->chan[ch].state & DCSR_STARTINTR)
134 s->startintr |= 1 << ch;
135 else
136 s->startintr &= ~(1 << ch);
137
138 if (s->chan[ch].state & DCSR_ENDINTR)
139 s->endintr |= 1 << ch;
140 else
141 s->endintr &= ~(1 << ch);
142 }
143
144 if (s->stopintr | s->eorintr | s->rasintr | s->startintr | s->endintr)
145 qemu_irq_raise(s->irq);
146 else
147 qemu_irq_lower(s->irq);
148}
149
150static inline void pxa2xx_dma_descriptor_fetch(
151 PXA2xxDMAState *s, int ch)
152{
153 uint32_t desc[4];
154 hwaddr daddr = s->chan[ch].descr & ~0xf;
155 if ((s->chan[ch].descr & DDADR_BREN) && (s->chan[ch].state & DCSR_CMPST))
156 daddr += 32;
157
158 cpu_physical_memory_read(daddr, desc, 16);
159 s->chan[ch].descr = desc[DDADR];
160 s->chan[ch].src = desc[DSADR];
161 s->chan[ch].dest = desc[DTADR];
162 s->chan[ch].cmd = desc[DCMD];
163
164 if (s->chan[ch].cmd & DCMD_FLOWSRC)
165 s->chan[ch].src &= ~3;
166 if (s->chan[ch].cmd & DCMD_FLOWTRG)
167 s->chan[ch].dest &= ~3;
168
169 if (s->chan[ch].cmd & (DCMD_CMPEN | DCMD_FLYBYS | DCMD_FLYBYT))
170 printf("%s: unsupported mode in channel %i\n", __FUNCTION__, ch);
171
172 if (s->chan[ch].cmd & DCMD_STARTIRQEN)
173 s->chan[ch].state |= DCSR_STARTINTR;
174}
175
176static void pxa2xx_dma_run(PXA2xxDMAState *s)
177{
178 int c, srcinc, destinc;
179 uint32_t n, size;
180 uint32_t width;
181 uint32_t length;
182 uint8_t buffer[32];
183 PXA2xxDMAChannel *ch;
184
185 if (s->running ++)
186 return;
187
188 while (s->running) {
189 s->running = 1;
190 for (c = 0; c < s->channels; c ++) {
191 ch = &s->chan[c];
192
193 while ((ch->state & DCSR_RUN) && !(ch->state & DCSR_STOPINTR)) {
194
195 if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) && !ch->request)
196 break;
197
198 length = ch->cmd & DCMD_LEN;
199 size = DCMD_SIZE(ch->cmd);
200 width = DCMD_WIDTH(ch->cmd);
201
202 srcinc = (ch->cmd & DCMD_INCSRCADDR) ? width : 0;
203 destinc = (ch->cmd & DCMD_INCTRGADDR) ? width : 0;
204
205 while (length) {
206 size = MIN(length, size);
207
208 for (n = 0; n < size; n += width) {
209 cpu_physical_memory_read(ch->src, buffer + n, width);
210 ch->src += srcinc;
211 }
212
213 for (n = 0; n < size; n += width) {
214 cpu_physical_memory_write(ch->dest, buffer + n, width);
215 ch->dest += destinc;
216 }
217
218 length -= size;
219
220 if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) &&
221 !ch->request) {
222 ch->state |= DCSR_EORINT;
223 if (ch->state & DCSR_EORSTOPEN)
224 ch->state |= DCSR_STOPINTR;
225 if ((ch->state & DCSR_EORJMPEN) &&
226 !(ch->state & DCSR_NODESCFETCH))
227 pxa2xx_dma_descriptor_fetch(s, c);
228 break;
229 }
230 }
231
232 ch->cmd = (ch->cmd & ~DCMD_LEN) | length;
233
234
235 if (!length) {
236 if (ch->cmd & DCMD_ENDIRQEN)
237 ch->state |= DCSR_ENDINTR;
238
239 if ((ch->state & DCSR_NODESCFETCH) ||
240 (ch->descr & DDADR_STOP) ||
241 (ch->state & DCSR_EORSTOPEN)) {
242 ch->state |= DCSR_STOPINTR;
243 ch->state &= ~DCSR_RUN;
244
245 break;
246 }
247
248 ch->state |= DCSR_STOPINTR;
249 break;
250 }
251 }
252 }
253
254 s->running --;
255 }
256}
257
258static uint64_t pxa2xx_dma_read(void *opaque, hwaddr offset,
259 unsigned size)
260{
261 PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
262 unsigned int channel;
263
264 if (size != 4) {
265 hw_error("%s: Bad access width\n", __FUNCTION__);
266 return 5;
267 }
268
269 switch (offset) {
270 case DRCMR64 ... DRCMR74:
271 offset -= DRCMR64 - DRCMR0 - (64 << 2);
272
273 case DRCMR0 ... DRCMR63:
274 channel = (offset - DRCMR0) >> 2;
275 return s->req[channel];
276
277 case DRQSR0:
278 case DRQSR1:
279 case DRQSR2:
280 return 0;
281
282 case DCSR0 ... DCSR31:
283 channel = offset >> 2;
284 if (s->chan[channel].request)
285 return s->chan[channel].state | DCSR_REQPEND;
286 return s->chan[channel].state;
287
288 case DINT:
289 return s->stopintr | s->eorintr | s->rasintr |
290 s->startintr | s->endintr;
291
292 case DALGN:
293 return s->align;
294
295 case DPCSR:
296 return s->pio;
297 }
298
299 if (offset >= D_CH0 && offset < D_CH0 + (s->channels << 4)) {
300 channel = (offset - D_CH0) >> 4;
301 switch ((offset & 0x0f) >> 2) {
302 case DDADR:
303 return s->chan[channel].descr;
304 case DSADR:
305 return s->chan[channel].src;
306 case DTADR:
307 return s->chan[channel].dest;
308 case DCMD:
309 return s->chan[channel].cmd;
310 }
311 }
312
313 hw_error("%s: Bad offset 0x" TARGET_FMT_plx "\n", __FUNCTION__, offset);
314 return 7;
315}
316
317static void pxa2xx_dma_write(void *opaque, hwaddr offset,
318 uint64_t value, unsigned size)
319{
320 PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
321 unsigned int channel;
322
323 if (size != 4) {
324 hw_error("%s: Bad access width\n", __FUNCTION__);
325 return;
326 }
327
328 switch (offset) {
329 case DRCMR64 ... DRCMR74:
330 offset -= DRCMR64 - DRCMR0 - (64 << 2);
331
332 case DRCMR0 ... DRCMR63:
333 channel = (offset - DRCMR0) >> 2;
334
335 if (value & DRCMR_MAPVLD)
336 if ((value & DRCMR_CHLNUM) > s->channels)
337 hw_error("%s: Bad DMA channel %i\n",
338 __FUNCTION__, (unsigned)value & DRCMR_CHLNUM);
339
340 s->req[channel] = value;
341 break;
342
343 case DRQSR0:
344 case DRQSR1:
345 case DRQSR2:
346
347 break;
348
349 case DCSR0 ... DCSR31:
350 channel = offset >> 2;
351 s->chan[channel].state &= 0x0000071f & ~(value &
352 (DCSR_EORINT | DCSR_ENDINTR |
353 DCSR_STARTINTR | DCSR_BUSERRINTR));
354 s->chan[channel].state |= value & 0xfc800000;
355
356 if (s->chan[channel].state & DCSR_STOPIRQEN)
357 s->chan[channel].state &= ~DCSR_STOPINTR;
358
359 if (value & DCSR_NODESCFETCH) {
360
361 if (value & DCSR_RUN) {
362 s->chan[channel].state &= ~DCSR_STOPINTR;
363 pxa2xx_dma_run(s);
364 }
365 } else {
366
367 if (value & DCSR_RUN) {
368 s->chan[channel].state &= ~DCSR_STOPINTR;
369 pxa2xx_dma_descriptor_fetch(s, channel);
370 pxa2xx_dma_run(s);
371 }
372 }
373
374
375 if (!(value & (DCSR_RUN | DCSR_MASKRUN)))
376 s->chan[channel].state |= DCSR_STOPINTR;
377
378 if (value & DCSR_CLRCMPST)
379 s->chan[channel].state &= ~DCSR_CMPST;
380 if (value & DCSR_SETCMPST)
381 s->chan[channel].state |= DCSR_CMPST;
382
383 pxa2xx_dma_update(s, channel);
384 break;
385
386 case DALGN:
387 s->align = value;
388 break;
389
390 case DPCSR:
391 s->pio = value & 0x80000001;
392 break;
393
394 default:
395 if (offset >= D_CH0 && offset < D_CH0 + (s->channels << 4)) {
396 channel = (offset - D_CH0) >> 4;
397 switch ((offset & 0x0f) >> 2) {
398 case DDADR:
399 s->chan[channel].descr = value;
400 break;
401 case DSADR:
402 s->chan[channel].src = value;
403 break;
404 case DTADR:
405 s->chan[channel].dest = value;
406 break;
407 case DCMD:
408 s->chan[channel].cmd = value;
409 break;
410 default:
411 goto fail;
412 }
413
414 break;
415 }
416 fail:
417 hw_error("%s: Bad offset " TARGET_FMT_plx "\n", __FUNCTION__, offset);
418 }
419}
420
421static const MemoryRegionOps pxa2xx_dma_ops = {
422 .read = pxa2xx_dma_read,
423 .write = pxa2xx_dma_write,
424 .endianness = DEVICE_NATIVE_ENDIAN,
425};
426
427static void pxa2xx_dma_request(void *opaque, int req_num, int on)
428{
429 PXA2xxDMAState *s = opaque;
430 int ch;
431 if (req_num < 0 || req_num >= PXA2XX_DMA_NUM_REQUESTS)
432 hw_error("%s: Bad DMA request %i\n", __FUNCTION__, req_num);
433
434 if (!(s->req[req_num] & DRCMR_MAPVLD))
435 return;
436 ch = s->req[req_num] & DRCMR_CHLNUM;
437
438 if (!s->chan[ch].request && on)
439 s->chan[ch].state |= DCSR_RASINTR;
440 else
441 s->chan[ch].state &= ~DCSR_RASINTR;
442 if (s->chan[ch].request && !on)
443 s->chan[ch].state |= DCSR_EORINT;
444
445 s->chan[ch].request = on;
446 if (on) {
447 pxa2xx_dma_run(s);
448 pxa2xx_dma_update(s, ch);
449 }
450}
451
452static int pxa2xx_dma_init(SysBusDevice *sbd)
453{
454 DeviceState *dev = DEVICE(sbd);
455 PXA2xxDMAState *s = PXA2XX_DMA(dev);
456 int i;
457
458 if (s->channels <= 0) {
459 return -1;
460 }
461
462 s->chan = g_malloc0(sizeof(PXA2xxDMAChannel) * s->channels);
463
464 memset(s->chan, 0, sizeof(PXA2xxDMAChannel) * s->channels);
465 for (i = 0; i < s->channels; i ++)
466 s->chan[i].state = DCSR_STOPINTR;
467
468 memset(s->req, 0, sizeof(uint8_t) * PXA2XX_DMA_NUM_REQUESTS);
469
470 qdev_init_gpio_in(dev, pxa2xx_dma_request, PXA2XX_DMA_NUM_REQUESTS);
471
472 memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_dma_ops, s,
473 "pxa2xx.dma", 0x00010000);
474 sysbus_init_mmio(sbd, &s->iomem);
475 sysbus_init_irq(sbd, &s->irq);
476
477 return 0;
478}
479
480DeviceState *pxa27x_dma_init(hwaddr base, qemu_irq irq)
481{
482 DeviceState *dev;
483
484 dev = qdev_create(NULL, "pxa2xx-dma");
485 qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS);
486 qdev_init_nofail(dev);
487
488 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
489 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
490
491 return dev;
492}
493
494DeviceState *pxa255_dma_init(hwaddr base, qemu_irq irq)
495{
496 DeviceState *dev;
497
498 dev = qdev_create(NULL, "pxa2xx-dma");
499 qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS);
500 qdev_init_nofail(dev);
501
502 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
503 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
504
505 return dev;
506}
507
508static bool is_version_0(void *opaque, int version_id)
509{
510 return version_id == 0;
511}
512
513static VMStateDescription vmstate_pxa2xx_dma_chan = {
514 .name = "pxa2xx_dma_chan",
515 .version_id = 1,
516 .minimum_version_id = 1,
517 .minimum_version_id_old = 1,
518 .fields = (VMStateField[]) {
519 VMSTATE_UINT32(descr, PXA2xxDMAChannel),
520 VMSTATE_UINT32(src, PXA2xxDMAChannel),
521 VMSTATE_UINT32(dest, PXA2xxDMAChannel),
522 VMSTATE_UINT32(cmd, PXA2xxDMAChannel),
523 VMSTATE_UINT32(state, PXA2xxDMAChannel),
524 VMSTATE_INT32(request, PXA2xxDMAChannel),
525 VMSTATE_END_OF_LIST(),
526 },
527};
528
529static VMStateDescription vmstate_pxa2xx_dma = {
530 .name = "pxa2xx_dma",
531 .version_id = 1,
532 .minimum_version_id = 0,
533 .minimum_version_id_old = 0,
534 .fields = (VMStateField[]) {
535 VMSTATE_UNUSED_TEST(is_version_0, 4),
536 VMSTATE_UINT32(stopintr, PXA2xxDMAState),
537 VMSTATE_UINT32(eorintr, PXA2xxDMAState),
538 VMSTATE_UINT32(rasintr, PXA2xxDMAState),
539 VMSTATE_UINT32(startintr, PXA2xxDMAState),
540 VMSTATE_UINT32(endintr, PXA2xxDMAState),
541 VMSTATE_UINT32(align, PXA2xxDMAState),
542 VMSTATE_UINT32(pio, PXA2xxDMAState),
543 VMSTATE_BUFFER(req, PXA2xxDMAState),
544 VMSTATE_STRUCT_VARRAY_POINTER_INT32(chan, PXA2xxDMAState, channels,
545 vmstate_pxa2xx_dma_chan, PXA2xxDMAChannel),
546 VMSTATE_END_OF_LIST(),
547 },
548};
549
550static Property pxa2xx_dma_properties[] = {
551 DEFINE_PROP_INT32("channels", PXA2xxDMAState, channels, -1),
552 DEFINE_PROP_END_OF_LIST(),
553};
554
555static void pxa2xx_dma_class_init(ObjectClass *klass, void *data)
556{
557 DeviceClass *dc = DEVICE_CLASS(klass);
558 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
559
560 k->init = pxa2xx_dma_init;
561 dc->desc = "PXA2xx DMA controller";
562 dc->vmsd = &vmstate_pxa2xx_dma;
563 dc->props = pxa2xx_dma_properties;
564}
565
566static const TypeInfo pxa2xx_dma_info = {
567 .name = TYPE_PXA2XX_DMA,
568 .parent = TYPE_SYS_BUS_DEVICE,
569 .instance_size = sizeof(PXA2xxDMAState),
570 .class_init = pxa2xx_dma_class_init,
571};
572
573static void pxa2xx_dma_register_types(void)
574{
575 type_register_static(&pxa2xx_dma_info);
576}
577
578type_init(pxa2xx_dma_register_types)
579
