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34#include "hw/hw.h"
35#include "hw/sysbus.h"
36#include "net/net.h"
37#include "sysemu/sysemu.h"
38#include "trace.h"
39
40
41
42
43#undef USE_RECSMALL
44
45#define GET_FIELD(v, field) (((v) & (field)) >> (field ## _LBN))
46#define GET_REGBIT(s, reg, field) ((s)->regs[reg] & (reg ## _ ## field))
47#define GET_REGFIELD(s, reg, field) \
48 GET_FIELD((s)->regs[reg], reg ## _ ## field)
49
50#define SET_FIELD(v, field, data) \
51 ((v) = (((v) & ~(field)) | (((data) << (field ## _LBN)) & (field))))
52#define SET_REGFIELD(s, reg, field, data) \
53 SET_FIELD((s)->regs[reg], reg ## _ ## field, data)
54
55
56enum {
57 MII_BMCR,
58 MII_BMSR,
59 MII_PHYIDR1,
60 MII_PHYIDR2,
61 MII_ANAR,
62 MII_ANLPAR,
63 MII_REG_MAX = 16,
64};
65
66typedef struct Mii {
67 uint16_t regs[MII_REG_MAX];
68 bool link_ok;
69} Mii;
70
71static void mii_set_link(Mii *s, bool link_ok)
72{
73 if (link_ok) {
74 s->regs[MII_BMSR] |= 0x4;
75 s->regs[MII_ANLPAR] |= 0x01e1;
76 } else {
77 s->regs[MII_BMSR] &= ~0x4;
78 s->regs[MII_ANLPAR] &= 0x01ff;
79 }
80 s->link_ok = link_ok;
81}
82
83static void mii_reset(Mii *s)
84{
85 memset(s->regs, 0, sizeof(s->regs));
86 s->regs[MII_BMCR] = 0x1000;
87 s->regs[MII_BMSR] = 0x7848;
88 s->regs[MII_PHYIDR1] = 0x2000;
89 s->regs[MII_PHYIDR2] = 0x5c90;
90 s->regs[MII_ANAR] = 0x01e1;
91 mii_set_link(s, s->link_ok);
92}
93
94static void mii_ro(Mii *s, uint16_t v)
95{
96}
97
98static void mii_write_bmcr(Mii *s, uint16_t v)
99{
100 if (v & 0x8000) {
101 mii_reset(s);
102 } else {
103 s->regs[MII_BMCR] = v;
104 }
105}
106
107static void mii_write_host(Mii *s, unsigned idx, uint16_t v)
108{
109 static void (*reg_write[MII_REG_MAX])(Mii *s, uint16_t v) = {
110 [MII_BMCR] = mii_write_bmcr,
111 [MII_BMSR] = mii_ro,
112 [MII_PHYIDR1] = mii_ro,
113 [MII_PHYIDR2] = mii_ro,
114 };
115
116 if (idx < MII_REG_MAX) {
117 trace_open_eth_mii_write(idx, v);
118 if (reg_write[idx]) {
119 reg_write[idx](s, v);
120 } else {
121 s->regs[idx] = v;
122 }
123 }
124}
125
126static uint16_t mii_read_host(Mii *s, unsigned idx)
127{
128 trace_open_eth_mii_read(idx, s->regs[idx]);
129 return s->regs[idx];
130}
131
132
133enum {
134 MODER,
135 INT_SOURCE,
136 INT_MASK,
137 IPGT,
138 IPGR1,
139 IPGR2,
140 PACKETLEN,
141 COLLCONF,
142 TX_BD_NUM,
143 CTRLMODER,
144 MIIMODER,
145 MIICOMMAND,
146 MIIADDRESS,
147 MIITX_DATA,
148 MIIRX_DATA,
149 MIISTATUS,
150 MAC_ADDR0,
151 MAC_ADDR1,
152 HASH0,
153 HASH1,
154 TXCTRL,
155 REG_MAX,
156};
157
158enum {
159 MODER_RECSMALL = 0x10000,
160 MODER_PAD = 0x8000,
161 MODER_HUGEN = 0x4000,
162 MODER_RST = 0x800,
163 MODER_LOOPBCK = 0x80,
164 MODER_PRO = 0x20,
165 MODER_IAM = 0x10,
166 MODER_BRO = 0x8,
167 MODER_TXEN = 0x2,
168 MODER_RXEN = 0x1,
169};
170
171enum {
172 INT_SOURCE_RXB = 0x4,
173 INT_SOURCE_TXB = 0x1,
174};
175
176enum {
177 PACKETLEN_MINFL = 0xffff0000,
178 PACKETLEN_MINFL_LBN = 16,
179 PACKETLEN_MAXFL = 0xffff,
180 PACKETLEN_MAXFL_LBN = 0,
181};
182
183enum {
184 MIICOMMAND_WCTRLDATA = 0x4,
185 MIICOMMAND_RSTAT = 0x2,
186 MIICOMMAND_SCANSTAT = 0x1,
187};
188
189enum {
190 MIIADDRESS_RGAD = 0x1f00,
191 MIIADDRESS_RGAD_LBN = 8,
192 MIIADDRESS_FIAD = 0x1f,
193 MIIADDRESS_FIAD_LBN = 0,
194};
195
196enum {
197 MIITX_DATA_CTRLDATA = 0xffff,
198 MIITX_DATA_CTRLDATA_LBN = 0,
199};
200
201enum {
202 MIIRX_DATA_PRSD = 0xffff,
203 MIIRX_DATA_PRSD_LBN = 0,
204};
205
206enum {
207 MIISTATUS_LINKFAIL = 0x1,
208 MIISTATUS_LINKFAIL_LBN = 0,
209};
210
211enum {
212 MAC_ADDR0_BYTE2 = 0xff000000,
213 MAC_ADDR0_BYTE2_LBN = 24,
214 MAC_ADDR0_BYTE3 = 0xff0000,
215 MAC_ADDR0_BYTE3_LBN = 16,
216 MAC_ADDR0_BYTE4 = 0xff00,
217 MAC_ADDR0_BYTE4_LBN = 8,
218 MAC_ADDR0_BYTE5 = 0xff,
219 MAC_ADDR0_BYTE5_LBN = 0,
220};
221
222enum {
223 MAC_ADDR1_BYTE0 = 0xff00,
224 MAC_ADDR1_BYTE0_LBN = 8,
225 MAC_ADDR1_BYTE1 = 0xff,
226 MAC_ADDR1_BYTE1_LBN = 0,
227};
228
229enum {
230 TXD_LEN = 0xffff0000,
231 TXD_LEN_LBN = 16,
232 TXD_RD = 0x8000,
233 TXD_IRQ = 0x4000,
234 TXD_WR = 0x2000,
235 TXD_PAD = 0x1000,
236 TXD_CRC = 0x800,
237 TXD_UR = 0x100,
238 TXD_RTRY = 0xf0,
239 TXD_RTRY_LBN = 4,
240 TXD_RL = 0x8,
241 TXD_LC = 0x4,
242 TXD_DF = 0x2,
243 TXD_CS = 0x1,
244};
245
246enum {
247 RXD_LEN = 0xffff0000,
248 RXD_LEN_LBN = 16,
249 RXD_E = 0x8000,
250 RXD_IRQ = 0x4000,
251 RXD_WRAP = 0x2000,
252 RXD_CF = 0x100,
253 RXD_M = 0x80,
254 RXD_OR = 0x40,
255 RXD_IS = 0x20,
256 RXD_DN = 0x10,
257 RXD_TL = 0x8,
258 RXD_SF = 0x4,
259 RXD_CRC = 0x2,
260 RXD_LC = 0x1,
261};
262
263typedef struct desc {
264 uint32_t len_flags;
265 uint32_t buf_ptr;
266} desc;
267
268#define DEFAULT_PHY 1
269
270#define TYPE_OPEN_ETH "open_eth"
271#define OPEN_ETH(obj) OBJECT_CHECK(OpenEthState, (obj), TYPE_OPEN_ETH)
272
273typedef struct OpenEthState {
274 SysBusDevice parent_obj;
275
276 NICState *nic;
277 NICConf conf;
278 MemoryRegion reg_io;
279 MemoryRegion desc_io;
280 qemu_irq irq;
281
282 Mii mii;
283 uint32_t regs[REG_MAX];
284 unsigned tx_desc;
285 unsigned rx_desc;
286 desc desc[128];
287} OpenEthState;
288
289static desc *rx_desc(OpenEthState *s)
290{
291 return s->desc + s->rx_desc;
292}
293
294static desc *tx_desc(OpenEthState *s)
295{
296 return s->desc + s->tx_desc;
297}
298
299static void open_eth_update_irq(OpenEthState *s,
300 uint32_t old, uint32_t new)
301{
302 if (!old != !new) {
303 trace_open_eth_update_irq(new);
304 qemu_set_irq(s->irq, new);
305 }
306}
307
308static void open_eth_int_source_write(OpenEthState *s,
309 uint32_t val)
310{
311 uint32_t old_val = s->regs[INT_SOURCE];
312
313 s->regs[INT_SOURCE] = val;
314 open_eth_update_irq(s, old_val & s->regs[INT_MASK],
315 s->regs[INT_SOURCE] & s->regs[INT_MASK]);
316}
317
318static void open_eth_set_link_status(NetClientState *nc)
319{
320 OpenEthState *s = qemu_get_nic_opaque(nc);
321
322 if (GET_REGBIT(s, MIICOMMAND, SCANSTAT)) {
323 SET_REGFIELD(s, MIISTATUS, LINKFAIL, nc->link_down);
324 }
325 mii_set_link(&s->mii, !nc->link_down);
326}
327
328static void open_eth_reset(void *opaque)
329{
330 OpenEthState *s = opaque;
331
332 memset(s->regs, 0, sizeof(s->regs));
333 s->regs[MODER] = 0xa000;
334 s->regs[IPGT] = 0x12;
335 s->regs[IPGR1] = 0xc;
336 s->regs[IPGR2] = 0x12;
337 s->regs[PACKETLEN] = 0x400600;
338 s->regs[COLLCONF] = 0xf003f;
339 s->regs[TX_BD_NUM] = 0x40;
340 s->regs[MIIMODER] = 0x64;
341
342 s->tx_desc = 0;
343 s->rx_desc = 0x40;
344
345 mii_reset(&s->mii);
346 open_eth_set_link_status(qemu_get_queue(s->nic));
347}
348
349static int open_eth_can_receive(NetClientState *nc)
350{
351 OpenEthState *s = qemu_get_nic_opaque(nc);
352
353 return GET_REGBIT(s, MODER, RXEN) &&
354 (s->regs[TX_BD_NUM] < 0x80) &&
355 (rx_desc(s)->len_flags & RXD_E);
356}
357
358static ssize_t open_eth_receive(NetClientState *nc,
359 const uint8_t *buf, size_t size)
360{
361 OpenEthState *s = qemu_get_nic_opaque(nc);
362 size_t maxfl = GET_REGFIELD(s, PACKETLEN, MAXFL);
363 size_t minfl = GET_REGFIELD(s, PACKETLEN, MINFL);
364 size_t fcsl = 4;
365 bool miss = true;
366
367 trace_open_eth_receive((unsigned)size);
368
369 if (size >= 6) {
370 static const uint8_t bcast_addr[] = {
371 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
372 };
373 if (memcmp(buf, bcast_addr, sizeof(bcast_addr)) == 0) {
374 miss = GET_REGBIT(s, MODER, BRO);
375 } else if ((buf[0] & 0x1) || GET_REGBIT(s, MODER, IAM)) {
376 unsigned mcast_idx = compute_mcast_idx(buf);
377 miss = !(s->regs[HASH0 + mcast_idx / 32] &
378 (1 << (mcast_idx % 32)));
379 trace_open_eth_receive_mcast(
380 mcast_idx, s->regs[HASH0], s->regs[HASH1]);
381 } else {
382 miss = GET_REGFIELD(s, MAC_ADDR1, BYTE0) != buf[0] ||
383 GET_REGFIELD(s, MAC_ADDR1, BYTE1) != buf[1] ||
384 GET_REGFIELD(s, MAC_ADDR0, BYTE2) != buf[2] ||
385 GET_REGFIELD(s, MAC_ADDR0, BYTE3) != buf[3] ||
386 GET_REGFIELD(s, MAC_ADDR0, BYTE4) != buf[4] ||
387 GET_REGFIELD(s, MAC_ADDR0, BYTE5) != buf[5];
388 }
389 }
390
391 if (miss && !GET_REGBIT(s, MODER, PRO)) {
392 trace_open_eth_receive_reject();
393 return size;
394 }
395
396#ifdef USE_RECSMALL
397 if (GET_REGBIT(s, MODER, RECSMALL) || size >= minfl) {
398#else
399 {
400#endif
401 static const uint8_t zero[64] = {0};
402 desc *desc = rx_desc(s);
403 size_t copy_size = GET_REGBIT(s, MODER, HUGEN) ? 65536 : maxfl;
404
405 desc->len_flags &= ~(RXD_CF | RXD_M | RXD_OR |
406 RXD_IS | RXD_DN | RXD_TL | RXD_SF | RXD_CRC | RXD_LC);
407
408 if (copy_size > size) {
409 copy_size = size;
410 } else {
411 fcsl = 0;
412 }
413 if (miss) {
414 desc->len_flags |= RXD_M;
415 }
416 if (GET_REGBIT(s, MODER, HUGEN) && size > maxfl) {
417 desc->len_flags |= RXD_TL;
418 }
419#ifdef USE_RECSMALL
420 if (size < minfl) {
421 desc->len_flags |= RXD_SF;
422 }
423#endif
424
425 cpu_physical_memory_write(desc->buf_ptr, buf, copy_size);
426
427 if (GET_REGBIT(s, MODER, PAD) && copy_size < minfl) {
428 if (minfl - copy_size > fcsl) {
429 fcsl = 0;
430 } else {
431 fcsl -= minfl - copy_size;
432 }
433 while (copy_size < minfl) {
434 size_t zero_sz = minfl - copy_size < sizeof(zero) ?
435 minfl - copy_size : sizeof(zero);
436
437 cpu_physical_memory_write(desc->buf_ptr + copy_size,
438 zero, zero_sz);
439 copy_size += zero_sz;
440 }
441 }
442
443
444
445
446
447 cpu_physical_memory_write(desc->buf_ptr + copy_size, zero, fcsl);
448 copy_size += fcsl;
449
450 SET_FIELD(desc->len_flags, RXD_LEN, copy_size);
451
452 if ((desc->len_flags & RXD_WRAP) || s->rx_desc == 0x7f) {
453 s->rx_desc = s->regs[TX_BD_NUM];
454 } else {
455 ++s->rx_desc;
456 }
457 desc->len_flags &= ~RXD_E;
458
459 trace_open_eth_receive_desc(desc->buf_ptr, desc->len_flags);
460
461 if (desc->len_flags & RXD_IRQ) {
462 open_eth_int_source_write(s,
463 s->regs[INT_SOURCE] | INT_SOURCE_RXB);
464 }
465 }
466 return size;
467}
468
469static void open_eth_cleanup(NetClientState *nc)
470{
471}
472
473static NetClientInfo net_open_eth_info = {
474 .type = NET_CLIENT_OPTIONS_KIND_NIC,
475 .size = sizeof(NICState),
476 .can_receive = open_eth_can_receive,
477 .receive = open_eth_receive,
478 .cleanup = open_eth_cleanup,
479 .link_status_changed = open_eth_set_link_status,
480};
481
482static void open_eth_start_xmit(OpenEthState *s, desc *tx)
483{
484 uint8_t buf[65536];
485 unsigned len = GET_FIELD(tx->len_flags, TXD_LEN);
486 unsigned tx_len = len;
487
488 if ((tx->len_flags & TXD_PAD) &&
489 tx_len < GET_REGFIELD(s, PACKETLEN, MINFL)) {
490 tx_len = GET_REGFIELD(s, PACKETLEN, MINFL);
491 }
492 if (!GET_REGBIT(s, MODER, HUGEN) &&
493 tx_len > GET_REGFIELD(s, PACKETLEN, MAXFL)) {
494 tx_len = GET_REGFIELD(s, PACKETLEN, MAXFL);
495 }
496
497 trace_open_eth_start_xmit(tx->buf_ptr, len, tx_len);
498
499 if (len > tx_len) {
500 len = tx_len;
501 }
502 cpu_physical_memory_read(tx->buf_ptr, buf, len);
503 if (tx_len > len) {
504 memset(buf + len, 0, tx_len - len);
505 }
506 qemu_send_packet(qemu_get_queue(s->nic), buf, tx_len);
507
508 if (tx->len_flags & TXD_WR) {
509 s->tx_desc = 0;
510 } else {
511 ++s->tx_desc;
512 if (s->tx_desc >= s->regs[TX_BD_NUM]) {
513 s->tx_desc = 0;
514 }
515 }
516 tx->len_flags &= ~(TXD_RD | TXD_UR |
517 TXD_RTRY | TXD_RL | TXD_LC | TXD_DF | TXD_CS);
518 if (tx->len_flags & TXD_IRQ) {
519 open_eth_int_source_write(s, s->regs[INT_SOURCE] | INT_SOURCE_TXB);
520 }
521
522}
523
524static void open_eth_check_start_xmit(OpenEthState *s)
525{
526 desc *tx = tx_desc(s);
527 if (GET_REGBIT(s, MODER, TXEN) && s->regs[TX_BD_NUM] > 0 &&
528 (tx->len_flags & TXD_RD) &&
529 GET_FIELD(tx->len_flags, TXD_LEN) > 4) {
530 open_eth_start_xmit(s, tx);
531 }
532}
533
534static uint64_t open_eth_reg_read(void *opaque,
535 hwaddr addr, unsigned int size)
536{
537 static uint32_t (*reg_read[REG_MAX])(OpenEthState *s) = {
538 };
539 OpenEthState *s = opaque;
540 unsigned idx = addr / 4;
541 uint64_t v = 0;
542
543 if (idx < REG_MAX) {
544 if (reg_read[idx]) {
545 v = reg_read[idx](s);
546 } else {
547 v = s->regs[idx];
548 }
549 }
550 trace_open_eth_reg_read((uint32_t)addr, (uint32_t)v);
551 return v;
552}
553
554static void open_eth_ro(OpenEthState *s, uint32_t val)
555{
556}
557
558static void open_eth_moder_host_write(OpenEthState *s, uint32_t val)
559{
560 uint32_t set = val & ~s->regs[MODER];
561
562 if (set & MODER_RST) {
563 open_eth_reset(s);
564 }
565
566 s->regs[MODER] = val;
567
568 if (set & MODER_RXEN) {
569 s->rx_desc = s->regs[TX_BD_NUM];
570 }
571 if (set & MODER_TXEN) {
572 s->tx_desc = 0;
573 open_eth_check_start_xmit(s);
574 }
575}
576
577static void open_eth_int_source_host_write(OpenEthState *s, uint32_t val)
578{
579 uint32_t old = s->regs[INT_SOURCE];
580
581 s->regs[INT_SOURCE] &= ~val;
582 open_eth_update_irq(s, old & s->regs[INT_MASK],
583 s->regs[INT_SOURCE] & s->regs[INT_MASK]);
584}
585
586static void open_eth_int_mask_host_write(OpenEthState *s, uint32_t val)
587{
588 uint32_t old = s->regs[INT_MASK];
589
590 s->regs[INT_MASK] = val;
591 open_eth_update_irq(s, s->regs[INT_SOURCE] & old,
592 s->regs[INT_SOURCE] & s->regs[INT_MASK]);
593}
594
595static void open_eth_mii_command_host_write(OpenEthState *s, uint32_t val)
596{
597 unsigned fiad = GET_REGFIELD(s, MIIADDRESS, FIAD);
598 unsigned rgad = GET_REGFIELD(s, MIIADDRESS, RGAD);
599
600 if (val & MIICOMMAND_WCTRLDATA) {
601 if (fiad == DEFAULT_PHY) {
602 mii_write_host(&s->mii, rgad,
603 GET_REGFIELD(s, MIITX_DATA, CTRLDATA));
604 }
605 }
606 if (val & MIICOMMAND_RSTAT) {
607 if (fiad == DEFAULT_PHY) {
608 SET_REGFIELD(s, MIIRX_DATA, PRSD,
609 mii_read_host(&s->mii, rgad));
610 } else {
611 s->regs[MIIRX_DATA] = 0xffff;
612 }
613 SET_REGFIELD(s, MIISTATUS, LINKFAIL, qemu_get_queue(s->nic)->link_down);
614 }
615}
616
617static void open_eth_mii_tx_host_write(OpenEthState *s, uint32_t val)
618{
619 SET_REGFIELD(s, MIITX_DATA, CTRLDATA, val);
620 if (GET_REGFIELD(s, MIIADDRESS, FIAD) == DEFAULT_PHY) {
621 mii_write_host(&s->mii, GET_REGFIELD(s, MIIADDRESS, RGAD),
622 GET_REGFIELD(s, MIITX_DATA, CTRLDATA));
623 }
624}
625
626static void open_eth_reg_write(void *opaque,
627 hwaddr addr, uint64_t val, unsigned int size)
628{
629 static void (*reg_write[REG_MAX])(OpenEthState *s, uint32_t val) = {
630 [MODER] = open_eth_moder_host_write,
631 [INT_SOURCE] = open_eth_int_source_host_write,
632 [INT_MASK] = open_eth_int_mask_host_write,
633 [MIICOMMAND] = open_eth_mii_command_host_write,
634 [MIITX_DATA] = open_eth_mii_tx_host_write,
635 [MIISTATUS] = open_eth_ro,
636 };
637 OpenEthState *s = opaque;
638 unsigned idx = addr / 4;
639
640 if (idx < REG_MAX) {
641 trace_open_eth_reg_write((uint32_t)addr, (uint32_t)val);
642 if (reg_write[idx]) {
643 reg_write[idx](s, val);
644 } else {
645 s->regs[idx] = val;
646 }
647 }
648}
649
650static uint64_t open_eth_desc_read(void *opaque,
651 hwaddr addr, unsigned int size)
652{
653 OpenEthState *s = opaque;
654 uint64_t v = 0;
655
656 addr &= 0x3ff;
657 memcpy(&v, (uint8_t *)s->desc + addr, size);
658 trace_open_eth_desc_read((uint32_t)addr, (uint32_t)v);
659 return v;
660}
661
662static void open_eth_desc_write(void *opaque,
663 hwaddr addr, uint64_t val, unsigned int size)
664{
665 OpenEthState *s = opaque;
666
667 addr &= 0x3ff;
668 trace_open_eth_desc_write((uint32_t)addr, (uint32_t)val);
669 memcpy((uint8_t *)s->desc + addr, &val, size);
670 open_eth_check_start_xmit(s);
671}
672
673
674static const MemoryRegionOps open_eth_reg_ops = {
675 .read = open_eth_reg_read,
676 .write = open_eth_reg_write,
677};
678
679static const MemoryRegionOps open_eth_desc_ops = {
680 .read = open_eth_desc_read,
681 .write = open_eth_desc_write,
682};
683
684static int sysbus_open_eth_init(SysBusDevice *sbd)
685{
686 DeviceState *dev = DEVICE(sbd);
687 OpenEthState *s = OPEN_ETH(dev);
688
689 memory_region_init_io(&s->reg_io, OBJECT(dev), &open_eth_reg_ops, s,
690 "open_eth.regs", 0x54);
691 sysbus_init_mmio(sbd, &s->reg_io);
692
693 memory_region_init_io(&s->desc_io, OBJECT(dev), &open_eth_desc_ops, s,
694 "open_eth.desc", 0x400);
695 sysbus_init_mmio(sbd, &s->desc_io);
696
697 sysbus_init_irq(sbd, &s->irq);
698
699 s->nic = qemu_new_nic(&net_open_eth_info, &s->conf,
700 object_get_typename(OBJECT(s)), dev->id, s);
701 return 0;
702}
703
704static void qdev_open_eth_reset(DeviceState *dev)
705{
706 OpenEthState *d = OPEN_ETH(dev);
707
708 open_eth_reset(d);
709}
710
711static Property open_eth_properties[] = {
712 DEFINE_NIC_PROPERTIES(OpenEthState, conf),
713 DEFINE_PROP_END_OF_LIST(),
714};
715
716static void open_eth_class_init(ObjectClass *klass, void *data)
717{
718 DeviceClass *dc = DEVICE_CLASS(klass);
719 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
720
721 k->init = sysbus_open_eth_init;
722 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
723 dc->desc = "Opencores 10/100 Mbit Ethernet";
724 dc->reset = qdev_open_eth_reset;
725 dc->props = open_eth_properties;
726}
727
728static const TypeInfo open_eth_info = {
729 .name = TYPE_OPEN_ETH,
730 .parent = TYPE_SYS_BUS_DEVICE,
731 .instance_size = sizeof(OpenEthState),
732 .class_init = open_eth_class_init,
733};
734
735static void open_eth_register_types(void)
736{
737 type_register_static(&open_eth_info);
738}
739
740type_init(open_eth_register_types)
741
