1/* 2 * common defines for all CPUs 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19#ifndef CPU_DEFS_H 20#define CPU_DEFS_H 21 22#ifndef NEED_CPU_H 23#error cpu.h included from common code 24#endif 25 26#include "config.h" 27#include <setjmp.h> 28#include <inttypes.h> 29#include "qemu/osdep.h" 30#include "qemu/queue.h" 31#ifndef CONFIG_USER_ONLY 32#include "exec/hwaddr.h" 33#endif 34 35#ifndef TARGET_LONG_BITS 36#error TARGET_LONG_BITS must be defined before including this header 37#endif 38 39#define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8) 40 41/* target_ulong is the type of a virtual address */ 42#if TARGET_LONG_SIZE == 4 43typedef int32_t target_long; 44typedef uint32_t target_ulong; 45#define TARGET_FMT_lx "%08x" 46#define TARGET_FMT_ld "%d" 47#define TARGET_FMT_lu "%u" 48#elif TARGET_LONG_SIZE == 8 49typedef int64_t target_long; 50typedef uint64_t target_ulong; 51#define TARGET_FMT_lx "%016" PRIx64 52#define TARGET_FMT_ld "%" PRId64 53#define TARGET_FMT_lu "%" PRIu64 54#else 55#error TARGET_LONG_SIZE undefined 56#endif 57 58#define EXCP_INTERRUPT 0x10000 /* async interruption */ 59#define EXCP_HLT 0x10001 /* hlt instruction reached */ 60#define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */ 61#define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ 62 63#define TB_JMP_CACHE_BITS 12 64#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) 65 66/* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for 67 addresses on the same page. The top bits are the same. This allows 68 TLB invalidation to quickly clear a subset of the hash table. */ 69#define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2) 70#define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS) 71#define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1) 72#define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE) 73 74#if !defined(CONFIG_USER_ONLY) 75#define CPU_TLB_BITS 8 76#define CPU_TLB_SIZE (1 << CPU_TLB_BITS) 77 78#if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32 79#define CPU_TLB_ENTRY_BITS 4 80#else 81#define CPU_TLB_ENTRY_BITS 5 82#endif 83 84typedef struct CPUTLBEntry { 85 /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address 86 bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not 87 go directly to ram. 88 bit 3 : indicates that the entry is invalid 89 bit 2..0 : zero 90 */ 91 target_ulong addr_read; 92 target_ulong addr_write; 93 target_ulong addr_code; 94 /* Addend to virtual address to get host address. IO accesses 95 use the corresponding iotlb value. */ 96 uintptr_t addend; 97 /* padding to get a power of two size */ 98 uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) - 99 (sizeof(target_ulong) * 3 + 100 ((-sizeof(target_ulong) * 3) & (sizeof(uintptr_t) - 1)) + 101 sizeof(uintptr_t))]; 102} CPUTLBEntry; 103 104QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); 105 106#define CPU_COMMON_TLB \ 107 /* The meaning of the MMU modes is defined in the target code. */ \ 108 CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ 109 hwaddr iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ 110 target_ulong tlb_flush_addr; \ 111 target_ulong tlb_flush_mask; 112 113#else 114 115#define CPU_COMMON_TLB 116 117#endif 118 119 120#ifdef HOST_WORDS_BIGENDIAN 121typedef struct icount_decr_u16 { 122 uint16_t high; 123 uint16_t low; 124} icount_decr_u16; 125#else 126typedef struct icount_decr_u16 { 127 uint16_t low; 128 uint16_t high; 129} icount_decr_u16; 130#endif 131 132typedef struct CPUBreakpoint { 133 target_ulong pc; 134 int flags; /* BP_* */ 135 QTAILQ_ENTRY(CPUBreakpoint) entry; 136} CPUBreakpoint; 137 138typedef struct CPUWatchpoint { 139 target_ulong vaddr; 140 target_ulong len_mask; 141 int flags; /* BP_* */ 142 QTAILQ_ENTRY(CPUWatchpoint) entry; 143} CPUWatchpoint; 144 145#define CPU_TEMP_BUF_NLONGS 128 146#define CPU_COMMON \ 147 /* soft mmu support */ \ 148 /* in order to avoid passing too many arguments to the MMIO \ 149 helpers, we store some rarely used information in the CPU \ 150 context) */ \ 151 uintptr_t mem_io_pc; /* host pc at which the memory was \ 152 accessed */ \ 153 target_ulong mem_io_vaddr; /* target virtual addr at which the \ 154 memory was accessed */ \ 155 CPU_COMMON_TLB \ 156 struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \ 157 \ 158 int64_t icount_extra; /* Instructions until next timer event. */ \ 159 /* Number of cycles left, with interrupt flag in high bit. \ 160 This allows a single read-compare-cbranch-write sequence to test \ 161 for both decrementer underflow and exceptions. */ \ 162 union { \ 163 uint32_t u32; \ 164 icount_decr_u16 u16; \ 165 } icount_decr; \ 166 uint32_t can_do_io; /* nonzero if memory mapped IO is safe. */ \ 167 \ 168 /* from this point: preserved by CPU reset */ \ 169 /* ice debug support */ \ 170 QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \ 171 \ 172 QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \ 173 CPUWatchpoint *watchpoint_hit; \ 174 \ 175 /* Core interrupt code */ \ 176 sigjmp_buf jmp_env; \ 177 int exception_index; \ 178 \ 179 /* user data */ \ 180 void *opaque; \ 181 182#endif 183