1#include "hw/hw.h"
2#include "hw/boards.h"
3#include "sysemu/kvm.h"
4#include "helper_regs.h"
5
6static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
7{
8 PowerPCCPU *cpu = opaque;
9 CPUPPCState *env = &cpu->env;
10 unsigned int i, j;
11 target_ulong sdr1;
12 uint32_t fpscr;
13 target_ulong xer;
14
15 for (i = 0; i < 32; i++)
16 qemu_get_betls(f, &env->gpr[i]);
17#if !defined(TARGET_PPC64)
18 for (i = 0; i < 32; i++)
19 qemu_get_betls(f, &env->gprh[i]);
20#endif
21 qemu_get_betls(f, &env->lr);
22 qemu_get_betls(f, &env->ctr);
23 for (i = 0; i < 8; i++)
24 qemu_get_be32s(f, &env->crf[i]);
25 qemu_get_betls(f, &xer);
26 cpu_write_xer(env, xer);
27 qemu_get_betls(f, &env->reserve_addr);
28 qemu_get_betls(f, &env->msr);
29 for (i = 0; i < 4; i++)
30 qemu_get_betls(f, &env->tgpr[i]);
31 for (i = 0; i < 32; i++) {
32 union {
33 float64 d;
34 uint64_t l;
35 } u;
36 u.l = qemu_get_be64(f);
37 env->fpr[i] = u.d;
38 }
39 qemu_get_be32s(f, &fpscr);
40 env->fpscr = fpscr;
41 qemu_get_sbe32s(f, &env->access_type);
42#if defined(TARGET_PPC64)
43 qemu_get_betls(f, &env->spr[SPR_ASR]);
44 qemu_get_sbe32s(f, &env->slb_nr);
45#endif
46 qemu_get_betls(f, &sdr1);
47 for (i = 0; i < 32; i++)
48 qemu_get_betls(f, &env->sr[i]);
49 for (i = 0; i < 2; i++)
50 for (j = 0; j < 8; j++)
51 qemu_get_betls(f, &env->DBAT[i][j]);
52 for (i = 0; i < 2; i++)
53 for (j = 0; j < 8; j++)
54 qemu_get_betls(f, &env->IBAT[i][j]);
55 qemu_get_sbe32s(f, &env->nb_tlb);
56 qemu_get_sbe32s(f, &env->tlb_per_way);
57 qemu_get_sbe32s(f, &env->nb_ways);
58 qemu_get_sbe32s(f, &env->last_way);
59 qemu_get_sbe32s(f, &env->id_tlbs);
60 qemu_get_sbe32s(f, &env->nb_pids);
61 if (env->tlb.tlb6) {
62
63 for (i = 0; i < env->nb_tlb; i++) {
64 qemu_get_betls(f, &env->tlb.tlb6[i].pte0);
65 qemu_get_betls(f, &env->tlb.tlb6[i].pte1);
66 qemu_get_betls(f, &env->tlb.tlb6[i].EPN);
67 }
68 }
69 for (i = 0; i < 4; i++)
70 qemu_get_betls(f, &env->pb[i]);
71 for (i = 0; i < 1024; i++)
72 qemu_get_betls(f, &env->spr[i]);
73 if (!env->external_htab) {
74 ppc_store_sdr1(env, sdr1);
75 }
76 qemu_get_be32s(f, &env->vscr);
77 qemu_get_be64s(f, &env->spe_acc);
78 qemu_get_be32s(f, &env->spe_fscr);
79 qemu_get_betls(f, &env->msr_mask);
80 qemu_get_be32s(f, &env->flags);
81 qemu_get_sbe32s(f, &env->error_code);
82 qemu_get_be32s(f, &env->pending_interrupts);
83 qemu_get_be32s(f, &env->irq_input_state);
84 for (i = 0; i < POWERPC_EXCP_NB; i++)
85 qemu_get_betls(f, &env->excp_vectors[i]);
86 qemu_get_betls(f, &env->excp_prefix);
87 qemu_get_betls(f, &env->ivor_mask);
88 qemu_get_betls(f, &env->ivpr_mask);
89 qemu_get_betls(f, &env->hreset_vector);
90 qemu_get_betls(f, &env->nip);
91 qemu_get_betls(f, &env->hflags);
92 qemu_get_betls(f, &env->hflags_nmsr);
93 qemu_get_sbe32s(f, &env->mmu_idx);
94 qemu_get_sbe32(f);
95
96 return 0;
97}
98
99static int get_avr(QEMUFile *f, void *pv, size_t size)
100{
101 ppc_avr_t *v = pv;
102
103 v->u64[0] = qemu_get_be64(f);
104 v->u64[1] = qemu_get_be64(f);
105
106 return 0;
107}
108
109static void put_avr(QEMUFile *f, void *pv, size_t size)
110{
111 ppc_avr_t *v = pv;
112
113 qemu_put_be64(f, v->u64[0]);
114 qemu_put_be64(f, v->u64[1]);
115}
116
117static const VMStateInfo vmstate_info_avr = {
118 .name = "avr",
119 .get = get_avr,
120 .put = put_avr,
121};
122
123#define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v) \
124 VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t)
125
126#define VMSTATE_AVR_ARRAY(_f, _s, _n) \
127 VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0)
128
129static void cpu_pre_save(void *opaque)
130{
131 PowerPCCPU *cpu = opaque;
132 CPUPPCState *env = &cpu->env;
133 int i;
134
135 env->spr[SPR_LR] = env->lr;
136 env->spr[SPR_CTR] = env->ctr;
137 env->spr[SPR_XER] = env->xer;
138#if defined(TARGET_PPC64)
139 env->spr[SPR_CFAR] = env->cfar;
140#endif
141 env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr;
142
143 for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
144 env->spr[SPR_DBAT0U + 2*i] = env->DBAT[0][i];
145 env->spr[SPR_DBAT0U + 2*i + 1] = env->DBAT[1][i];
146 env->spr[SPR_IBAT0U + 2*i] = env->IBAT[0][i];
147 env->spr[SPR_IBAT0U + 2*i + 1] = env->IBAT[1][i];
148 }
149 for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
150 env->spr[SPR_DBAT4U + 2*i] = env->DBAT[0][i+4];
151 env->spr[SPR_DBAT4U + 2*i + 1] = env->DBAT[1][i+4];
152 env->spr[SPR_IBAT4U + 2*i] = env->IBAT[0][i+4];
153 env->spr[SPR_IBAT4U + 2*i + 1] = env->IBAT[1][i+4];
154 }
155}
156
157static int cpu_post_load(void *opaque, int version_id)
158{
159 PowerPCCPU *cpu = opaque;
160 CPUPPCState *env = &cpu->env;
161 int i;
162
163
164
165
166
167 env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value;
168 env->lr = env->spr[SPR_LR];
169 env->ctr = env->spr[SPR_CTR];
170 env->xer = env->spr[SPR_XER];
171#if defined(TARGET_PPC64)
172 env->cfar = env->spr[SPR_CFAR];
173#endif
174 env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR];
175
176 for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
177 env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2*i];
178 env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2*i + 1];
179 env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2*i];
180 env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2*i + 1];
181 }
182 for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
183 env->DBAT[0][i+4] = env->spr[SPR_DBAT4U + 2*i];
184 env->DBAT[1][i+4] = env->spr[SPR_DBAT4U + 2*i + 1];
185 env->IBAT[0][i+4] = env->spr[SPR_IBAT4U + 2*i];
186 env->IBAT[1][i+4] = env->spr[SPR_IBAT4U + 2*i + 1];
187 }
188
189 if (!env->external_htab) {
190
191 ppc_store_sdr1(env, env->spr[SPR_SDR1]);
192 }
193 hreg_compute_hflags(env);
194 hreg_compute_mem_idx(env);
195
196 return 0;
197}
198
199static bool fpu_needed(void *opaque)
200{
201 PowerPCCPU *cpu = opaque;
202
203 return (cpu->env.insns_flags & PPC_FLOAT);
204}
205
206static const VMStateDescription vmstate_fpu = {
207 .name = "cpu/fpu",
208 .version_id = 1,
209 .minimum_version_id = 1,
210 .fields = (VMStateField[]) {
211 VMSTATE_FLOAT64_ARRAY(env.fpr, PowerPCCPU, 32),
212 VMSTATE_UINTTL(env.fpscr, PowerPCCPU),
213 VMSTATE_END_OF_LIST()
214 },
215};
216
217static bool altivec_needed(void *opaque)
218{
219 PowerPCCPU *cpu = opaque;
220
221 return (cpu->env.insns_flags & PPC_ALTIVEC);
222}
223
224static const VMStateDescription vmstate_altivec = {
225 .name = "cpu/altivec",
226 .version_id = 1,
227 .minimum_version_id = 1,
228 .fields = (VMStateField[]) {
229 VMSTATE_AVR_ARRAY(env.avr, PowerPCCPU, 32),
230 VMSTATE_UINT32(env.vscr, PowerPCCPU),
231 VMSTATE_END_OF_LIST()
232 },
233};
234
235static bool vsx_needed(void *opaque)
236{
237 PowerPCCPU *cpu = opaque;
238
239 return (cpu->env.insns_flags2 & PPC2_VSX);
240}
241
242static const VMStateDescription vmstate_vsx = {
243 .name = "cpu/vsx",
244 .version_id = 1,
245 .minimum_version_id = 1,
246 .fields = (VMStateField[]) {
247 VMSTATE_UINT64_ARRAY(env.vsr, PowerPCCPU, 32),
248 VMSTATE_END_OF_LIST()
249 },
250};
251
252#ifdef TARGET_PPC64
253
254static bool tm_needed(void *opaque)
255{
256 PowerPCCPU *cpu = opaque;
257 CPUPPCState *env = &cpu->env;
258 return msr_ts;
259}
260
261static const VMStateDescription vmstate_tm = {
262 .name = "cpu/tm",
263 .version_id = 1,
264 .minimum_version_id = 1,
265 .minimum_version_id_old = 1,
266 .fields = (VMStateField []) {
267 VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32),
268 VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64),
269 VMSTATE_UINT64(env.tm_cr, PowerPCCPU),
270 VMSTATE_UINT64(env.tm_lr, PowerPCCPU),
271 VMSTATE_UINT64(env.tm_ctr, PowerPCCPU),
272 VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU),
273 VMSTATE_UINT64(env.tm_amr, PowerPCCPU),
274 VMSTATE_UINT64(env.tm_ppr, PowerPCCPU),
275 VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU),
276 VMSTATE_UINT32(env.tm_vscr, PowerPCCPU),
277 VMSTATE_UINT64(env.tm_dscr, PowerPCCPU),
278 VMSTATE_UINT64(env.tm_tar, PowerPCCPU),
279 VMSTATE_END_OF_LIST()
280 },
281};
282#endif
283
284static bool sr_needed(void *opaque)
285{
286#ifdef TARGET_PPC64
287 PowerPCCPU *cpu = opaque;
288
289 return !(cpu->env.mmu_model & POWERPC_MMU_64);
290#else
291 return true;
292#endif
293}
294
295static const VMStateDescription vmstate_sr = {
296 .name = "cpu/sr",
297 .version_id = 1,
298 .minimum_version_id = 1,
299 .fields = (VMStateField[]) {
300 VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32),
301 VMSTATE_END_OF_LIST()
302 },
303};
304
305#ifdef TARGET_PPC64
306static int get_slbe(QEMUFile *f, void *pv, size_t size)
307{
308 ppc_slb_t *v = pv;
309
310 v->esid = qemu_get_be64(f);
311 v->vsid = qemu_get_be64(f);
312
313 return 0;
314}
315
316static void put_slbe(QEMUFile *f, void *pv, size_t size)
317{
318 ppc_slb_t *v = pv;
319
320 qemu_put_be64(f, v->esid);
321 qemu_put_be64(f, v->vsid);
322}
323
324static const VMStateInfo vmstate_info_slbe = {
325 .name = "slbe",
326 .get = get_slbe,
327 .put = put_slbe,
328};
329
330#define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v) \
331 VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t)
332
333#define VMSTATE_SLB_ARRAY(_f, _s, _n) \
334 VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0)
335
336static bool slb_needed(void *opaque)
337{
338 PowerPCCPU *cpu = opaque;
339
340
341 return (cpu->env.mmu_model & POWERPC_MMU_64);
342}
343
344static const VMStateDescription vmstate_slb = {
345 .name = "cpu/slb",
346 .version_id = 1,
347 .minimum_version_id = 1,
348 .fields = (VMStateField[]) {
349 VMSTATE_INT32_EQUAL(env.slb_nr, PowerPCCPU),
350 VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES),
351 VMSTATE_END_OF_LIST()
352 }
353};
354#endif
355
356static const VMStateDescription vmstate_tlb6xx_entry = {
357 .name = "cpu/tlb6xx_entry",
358 .version_id = 1,
359 .minimum_version_id = 1,
360 .fields = (VMStateField[]) {
361 VMSTATE_UINTTL(pte0, ppc6xx_tlb_t),
362 VMSTATE_UINTTL(pte1, ppc6xx_tlb_t),
363 VMSTATE_UINTTL(EPN, ppc6xx_tlb_t),
364 VMSTATE_END_OF_LIST()
365 },
366};
367
368static bool tlb6xx_needed(void *opaque)
369{
370 PowerPCCPU *cpu = opaque;
371 CPUPPCState *env = &cpu->env;
372
373 return env->nb_tlb && (env->tlb_type == TLB_6XX);
374}
375
376static const VMStateDescription vmstate_tlb6xx = {
377 .name = "cpu/tlb6xx",
378 .version_id = 1,
379 .minimum_version_id = 1,
380 .fields = (VMStateField[]) {
381 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
382 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU,
383 env.nb_tlb,
384 vmstate_tlb6xx_entry,
385 ppc6xx_tlb_t),
386 VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4),
387 VMSTATE_END_OF_LIST()
388 }
389};
390
391static const VMStateDescription vmstate_tlbemb_entry = {
392 .name = "cpu/tlbemb_entry",
393 .version_id = 1,
394 .minimum_version_id = 1,
395 .fields = (VMStateField[]) {
396 VMSTATE_UINT64(RPN, ppcemb_tlb_t),
397 VMSTATE_UINTTL(EPN, ppcemb_tlb_t),
398 VMSTATE_UINTTL(PID, ppcemb_tlb_t),
399 VMSTATE_UINTTL(size, ppcemb_tlb_t),
400 VMSTATE_UINT32(prot, ppcemb_tlb_t),
401 VMSTATE_UINT32(attr, ppcemb_tlb_t),
402 VMSTATE_END_OF_LIST()
403 },
404};
405
406static bool tlbemb_needed(void *opaque)
407{
408 PowerPCCPU *cpu = opaque;
409 CPUPPCState *env = &cpu->env;
410
411 return env->nb_tlb && (env->tlb_type == TLB_EMB);
412}
413
414static bool pbr403_needed(void *opaque)
415{
416 PowerPCCPU *cpu = opaque;
417 uint32_t pvr = cpu->env.spr[SPR_PVR];
418
419 return (pvr & 0xffff0000) == 0x00200000;
420}
421
422static const VMStateDescription vmstate_pbr403 = {
423 .name = "cpu/pbr403",
424 .version_id = 1,
425 .minimum_version_id = 1,
426 .fields = (VMStateField[]) {
427 VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4),
428 VMSTATE_END_OF_LIST()
429 },
430};
431
432static const VMStateDescription vmstate_tlbemb = {
433 .name = "cpu/tlb6xx",
434 .version_id = 1,
435 .minimum_version_id = 1,
436 .fields = (VMStateField[]) {
437 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
438 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU,
439 env.nb_tlb,
440 vmstate_tlbemb_entry,
441 ppcemb_tlb_t),
442
443 VMSTATE_END_OF_LIST()
444 },
445 .subsections = (VMStateSubsection []) {
446 {
447 .vmsd = &vmstate_pbr403,
448 .needed = pbr403_needed,
449 } , {
450
451 }
452 }
453};
454
455static const VMStateDescription vmstate_tlbmas_entry = {
456 .name = "cpu/tlbmas_entry",
457 .version_id = 1,
458 .minimum_version_id = 1,
459 .fields = (VMStateField[]) {
460 VMSTATE_UINT32(mas8, ppcmas_tlb_t),
461 VMSTATE_UINT32(mas1, ppcmas_tlb_t),
462 VMSTATE_UINT64(mas2, ppcmas_tlb_t),
463 VMSTATE_UINT64(mas7_3, ppcmas_tlb_t),
464 VMSTATE_END_OF_LIST()
465 },
466};
467
468static bool tlbmas_needed(void *opaque)
469{
470 PowerPCCPU *cpu = opaque;
471 CPUPPCState *env = &cpu->env;
472
473 return env->nb_tlb && (env->tlb_type == TLB_MAS);
474}
475
476static const VMStateDescription vmstate_tlbmas = {
477 .name = "cpu/tlbmas",
478 .version_id = 1,
479 .minimum_version_id = 1,
480 .fields = (VMStateField[]) {
481 VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
482 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU,
483 env.nb_tlb,
484 vmstate_tlbmas_entry,
485 ppcmas_tlb_t),
486 VMSTATE_END_OF_LIST()
487 }
488};
489
490const VMStateDescription vmstate_ppc_cpu = {
491 .name = "cpu",
492 .version_id = 5,
493 .minimum_version_id = 5,
494 .minimum_version_id_old = 4,
495 .load_state_old = cpu_load_old,
496 .pre_save = cpu_pre_save,
497 .post_load = cpu_post_load,
498 .fields = (VMStateField[]) {
499 VMSTATE_UNUSED(sizeof(target_ulong)),
500
501
502 VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32),
503#if !defined(TARGET_PPC64)
504 VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32),
505#endif
506 VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8),
507 VMSTATE_UINTTL(env.nip, PowerPCCPU),
508
509
510 VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024),
511 VMSTATE_UINT64(env.spe_acc, PowerPCCPU),
512
513
514 VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU),
515
516
517 VMSTATE_UINTTL(env.msr, PowerPCCPU),
518
519
520 VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU),
521
522
523
524 VMSTATE_UINTTL_EQUAL(env.msr_mask, PowerPCCPU),
525 VMSTATE_UINT64_EQUAL(env.insns_flags, PowerPCCPU),
526 VMSTATE_UINT64_EQUAL(env.insns_flags2, PowerPCCPU),
527 VMSTATE_UINT32_EQUAL(env.nb_BATs, PowerPCCPU),
528 VMSTATE_END_OF_LIST()
529 },
530 .subsections = (VMStateSubsection []) {
531 {
532 .vmsd = &vmstate_fpu,
533 .needed = fpu_needed,
534 } , {
535 .vmsd = &vmstate_altivec,
536 .needed = altivec_needed,
537 } , {
538 .vmsd = &vmstate_vsx,
539 .needed = vsx_needed,
540 } , {
541 .vmsd = &vmstate_sr,
542 .needed = sr_needed,
543 } , {
544#ifdef TARGET_PPC64
545 .vmsd = &vmstate_tm,
546 .needed = tm_needed,
547 } , {
548 .vmsd = &vmstate_slb,
549 .needed = slb_needed,
550 } , {
551#endif
552 .vmsd = &vmstate_tlb6xx,
553 .needed = tlb6xx_needed,
554 } , {
555 .vmsd = &vmstate_tlbemb,
556 .needed = tlbemb_needed,
557 } , {
558 .vmsd = &vmstate_tlbmas,
559 .needed = tlbmas_needed,
560 } , {
561
562 }
563 }
564};
565
