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10#include "qemu/osdep.h"
11#include "qapi/error.h"
12#include "qemu-common.h"
13#include "cpu.h"
14#include "hw/sysbus.h"
15#include "hw/devices.h"
16#include "hw/boards.h"
17#include "hw/arm/arm.h"
18#include "hw/misc/arm_integrator_debug.h"
19#include "net/net.h"
20#include "exec/address-spaces.h"
21#include "sysemu/sysemu.h"
22#include "qemu/error-report.h"
23#include "hw/char/pl011.h"
24
25#define TYPE_INTEGRATOR_CM "integrator_core"
26#define INTEGRATOR_CM(obj) \
27 OBJECT_CHECK(IntegratorCMState, (obj), TYPE_INTEGRATOR_CM)
28
29typedef struct IntegratorCMState {
30
31 SysBusDevice parent_obj;
32
33
34 MemoryRegion iomem;
35 uint32_t memsz;
36 MemoryRegion flash;
37 uint32_t cm_osc;
38 uint32_t cm_ctrl;
39 uint32_t cm_lock;
40 uint32_t cm_auxosc;
41 uint32_t cm_sdram;
42 uint32_t cm_init;
43 uint32_t cm_flags;
44 uint32_t cm_nvflags;
45 uint32_t cm_refcnt_offset;
46 uint32_t int_level;
47 uint32_t irq_enabled;
48 uint32_t fiq_enabled;
49} IntegratorCMState;
50
51static uint8_t integrator_spd[128] = {
52 128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1,
53 0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
54};
55
56static const VMStateDescription vmstate_integratorcm = {
57 .name = "integratorcm",
58 .version_id = 1,
59 .minimum_version_id = 1,
60 .fields = (VMStateField[]) {
61 VMSTATE_UINT32(cm_osc, IntegratorCMState),
62 VMSTATE_UINT32(cm_ctrl, IntegratorCMState),
63 VMSTATE_UINT32(cm_lock, IntegratorCMState),
64 VMSTATE_UINT32(cm_auxosc, IntegratorCMState),
65 VMSTATE_UINT32(cm_sdram, IntegratorCMState),
66 VMSTATE_UINT32(cm_init, IntegratorCMState),
67 VMSTATE_UINT32(cm_flags, IntegratorCMState),
68 VMSTATE_UINT32(cm_nvflags, IntegratorCMState),
69 VMSTATE_UINT32(int_level, IntegratorCMState),
70 VMSTATE_UINT32(irq_enabled, IntegratorCMState),
71 VMSTATE_UINT32(fiq_enabled, IntegratorCMState),
72 VMSTATE_END_OF_LIST()
73 }
74};
75
76static uint64_t integratorcm_read(void *opaque, hwaddr offset,
77 unsigned size)
78{
79 IntegratorCMState *s = opaque;
80 if (offset >= 0x100 && offset < 0x200) {
81
82 if (offset >= 0x180)
83 return 0;
84 return integrator_spd[offset >> 2];
85 }
86 switch (offset >> 2) {
87 case 0:
88 return 0x411a3001;
89 case 1:
90 return 0;
91 case 2:
92 return s->cm_osc;
93 case 3:
94 return s->cm_ctrl;
95 case 4:
96 return 0x00100000;
97 case 5:
98 if (s->cm_lock == 0xa05f) {
99 return 0x1a05f;
100 } else {
101 return s->cm_lock;
102 }
103 case 6:
104
105 hw_error("integratorcm_read: CM_LMBUSCNT");
106 case 7:
107 return s->cm_auxosc;
108 case 8:
109 return s->cm_sdram;
110 case 9:
111 return s->cm_init;
112 case 10:
113
114
115
116
117 return (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24,
118 1000) - s->cm_refcnt_offset;
119 case 12:
120 return s->cm_flags;
121 case 14:
122 return s->cm_nvflags;
123 case 16:
124 return s->int_level & s->irq_enabled;
125 case 17:
126 return s->int_level;
127 case 18:
128 return s->irq_enabled;
129 case 20:
130 return s->int_level & 1;
131 case 24:
132 return s->int_level & s->fiq_enabled;
133 case 25:
134 return s->int_level;
135 case 26:
136 return s->fiq_enabled;
137 case 32:
138 case 33:
139 case 34:
140 case 35:
141
142 return 0;
143 default:
144 hw_error("integratorcm_read: Unimplemented offset 0x%x\n",
145 (int)offset);
146 return 0;
147 }
148}
149
150static void integratorcm_do_remap(IntegratorCMState *s)
151{
152
153
154
155 memory_region_set_enabled(&s->flash, !(s->cm_ctrl & 4));
156}
157
158static void integratorcm_set_ctrl(IntegratorCMState *s, uint32_t value)
159{
160 if (value & 8) {
161 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
162 }
163 if ((s->cm_ctrl ^ value) & 1) {
164
165
166
167
168
169 }
170
171 s->cm_ctrl = (s->cm_ctrl & ~5) | (value & 5);
172 integratorcm_do_remap(s);
173}
174
175static void integratorcm_update(IntegratorCMState *s)
176{
177
178
179 if (s->int_level & (s->irq_enabled | s->fiq_enabled))
180 hw_error("Core module interrupt\n");
181}
182
183static void integratorcm_write(void *opaque, hwaddr offset,
184 uint64_t value, unsigned size)
185{
186 IntegratorCMState *s = opaque;
187 switch (offset >> 2) {
188 case 2:
189 if (s->cm_lock == 0xa05f)
190 s->cm_osc = value;
191 break;
192 case 3:
193 integratorcm_set_ctrl(s, value);
194 break;
195 case 5:
196 s->cm_lock = value & 0xffff;
197 break;
198 case 7:
199 if (s->cm_lock == 0xa05f)
200 s->cm_auxosc = value;
201 break;
202 case 8:
203 s->cm_sdram = value;
204 break;
205 case 9:
206
207 s->cm_init = value;
208 break;
209 case 12:
210 s->cm_flags |= value;
211 break;
212 case 13:
213 s->cm_flags &= ~value;
214 break;
215 case 14:
216 s->cm_nvflags |= value;
217 break;
218 case 15:
219 s->cm_nvflags &= ~value;
220 break;
221 case 18:
222 s->irq_enabled |= value;
223 integratorcm_update(s);
224 break;
225 case 19:
226 s->irq_enabled &= ~value;
227 integratorcm_update(s);
228 break;
229 case 20:
230 s->int_level |= (value & 1);
231 integratorcm_update(s);
232 break;
233 case 21:
234 s->int_level &= ~(value & 1);
235 integratorcm_update(s);
236 break;
237 case 26:
238 s->fiq_enabled |= value;
239 integratorcm_update(s);
240 break;
241 case 27:
242 s->fiq_enabled &= ~value;
243 integratorcm_update(s);
244 break;
245 case 32:
246 case 33:
247 case 34:
248 case 35:
249
250 break;
251 default:
252 hw_error("integratorcm_write: Unimplemented offset 0x%x\n",
253 (int)offset);
254 break;
255 }
256}
257
258
259
260static const MemoryRegionOps integratorcm_ops = {
261 .read = integratorcm_read,
262 .write = integratorcm_write,
263 .endianness = DEVICE_NATIVE_ENDIAN,
264};
265
266static void integratorcm_init(Object *obj)
267{
268 IntegratorCMState *s = INTEGRATOR_CM(obj);
269 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
270
271 s->cm_osc = 0x01000048;
272
273 s->cm_auxosc = 0x0007feff;
274 s->cm_sdram = 0x00011122;
275 memcpy(integrator_spd + 73, "QEMU-MEMORY", 11);
276 s->cm_init = 0x00000112;
277 s->cm_refcnt_offset = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24,
278 1000);
279 memory_region_init_ram(&s->flash, obj, "integrator.flash", 0x100000,
280 &error_fatal);
281
282 memory_region_init_io(&s->iomem, obj, &integratorcm_ops, s,
283 "integratorcm", 0x00800000);
284 sysbus_init_mmio(dev, &s->iomem);
285
286 integratorcm_do_remap(s);
287
288}
289
290static void integratorcm_realize(DeviceState *d, Error **errp)
291{
292 IntegratorCMState *s = INTEGRATOR_CM(d);
293
294 if (s->memsz >= 256) {
295 integrator_spd[31] = 64;
296 s->cm_sdram |= 0x10;
297 } else if (s->memsz >= 128) {
298 integrator_spd[31] = 32;
299 s->cm_sdram |= 0x0c;
300 } else if (s->memsz >= 64) {
301 integrator_spd[31] = 16;
302 s->cm_sdram |= 0x08;
303 } else if (s->memsz >= 32) {
304 integrator_spd[31] = 4;
305 s->cm_sdram |= 0x04;
306 } else {
307 integrator_spd[31] = 2;
308 }
309}
310
311
312
313
314#define TYPE_INTEGRATOR_PIC "integrator_pic"
315#define INTEGRATOR_PIC(obj) \
316 OBJECT_CHECK(icp_pic_state, (obj), TYPE_INTEGRATOR_PIC)
317
318typedef struct icp_pic_state {
319
320 SysBusDevice parent_obj;
321
322
323 MemoryRegion iomem;
324 uint32_t level;
325 uint32_t irq_enabled;
326 uint32_t fiq_enabled;
327 qemu_irq parent_irq;
328 qemu_irq parent_fiq;
329} icp_pic_state;
330
331static const VMStateDescription vmstate_icp_pic = {
332 .name = "icp_pic",
333 .version_id = 1,
334 .minimum_version_id = 1,
335 .fields = (VMStateField[]) {
336 VMSTATE_UINT32(level, icp_pic_state),
337 VMSTATE_UINT32(irq_enabled, icp_pic_state),
338 VMSTATE_UINT32(fiq_enabled, icp_pic_state),
339 VMSTATE_END_OF_LIST()
340 }
341};
342
343static void icp_pic_update(icp_pic_state *s)
344{
345 uint32_t flags;
346
347 flags = (s->level & s->irq_enabled);
348 qemu_set_irq(s->parent_irq, flags != 0);
349 flags = (s->level & s->fiq_enabled);
350 qemu_set_irq(s->parent_fiq, flags != 0);
351}
352
353static void icp_pic_set_irq(void *opaque, int irq, int level)
354{
355 icp_pic_state *s = (icp_pic_state *)opaque;
356 if (level)
357 s->level |= 1 << irq;
358 else
359 s->level &= ~(1 << irq);
360 icp_pic_update(s);
361}
362
363static uint64_t icp_pic_read(void *opaque, hwaddr offset,
364 unsigned size)
365{
366 icp_pic_state *s = (icp_pic_state *)opaque;
367
368 switch (offset >> 2) {
369 case 0:
370 return s->level & s->irq_enabled;
371 case 1:
372 return s->level;
373 case 2:
374 return s->irq_enabled;
375 case 4:
376 return s->level & 1;
377 case 8:
378 return s->level & s->fiq_enabled;
379 case 9:
380 return s->level;
381 case 10:
382 return s->fiq_enabled;
383 case 3:
384 case 5:
385 case 11:
386 default:
387 printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset);
388 return 0;
389 }
390}
391
392static void icp_pic_write(void *opaque, hwaddr offset,
393 uint64_t value, unsigned size)
394{
395 icp_pic_state *s = (icp_pic_state *)opaque;
396
397 switch (offset >> 2) {
398 case 2:
399 s->irq_enabled |= value;
400 break;
401 case 3:
402 s->irq_enabled &= ~value;
403 break;
404 case 4:
405 if (value & 1)
406 icp_pic_set_irq(s, 0, 1);
407 break;
408 case 5:
409 if (value & 1)
410 icp_pic_set_irq(s, 0, 0);
411 break;
412 case 10:
413 s->fiq_enabled |= value;
414 break;
415 case 11:
416 s->fiq_enabled &= ~value;
417 break;
418 case 0:
419 case 1:
420 case 8:
421 case 9:
422 default:
423 printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset);
424 return;
425 }
426 icp_pic_update(s);
427}
428
429static const MemoryRegionOps icp_pic_ops = {
430 .read = icp_pic_read,
431 .write = icp_pic_write,
432 .endianness = DEVICE_NATIVE_ENDIAN,
433};
434
435static void icp_pic_init(Object *obj)
436{
437 DeviceState *dev = DEVICE(obj);
438 icp_pic_state *s = INTEGRATOR_PIC(obj);
439 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
440
441 qdev_init_gpio_in(dev, icp_pic_set_irq, 32);
442 sysbus_init_irq(sbd, &s->parent_irq);
443 sysbus_init_irq(sbd, &s->parent_fiq);
444 memory_region_init_io(&s->iomem, obj, &icp_pic_ops, s,
445 "icp-pic", 0x00800000);
446 sysbus_init_mmio(sbd, &s->iomem);
447}
448
449
450
451#define TYPE_ICP_CONTROL_REGS "icp-ctrl-regs"
452#define ICP_CONTROL_REGS(obj) \
453 OBJECT_CHECK(ICPCtrlRegsState, (obj), TYPE_ICP_CONTROL_REGS)
454
455typedef struct ICPCtrlRegsState {
456
457 SysBusDevice parent_obj;
458
459
460 MemoryRegion iomem;
461
462 qemu_irq mmc_irq;
463 uint32_t intreg_state;
464} ICPCtrlRegsState;
465
466#define ICP_GPIO_MMC_WPROT "mmc-wprot"
467#define ICP_GPIO_MMC_CARDIN "mmc-cardin"
468
469#define ICP_INTREG_WPROT (1 << 0)
470#define ICP_INTREG_CARDIN (1 << 3)
471
472static const VMStateDescription vmstate_icp_control = {
473 .name = "icp_control",
474 .version_id = 1,
475 .minimum_version_id = 1,
476 .fields = (VMStateField[]) {
477 VMSTATE_UINT32(intreg_state, ICPCtrlRegsState),
478 VMSTATE_END_OF_LIST()
479 }
480};
481
482static uint64_t icp_control_read(void *opaque, hwaddr offset,
483 unsigned size)
484{
485 ICPCtrlRegsState *s = opaque;
486
487 switch (offset >> 2) {
488 case 0:
489 return 0x41034003;
490 case 1:
491 return 0;
492 case 2:
493 return s->intreg_state;
494 case 3:
495 return 0x11;
496 default:
497 hw_error("icp_control_read: Bad offset %x\n", (int)offset);
498 return 0;
499 }
500}
501
502static void icp_control_write(void *opaque, hwaddr offset,
503 uint64_t value, unsigned size)
504{
505 ICPCtrlRegsState *s = opaque;
506
507 switch (offset >> 2) {
508 case 2:
509 s->intreg_state &= ~(value & ICP_INTREG_CARDIN);
510 qemu_set_irq(s->mmc_irq, !!(s->intreg_state & ICP_INTREG_CARDIN));
511 break;
512 case 1:
513 case 3:
514
515 break;
516 default:
517 hw_error("icp_control_write: Bad offset %x\n", (int)offset);
518 }
519}
520
521static const MemoryRegionOps icp_control_ops = {
522 .read = icp_control_read,
523 .write = icp_control_write,
524 .endianness = DEVICE_NATIVE_ENDIAN,
525};
526
527static void icp_control_mmc_wprot(void *opaque, int line, int level)
528{
529 ICPCtrlRegsState *s = opaque;
530
531 s->intreg_state &= ~ICP_INTREG_WPROT;
532 if (level) {
533 s->intreg_state |= ICP_INTREG_WPROT;
534 }
535}
536
537static void icp_control_mmc_cardin(void *opaque, int line, int level)
538{
539 ICPCtrlRegsState *s = opaque;
540
541
542 if (level) {
543 s->intreg_state |= ICP_INTREG_CARDIN;
544 qemu_set_irq(s->mmc_irq, 1);
545 }
546}
547
548static void icp_control_init(Object *obj)
549{
550 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
551 ICPCtrlRegsState *s = ICP_CONTROL_REGS(obj);
552 DeviceState *dev = DEVICE(obj);
553
554 memory_region_init_io(&s->iomem, OBJECT(s), &icp_control_ops, s,
555 "icp_ctrl_regs", 0x00800000);
556 sysbus_init_mmio(sbd, &s->iomem);
557
558 qdev_init_gpio_in_named(dev, icp_control_mmc_wprot, ICP_GPIO_MMC_WPROT, 1);
559 qdev_init_gpio_in_named(dev, icp_control_mmc_cardin,
560 ICP_GPIO_MMC_CARDIN, 1);
561 sysbus_init_irq(sbd, &s->mmc_irq);
562}
563
564
565
566
567static struct arm_boot_info integrator_binfo = {
568 .loader_start = 0x0,
569 .board_id = 0x113,
570};
571
572static void integratorcp_init(MachineState *machine)
573{
574 ram_addr_t ram_size = machine->ram_size;
575 const char *cpu_model = machine->cpu_model;
576 const char *kernel_filename = machine->kernel_filename;
577 const char *kernel_cmdline = machine->kernel_cmdline;
578 const char *initrd_filename = machine->initrd_filename;
579 char **cpustr;
580 ObjectClass *cpu_oc;
581 CPUClass *cc;
582 Object *cpuobj;
583 ARMCPU *cpu;
584 const char *typename;
585 MemoryRegion *address_space_mem = get_system_memory();
586 MemoryRegion *ram = g_new(MemoryRegion, 1);
587 MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
588 qemu_irq pic[32];
589 DeviceState *dev, *sic, *icp;
590 int i;
591 Error *err = NULL;
592
593 if (!cpu_model) {
594 cpu_model = "arm926";
595 }
596
597 cpustr = g_strsplit(cpu_model, ",", 2);
598
599 cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);
600 if (!cpu_oc) {
601 fprintf(stderr, "Unable to find CPU definition\n");
602 exit(1);
603 }
604 typename = object_class_get_name(cpu_oc);
605
606 cc = CPU_CLASS(cpu_oc);
607 cc->parse_features(typename, cpustr[1], &err);
608 g_strfreev(cpustr);
609 if (err) {
610 error_report_err(err);
611 exit(1);
612 }
613
614 cpuobj = object_new(typename);
615
616
617
618
619
620 if (object_property_find(cpuobj, "has_el3", NULL)) {
621 object_property_set_bool(cpuobj, false, "has_el3", &error_fatal);
622 }
623
624 object_property_set_bool(cpuobj, true, "realized", &error_fatal);
625
626 cpu = ARM_CPU(cpuobj);
627
628 memory_region_allocate_system_memory(ram, NULL, "integrator.ram",
629 ram_size);
630
631
632
633 memory_region_add_subregion(address_space_mem, 0, ram);
634
635 memory_region_init_alias(ram_alias, NULL, "ram.alias", ram, 0, ram_size);
636 memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias);
637
638 dev = qdev_create(NULL, TYPE_INTEGRATOR_CM);
639 qdev_prop_set_uint32(dev, "memsz", ram_size >> 20);
640 qdev_init_nofail(dev);
641 sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000);
642
643 dev = sysbus_create_varargs(TYPE_INTEGRATOR_PIC, 0x14000000,
644 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ),
645 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ),
646 NULL);
647 for (i = 0; i < 32; i++) {
648 pic[i] = qdev_get_gpio_in(dev, i);
649 }
650 sic = sysbus_create_simple(TYPE_INTEGRATOR_PIC, 0xca000000, pic[26]);
651 sysbus_create_varargs("integrator_pit", 0x13000000,
652 pic[5], pic[6], pic[7], NULL);
653 sysbus_create_simple("pl031", 0x15000000, pic[8]);
654 pl011_create(0x16000000, pic[1], serial_hds[0]);
655 pl011_create(0x17000000, pic[2], serial_hds[1]);
656 icp = sysbus_create_simple(TYPE_ICP_CONTROL_REGS, 0xcb000000,
657 qdev_get_gpio_in(sic, 3));
658 sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]);
659 sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]);
660 sysbus_create_simple(TYPE_INTEGRATOR_DEBUG, 0x1a000000, 0);
661
662 dev = sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL);
663 qdev_connect_gpio_out(dev, 0,
664 qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_WPROT, 0));
665 qdev_connect_gpio_out(dev, 1,
666 qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN, 0));
667
668 if (nd_table[0].used)
669 smc91c111_init(&nd_table[0], 0xc8000000, pic[27]);
670
671 sysbus_create_simple("pl110", 0xc0000000, pic[22]);
672
673 integrator_binfo.ram_size = ram_size;
674 integrator_binfo.kernel_filename = kernel_filename;
675 integrator_binfo.kernel_cmdline = kernel_cmdline;
676 integrator_binfo.initrd_filename = initrd_filename;
677 arm_load_kernel(cpu, &integrator_binfo);
678}
679
680static void integratorcp_machine_init(MachineClass *mc)
681{
682 mc->desc = "ARM Integrator/CP (ARM926EJ-S)";
683 mc->init = integratorcp_init;
684}
685
686DEFINE_MACHINE("integratorcp", integratorcp_machine_init)
687
688static Property core_properties[] = {
689 DEFINE_PROP_UINT32("memsz", IntegratorCMState, memsz, 0),
690 DEFINE_PROP_END_OF_LIST(),
691};
692
693static void core_class_init(ObjectClass *klass, void *data)
694{
695 DeviceClass *dc = DEVICE_CLASS(klass);
696
697 dc->props = core_properties;
698 dc->realize = integratorcm_realize;
699 dc->vmsd = &vmstate_integratorcm;
700}
701
702static void icp_pic_class_init(ObjectClass *klass, void *data)
703{
704 DeviceClass *dc = DEVICE_CLASS(klass);
705
706 dc->vmsd = &vmstate_icp_pic;
707}
708
709static void icp_control_class_init(ObjectClass *klass, void *data)
710{
711 DeviceClass *dc = DEVICE_CLASS(klass);
712
713 dc->vmsd = &vmstate_icp_control;
714}
715
716static const TypeInfo core_info = {
717 .name = TYPE_INTEGRATOR_CM,
718 .parent = TYPE_SYS_BUS_DEVICE,
719 .instance_size = sizeof(IntegratorCMState),
720 .instance_init = integratorcm_init,
721 .class_init = core_class_init,
722};
723
724static const TypeInfo icp_pic_info = {
725 .name = TYPE_INTEGRATOR_PIC,
726 .parent = TYPE_SYS_BUS_DEVICE,
727 .instance_size = sizeof(icp_pic_state),
728 .instance_init = icp_pic_init,
729 .class_init = icp_pic_class_init,
730};
731
732static const TypeInfo icp_ctrl_regs_info = {
733 .name = TYPE_ICP_CONTROL_REGS,
734 .parent = TYPE_SYS_BUS_DEVICE,
735 .instance_size = sizeof(ICPCtrlRegsState),
736 .instance_init = icp_control_init,
737 .class_init = icp_control_class_init,
738};
739
740static void integratorcp_register_types(void)
741{
742 type_register_static(&icp_pic_info);
743 type_register_static(&core_info);
744 type_register_static(&icp_ctrl_regs_info);
745}
746
747type_init(integratorcp_register_types)
748