1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29#include "qemu/osdep.h"
30#include "qapi/error.h"
31#include "qemu-common.h"
32#include "qemu/bitmap.h"
33#include "trace.h"
34#include "qom/cpu.h"
35#include "target/arm/cpu.h"
36#include "hw/acpi/acpi-defs.h"
37#include "hw/acpi/acpi.h"
38#include "hw/nvram/fw_cfg.h"
39#include "hw/acpi/bios-linker-loader.h"
40#include "hw/loader.h"
41#include "hw/hw.h"
42#include "hw/acpi/aml-build.h"
43#include "hw/pci/pcie_host.h"
44#include "hw/pci/pci.h"
45#include "hw/arm/virt.h"
46#include "sysemu/numa.h"
47#include "kvm_arm.h"
48
49#define ARM_SPI_BASE 32
50#define ACPI_POWER_BUTTON_DEVICE "PWRB"
51
52static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus)
53{
54 uint16_t i;
55
56 for (i = 0; i < smp_cpus; i++) {
57 Aml *dev = aml_device("C%.03X", i);
58 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007")));
59 aml_append(dev, aml_name_decl("_UID", aml_int(i)));
60 aml_append(scope, dev);
61 }
62}
63
64static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
65 uint32_t uart_irq)
66{
67 Aml *dev = aml_device("COM0");
68 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011")));
69 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
70
71 Aml *crs = aml_resource_template();
72 aml_append(crs, aml_memory32_fixed(uart_memmap->base,
73 uart_memmap->size, AML_READ_WRITE));
74 aml_append(crs,
75 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
76 AML_EXCLUSIVE, &uart_irq, 1));
77 aml_append(dev, aml_name_decl("_CRS", crs));
78
79
80
81
82 aml_append(dev, aml_name_decl("_ADR", aml_int(uart_memmap->base)));
83
84 aml_append(scope, dev);
85}
86
87static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap)
88{
89 Aml *dev = aml_device("FWCF");
90 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
91
92 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
93 aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
94
95 Aml *crs = aml_resource_template();
96 aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base,
97 fw_cfg_memmap->size, AML_READ_WRITE));
98 aml_append(dev, aml_name_decl("_CRS", crs));
99 aml_append(scope, dev);
100}
101
102static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap)
103{
104 Aml *dev, *crs;
105 hwaddr base = flash_memmap->base;
106 hwaddr size = flash_memmap->size / 2;
107
108 dev = aml_device("FLS0");
109 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
110 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
111
112 crs = aml_resource_template();
113 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
114 aml_append(dev, aml_name_decl("_CRS", crs));
115 aml_append(scope, dev);
116
117 dev = aml_device("FLS1");
118 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
119 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
120 crs = aml_resource_template();
121 aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE));
122 aml_append(dev, aml_name_decl("_CRS", crs));
123 aml_append(scope, dev);
124}
125
126static void acpi_dsdt_add_virtio(Aml *scope,
127 const MemMapEntry *virtio_mmio_memmap,
128 uint32_t mmio_irq, int num)
129{
130 hwaddr base = virtio_mmio_memmap->base;
131 hwaddr size = virtio_mmio_memmap->size;
132 int i;
133
134 for (i = 0; i < num; i++) {
135 uint32_t irq = mmio_irq + i;
136 Aml *dev = aml_device("VR%02u", i);
137 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
138 aml_append(dev, aml_name_decl("_UID", aml_int(i)));
139 aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
140
141 Aml *crs = aml_resource_template();
142 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
143 aml_append(crs,
144 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
145 AML_EXCLUSIVE, &irq, 1));
146 aml_append(dev, aml_name_decl("_CRS", crs));
147 aml_append(scope, dev);
148 base += size;
149 }
150}
151
152static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
153 uint32_t irq, bool use_highmem)
154{
155 Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf;
156 int i, bus_no;
157 hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base;
158 hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size;
159 hwaddr base_pio = memmap[VIRT_PCIE_PIO].base;
160 hwaddr size_pio = memmap[VIRT_PCIE_PIO].size;
161 hwaddr base_ecam = memmap[VIRT_PCIE_ECAM].base;
162 hwaddr size_ecam = memmap[VIRT_PCIE_ECAM].size;
163 int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
164
165 Aml *dev = aml_device("%s", "PCI0");
166 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
167 aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
168 aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
169 aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
170 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
171 aml_append(dev, aml_name_decl("_UID", aml_string("PCI0")));
172 aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device")));
173 aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
174
175
176 Aml *rt_pkg = aml_package(nr_pcie_buses * PCI_NUM_PINS);
177 for (bus_no = 0; bus_no < nr_pcie_buses; bus_no++) {
178 for (i = 0; i < PCI_NUM_PINS; i++) {
179 int gsi = (i + bus_no) % PCI_NUM_PINS;
180 Aml *pkg = aml_package(4);
181 aml_append(pkg, aml_int((bus_no << 16) | 0xFFFF));
182 aml_append(pkg, aml_int(i));
183 aml_append(pkg, aml_name("GSI%d", gsi));
184 aml_append(pkg, aml_int(0));
185 aml_append(rt_pkg, pkg);
186 }
187 }
188 aml_append(dev, aml_name_decl("_PRT", rt_pkg));
189
190
191 for (i = 0; i < PCI_NUM_PINS; i++) {
192 uint32_t irqs = irq + i;
193 Aml *dev_gsi = aml_device("GSI%d", i);
194 aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F")));
195 aml_append(dev_gsi, aml_name_decl("_UID", aml_int(0)));
196 crs = aml_resource_template();
197 aml_append(crs,
198 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
199 AML_EXCLUSIVE, &irqs, 1));
200 aml_append(dev_gsi, aml_name_decl("_PRS", crs));
201 crs = aml_resource_template();
202 aml_append(crs,
203 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
204 AML_EXCLUSIVE, &irqs, 1));
205 aml_append(dev_gsi, aml_name_decl("_CRS", crs));
206 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
207 aml_append(dev_gsi, method);
208 aml_append(dev, dev_gsi);
209 }
210
211 method = aml_method("_CBA", 0, AML_NOTSERIALIZED);
212 aml_append(method, aml_return(aml_int(base_ecam)));
213 aml_append(dev, method);
214
215 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
216 Aml *rbuf = aml_resource_template();
217 aml_append(rbuf,
218 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
219 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000,
220 nr_pcie_buses));
221 aml_append(rbuf,
222 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
223 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio,
224 base_mmio + size_mmio - 1, 0x0000, size_mmio));
225 aml_append(rbuf,
226 aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
227 AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio,
228 size_pio));
229
230 if (use_highmem) {
231 hwaddr base_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].base;
232 hwaddr size_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].size;
233
234 aml_append(rbuf,
235 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
236 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
237 base_mmio_high,
238 base_mmio_high + size_mmio_high - 1, 0x0000,
239 size_mmio_high));
240 }
241
242 aml_append(method, aml_name_decl("RBUF", rbuf));
243 aml_append(method, aml_return(rbuf));
244 aml_append(dev, method);
245
246
247 aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
248 aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
249 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
250 aml_append(method,
251 aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
252
253
254
255
256
257
258
259 UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766");
260 ifctx = aml_if(aml_equal(aml_arg(0), UUID));
261 aml_append(ifctx,
262 aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
263 aml_append(ifctx,
264 aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
265 aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
266 aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
267 aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D), NULL),
268 aml_name("CTRL")));
269
270 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1))));
271 aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x08), NULL),
272 aml_name("CDW1")));
273 aml_append(ifctx, ifctx1);
274
275 ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL"))));
276 aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x10), NULL),
277 aml_name("CDW1")));
278 aml_append(ifctx, ifctx1);
279
280 aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3")));
281 aml_append(ifctx, aml_return(aml_arg(3)));
282 aml_append(method, ifctx);
283
284 elsectx = aml_else();
285 aml_append(elsectx, aml_store(aml_or(aml_name("CDW1"), aml_int(4), NULL),
286 aml_name("CDW1")));
287 aml_append(elsectx, aml_return(aml_arg(3)));
288 aml_append(method, elsectx);
289 aml_append(dev, method);
290
291 method = aml_method("_DSM", 4, AML_NOTSERIALIZED);
292
293
294
295
296
297
298 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
299 ifctx = aml_if(aml_equal(aml_arg(0), UUID));
300 ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
301 uint8_t byte_list[1] = {1};
302 buf = aml_buffer(1, byte_list);
303 aml_append(ifctx1, aml_return(buf));
304 aml_append(ifctx, ifctx1);
305 aml_append(method, ifctx);
306
307 byte_list[0] = 0;
308 buf = aml_buffer(1, byte_list);
309 aml_append(method, aml_return(buf));
310 aml_append(dev, method);
311
312 Aml *dev_rp0 = aml_device("%s", "RP0");
313 aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0)));
314 aml_append(dev, dev_rp0);
315
316 Aml *dev_res0 = aml_device("%s", "RES0");
317 aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02")));
318 crs = aml_resource_template();
319 aml_append(crs, aml_memory32_fixed(base_ecam, size_ecam, AML_READ_WRITE));
320 aml_append(dev_res0, aml_name_decl("_CRS", crs));
321 aml_append(dev, dev_res0);
322 aml_append(scope, dev);
323}
324
325static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap,
326 uint32_t gpio_irq)
327{
328 Aml *dev = aml_device("GPO0");
329 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061")));
330 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
331 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
332
333 Aml *crs = aml_resource_template();
334 aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size,
335 AML_READ_WRITE));
336 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
337 AML_EXCLUSIVE, &gpio_irq, 1));
338 aml_append(dev, aml_name_decl("_CRS", crs));
339
340 Aml *aei = aml_resource_template();
341
342 const uint32_t pin_list[1] = {3};
343 aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH,
344 AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1,
345 "GPO0", NULL, 0));
346 aml_append(dev, aml_name_decl("_AEI", aei));
347
348
349 Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED);
350 aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE),
351 aml_int(0x80)));
352 aml_append(dev, method);
353 aml_append(scope, dev);
354}
355
356static void acpi_dsdt_add_power_button(Aml *scope)
357{
358 Aml *dev = aml_device(ACPI_POWER_BUTTON_DEVICE);
359 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C0C")));
360 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
361 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
362 aml_append(scope, dev);
363}
364
365
366static GArray *
367build_rsdp(GArray *rsdp_table, BIOSLinker *linker, unsigned xsdt_tbl_offset)
368{
369 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
370 unsigned xsdt_pa_size = sizeof(rsdp->xsdt_physical_address);
371 unsigned xsdt_pa_offset =
372 (char *)&rsdp->xsdt_physical_address - rsdp_table->data;
373
374 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, rsdp_table, 16,
375 true );
376
377 memcpy(&rsdp->signature, "RSD PTR ", sizeof(rsdp->signature));
378 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, sizeof(rsdp->oem_id));
379 rsdp->length = cpu_to_le32(sizeof(*rsdp));
380 rsdp->revision = 0x02;
381
382
383 bios_linker_loader_add_pointer(linker,
384 ACPI_BUILD_RSDP_FILE, xsdt_pa_offset, xsdt_pa_size,
385 ACPI_BUILD_TABLE_FILE, xsdt_tbl_offset);
386
387
388 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
389 (char *)rsdp - rsdp_table->data, sizeof *rsdp,
390 (char *)&rsdp->checksum - rsdp_table->data);
391
392 return rsdp_table;
393}
394
395static void
396build_iort(GArray *table_data, BIOSLinker *linker)
397{
398 int iort_start = table_data->len;
399 AcpiIortIdMapping *idmap;
400 AcpiIortItsGroup *its;
401 AcpiIortTable *iort;
402 size_t node_size, iort_length;
403 AcpiIortRC *rc;
404
405 iort = acpi_data_push(table_data, sizeof(*iort));
406
407 iort_length = sizeof(*iort);
408 iort->node_count = cpu_to_le32(2);
409 iort->node_offset = cpu_to_le32(sizeof(*iort));
410
411
412 node_size = sizeof(*its) + sizeof(uint32_t);
413 iort_length += node_size;
414 its = acpi_data_push(table_data, node_size);
415
416 its->type = ACPI_IORT_NODE_ITS_GROUP;
417 its->length = cpu_to_le16(node_size);
418 its->its_count = cpu_to_le32(1);
419 its->identifiers[0] = 0;
420
421
422 node_size = sizeof(*rc) + sizeof(*idmap);
423 iort_length += node_size;
424 rc = acpi_data_push(table_data, node_size);
425
426 rc->type = ACPI_IORT_NODE_PCI_ROOT_COMPLEX;
427 rc->length = cpu_to_le16(node_size);
428 rc->mapping_count = cpu_to_le32(1);
429 rc->mapping_offset = cpu_to_le32(sizeof(*rc));
430
431
432 rc->memory_properties.cache_coherency = cpu_to_le32(1);
433 rc->memory_properties.memory_flags = 0x3;
434 rc->pci_segment_number = 0;
435
436
437 idmap = &rc->id_mapping_array[0];
438 idmap->input_base = 0;
439 idmap->id_count = cpu_to_le32(0xFFFF);
440 idmap->output_base = 0;
441
442 idmap->output_reference = cpu_to_le32(iort->node_offset);
443
444 iort->length = cpu_to_le32(iort_length);
445
446 build_header(linker, table_data, (void *)(table_data->data + iort_start),
447 "IORT", table_data->len - iort_start, 0, NULL, NULL);
448}
449
450static void
451build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
452{
453 AcpiSerialPortConsoleRedirection *spcr;
454 const MemMapEntry *uart_memmap = &vms->memmap[VIRT_UART];
455 int irq = vms->irqmap[VIRT_UART] + ARM_SPI_BASE;
456
457 spcr = acpi_data_push(table_data, sizeof(*spcr));
458
459 spcr->interface_type = 0x3;
460
461 spcr->base_address.space_id = AML_SYSTEM_MEMORY;
462 spcr->base_address.bit_width = 8;
463 spcr->base_address.bit_offset = 0;
464 spcr->base_address.access_width = 1;
465 spcr->base_address.address = cpu_to_le64(uart_memmap->base);
466
467 spcr->interrupt_types = (1 << 3);
468 spcr->gsi = cpu_to_le32(irq);
469
470 spcr->baud = 3;
471 spcr->parity = 0;
472 spcr->stopbits = 1;
473 spcr->flowctrl = (1 << 1);
474 spcr->term_type = 0;
475
476 spcr->pci_device_id = 0xffff;
477 spcr->pci_vendor_id = 0xffff;
478
479 build_header(linker, table_data, (void *)spcr, "SPCR", sizeof(*spcr), 2,
480 NULL, NULL);
481}
482
483static void
484build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
485{
486 AcpiSystemResourceAffinityTable *srat;
487 AcpiSratProcessorGiccAffinity *core;
488 AcpiSratMemoryAffinity *numamem;
489 int i, srat_start;
490 uint64_t mem_base;
491 MachineClass *mc = MACHINE_GET_CLASS(vms);
492 const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(MACHINE(vms));
493
494 srat_start = table_data->len;
495 srat = acpi_data_push(table_data, sizeof(*srat));
496 srat->reserved1 = cpu_to_le32(1);
497
498 for (i = 0; i < cpu_list->len; ++i) {
499 core = acpi_data_push(table_data, sizeof(*core));
500 core->type = ACPI_SRAT_PROCESSOR_GICC;
501 core->length = sizeof(*core);
502 core->proximity = cpu_to_le32(cpu_list->cpus[i].props.node_id);
503 core->acpi_processor_uid = cpu_to_le32(i);
504 core->flags = cpu_to_le32(1);
505 }
506
507 mem_base = vms->memmap[VIRT_MEM].base;
508 for (i = 0; i < nb_numa_nodes; ++i) {
509 numamem = acpi_data_push(table_data, sizeof(*numamem));
510 build_srat_memory(numamem, mem_base, numa_info[i].node_mem, i,
511 MEM_AFFINITY_ENABLED);
512 mem_base += numa_info[i].node_mem;
513 }
514
515 build_header(linker, table_data, (void *)srat, "SRAT",
516 table_data->len - srat_start, 3, NULL, NULL);
517}
518
519static void
520build_mcfg(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
521{
522 AcpiTableMcfg *mcfg;
523 const MemMapEntry *memmap = vms->memmap;
524 int len = sizeof(*mcfg) + sizeof(mcfg->allocation[0]);
525
526 mcfg = acpi_data_push(table_data, len);
527 mcfg->allocation[0].address = cpu_to_le64(memmap[VIRT_PCIE_ECAM].base);
528
529
530 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
531 mcfg->allocation[0].start_bus_number = 0;
532 mcfg->allocation[0].end_bus_number = (memmap[VIRT_PCIE_ECAM].size
533 / PCIE_MMCFG_SIZE_MIN) - 1;
534
535 build_header(linker, table_data, (void *)mcfg, "MCFG", len, 1, NULL, NULL);
536}
537
538
539static void
540build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
541{
542 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
543 int gtdt_start = table_data->len;
544 AcpiGenericTimerTable *gtdt;
545 uint32_t irqflags;
546
547 if (vmc->claim_edge_triggered_timers) {
548 irqflags = ACPI_GTDT_INTERRUPT_MODE_EDGE;
549 } else {
550 irqflags = ACPI_GTDT_INTERRUPT_MODE_LEVEL;
551 }
552
553 gtdt = acpi_data_push(table_data, sizeof *gtdt);
554
555 gtdt->secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_S_EL1_IRQ + 16);
556 gtdt->secure_el1_flags = cpu_to_le32(irqflags);
557
558 gtdt->non_secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL1_IRQ + 16);
559 gtdt->non_secure_el1_flags = cpu_to_le32(irqflags |
560 ACPI_GTDT_CAP_ALWAYS_ON);
561
562 gtdt->virtual_timer_interrupt = cpu_to_le32(ARCH_TIMER_VIRT_IRQ + 16);
563 gtdt->virtual_timer_flags = cpu_to_le32(irqflags);
564
565 gtdt->non_secure_el2_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL2_IRQ + 16);
566 gtdt->non_secure_el2_flags = cpu_to_le32(irqflags);
567
568 build_header(linker, table_data,
569 (void *)(table_data->data + gtdt_start), "GTDT",
570 table_data->len - gtdt_start, 2, NULL, NULL);
571}
572
573
574static void
575build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
576{
577 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
578 int madt_start = table_data->len;
579 const MemMapEntry *memmap = vms->memmap;
580 const int *irqmap = vms->irqmap;
581 AcpiMultipleApicTable *madt;
582 AcpiMadtGenericDistributor *gicd;
583 AcpiMadtGenericMsiFrame *gic_msi;
584 int i;
585
586 madt = acpi_data_push(table_data, sizeof *madt);
587
588 gicd = acpi_data_push(table_data, sizeof *gicd);
589 gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR;
590 gicd->length = sizeof(*gicd);
591 gicd->base_address = cpu_to_le64(memmap[VIRT_GIC_DIST].base);
592 gicd->version = vms->gic_version;
593
594 for (i = 0; i < vms->smp_cpus; i++) {
595 AcpiMadtGenericCpuInterface *gicc = acpi_data_push(table_data,
596 sizeof(*gicc));
597 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
598
599 gicc->type = ACPI_APIC_GENERIC_CPU_INTERFACE;
600 gicc->length = sizeof(*gicc);
601 if (vms->gic_version == 2) {
602 gicc->base_address = cpu_to_le64(memmap[VIRT_GIC_CPU].base);
603 }
604 gicc->cpu_interface_number = cpu_to_le32(i);
605 gicc->arm_mpidr = cpu_to_le64(armcpu->mp_affinity);
606 gicc->uid = cpu_to_le32(i);
607 gicc->flags = cpu_to_le32(ACPI_MADT_GICC_ENABLED);
608
609 if (arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
610 gicc->performance_interrupt = cpu_to_le32(PPI(VIRTUAL_PMU_IRQ));
611 }
612 if (vms->virt && vms->gic_version == 3) {
613 gicc->vgic_interrupt = cpu_to_le32(PPI(ARCH_GICV3_MAINT_IRQ));
614 }
615 }
616
617 if (vms->gic_version == 3) {
618 AcpiMadtGenericTranslator *gic_its;
619 AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data,
620 sizeof *gicr);
621
622 gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR;
623 gicr->length = sizeof(*gicr);
624 gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base);
625 gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size);
626
627 if (its_class_name() && !vmc->no_its) {
628 gic_its = acpi_data_push(table_data, sizeof *gic_its);
629 gic_its->type = ACPI_APIC_GENERIC_TRANSLATOR;
630 gic_its->length = sizeof(*gic_its);
631 gic_its->translation_id = 0;
632 gic_its->base_address = cpu_to_le64(memmap[VIRT_GIC_ITS].base);
633 }
634 } else {
635 gic_msi = acpi_data_push(table_data, sizeof *gic_msi);
636 gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME;
637 gic_msi->length = sizeof(*gic_msi);
638 gic_msi->gic_msi_frame_id = 0;
639 gic_msi->base_address = cpu_to_le64(memmap[VIRT_GIC_V2M].base);
640 gic_msi->flags = cpu_to_le32(1);
641 gic_msi->spi_count = cpu_to_le16(NUM_GICV2M_SPIS);
642 gic_msi->spi_base = cpu_to_le16(irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE);
643 }
644
645 build_header(linker, table_data,
646 (void *)(table_data->data + madt_start), "APIC",
647 table_data->len - madt_start, 3, NULL, NULL);
648}
649
650
651static void build_fadt(GArray *table_data, BIOSLinker *linker,
652 VirtMachineState *vms, unsigned dsdt_tbl_offset)
653{
654 AcpiFadtDescriptorRev5_1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
655 unsigned xdsdt_entry_offset = (char *)&fadt->x_dsdt - table_data->data;
656 uint16_t bootflags;
657
658 switch (vms->psci_conduit) {
659 case QEMU_PSCI_CONDUIT_DISABLED:
660 bootflags = 0;
661 break;
662 case QEMU_PSCI_CONDUIT_HVC:
663 bootflags = ACPI_FADT_ARM_PSCI_COMPLIANT | ACPI_FADT_ARM_PSCI_USE_HVC;
664 break;
665 case QEMU_PSCI_CONDUIT_SMC:
666 bootflags = ACPI_FADT_ARM_PSCI_COMPLIANT;
667 break;
668 default:
669 g_assert_not_reached();
670 }
671
672
673 fadt->flags = cpu_to_le32(1 << ACPI_FADT_F_HW_REDUCED_ACPI);
674 fadt->arm_boot_flags = cpu_to_le16(bootflags);
675
676
677 fadt->minor_revision = 0x1;
678
679
680 bios_linker_loader_add_pointer(linker,
681 ACPI_BUILD_TABLE_FILE, xdsdt_entry_offset, sizeof(fadt->x_dsdt),
682 ACPI_BUILD_TABLE_FILE, dsdt_tbl_offset);
683
684 build_header(linker, table_data,
685 (void *)fadt, "FACP", sizeof(*fadt), 5, NULL, NULL);
686}
687
688
689static void
690build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
691{
692 Aml *scope, *dsdt;
693 const MemMapEntry *memmap = vms->memmap;
694 const int *irqmap = vms->irqmap;
695
696 dsdt = init_aml_allocator();
697
698 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
699
700
701
702
703
704
705 scope = aml_scope("\\_SB");
706 acpi_dsdt_add_cpus(scope, vms->smp_cpus);
707 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART],
708 (irqmap[VIRT_UART] + ARM_SPI_BASE));
709 acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
710 acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]);
711 acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
712 (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
713 acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE),
714 vms->highmem);
715 acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO],
716 (irqmap[VIRT_GPIO] + ARM_SPI_BASE));
717 acpi_dsdt_add_power_button(scope);
718
719 aml_append(dsdt, scope);
720
721
722 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
723 build_header(linker, table_data,
724 (void *)(table_data->data + table_data->len - dsdt->buf->len),
725 "DSDT", dsdt->buf->len, 2, NULL, NULL);
726 free_aml_allocator();
727}
728
729typedef
730struct AcpiBuildState {
731
732 MemoryRegion *table_mr;
733 MemoryRegion *rsdp_mr;
734 MemoryRegion *linker_mr;
735
736 bool patched;
737} AcpiBuildState;
738
739static
740void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
741{
742 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
743 GArray *table_offsets;
744 unsigned dsdt, xsdt;
745 GArray *tables_blob = tables->table_data;
746
747 table_offsets = g_array_new(false, true ,
748 sizeof(uint32_t));
749
750 bios_linker_loader_alloc(tables->linker,
751 ACPI_BUILD_TABLE_FILE, tables_blob,
752 64, false );
753
754
755 dsdt = tables_blob->len;
756 build_dsdt(tables_blob, tables->linker, vms);
757
758
759 acpi_add_table(table_offsets, tables_blob);
760 build_fadt(tables_blob, tables->linker, vms, dsdt);
761
762 acpi_add_table(table_offsets, tables_blob);
763 build_madt(tables_blob, tables->linker, vms);
764
765 acpi_add_table(table_offsets, tables_blob);
766 build_gtdt(tables_blob, tables->linker, vms);
767
768 acpi_add_table(table_offsets, tables_blob);
769 build_mcfg(tables_blob, tables->linker, vms);
770
771 acpi_add_table(table_offsets, tables_blob);
772 build_spcr(tables_blob, tables->linker, vms);
773
774 if (nb_numa_nodes > 0) {
775 acpi_add_table(table_offsets, tables_blob);
776 build_srat(tables_blob, tables->linker, vms);
777 if (have_numa_distance) {
778 acpi_add_table(table_offsets, tables_blob);
779 build_slit(tables_blob, tables->linker);
780 }
781 }
782
783 if (its_class_name() && !vmc->no_its) {
784 acpi_add_table(table_offsets, tables_blob);
785 build_iort(tables_blob, tables->linker);
786 }
787
788
789 xsdt = tables_blob->len;
790 build_xsdt(tables_blob, tables->linker, table_offsets, NULL, NULL);
791
792
793 build_rsdp(tables->rsdp, tables->linker, xsdt);
794
795
796 g_array_free(table_offsets, true);
797}
798
799static void acpi_ram_update(MemoryRegion *mr, GArray *data)
800{
801 uint32_t size = acpi_data_len(data);
802
803
804
805 memory_region_ram_resize(mr, size, &error_abort);
806
807 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
808 memory_region_set_dirty(mr, 0, size);
809}
810
811static void virt_acpi_build_update(void *build_opaque)
812{
813 AcpiBuildState *build_state = build_opaque;
814 AcpiBuildTables tables;
815
816
817 if (!build_state || build_state->patched) {
818 return;
819 }
820 build_state->patched = true;
821
822 acpi_build_tables_init(&tables);
823
824 virt_acpi_build(VIRT_MACHINE(qdev_get_machine()), &tables);
825
826 acpi_ram_update(build_state->table_mr, tables.table_data);
827 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
828 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
829
830 acpi_build_tables_cleanup(&tables, true);
831}
832
833static void virt_acpi_build_reset(void *build_opaque)
834{
835 AcpiBuildState *build_state = build_opaque;
836 build_state->patched = false;
837}
838
839static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
840 GArray *blob, const char *name,
841 uint64_t max_size)
842{
843 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
844 name, virt_acpi_build_update, build_state, NULL, true);
845}
846
847static const VMStateDescription vmstate_virt_acpi_build = {
848 .name = "virt_acpi_build",
849 .version_id = 1,
850 .minimum_version_id = 1,
851 .fields = (VMStateField[]) {
852 VMSTATE_BOOL(patched, AcpiBuildState),
853 VMSTATE_END_OF_LIST()
854 },
855};
856
857void virt_acpi_setup(VirtMachineState *vms)
858{
859 AcpiBuildTables tables;
860 AcpiBuildState *build_state;
861
862 if (!vms->fw_cfg) {
863 trace_virt_acpi_setup();
864 return;
865 }
866
867 if (!acpi_enabled) {
868 trace_virt_acpi_setup();
869 return;
870 }
871
872 build_state = g_malloc0(sizeof *build_state);
873
874 acpi_build_tables_init(&tables);
875 virt_acpi_build(vms, &tables);
876
877
878 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
879 ACPI_BUILD_TABLE_FILE,
880 ACPI_BUILD_TABLE_MAX_SIZE);
881 assert(build_state->table_mr != NULL);
882
883 build_state->linker_mr =
884 acpi_add_rom_blob(build_state, tables.linker->cmd_blob,
885 "etc/table-loader", 0);
886
887 fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data,
888 acpi_data_len(tables.tcpalog));
889
890 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
891 ACPI_BUILD_RSDP_FILE, 0);
892
893 qemu_register_reset(virt_acpi_build_reset, build_state);
894 virt_acpi_build_reset(build_state);
895 vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state);
896
897
898
899
900 acpi_build_tables_cleanup(&tables, false);
901}
902
