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25#include "qemu/osdep.h"
26#include "qemu/log.h"
27#include "hw/display/xlnx_dp.h"
28
29#ifndef DEBUG_DP
30#define DEBUG_DP 0
31#endif
32
33#define DPRINTF(fmt, ...) do { \
34 if (DEBUG_DP) { \
35 qemu_log("xlnx_dp: " fmt , ## __VA_ARGS__); \
36 } \
37} while (0);
38
39
40
41
42#define DP_LINK_BW_SET (0x0000 >> 2)
43#define DP_LANE_COUNT_SET (0x0004 >> 2)
44#define DP_ENHANCED_FRAME_EN (0x0008 >> 2)
45#define DP_TRAINING_PATTERN_SET (0x000C >> 2)
46#define DP_LINK_QUAL_PATTERN_SET (0x0010 >> 2)
47#define DP_SCRAMBLING_DISABLE (0x0014 >> 2)
48#define DP_DOWNSPREAD_CTRL (0x0018 >> 2)
49#define DP_SOFTWARE_RESET (0x001C >> 2)
50#define DP_TRANSMITTER_ENABLE (0x0080 >> 2)
51#define DP_MAIN_STREAM_ENABLE (0x0084 >> 2)
52#define DP_FORCE_SCRAMBLER_RESET (0x00C0 >> 2)
53#define DP_VERSION_REGISTER (0x00F8 >> 2)
54#define DP_CORE_ID (0x00FC >> 2)
55
56#define DP_AUX_COMMAND_REGISTER (0x0100 >> 2)
57#define AUX_ADDR_ONLY_MASK (0x1000)
58#define AUX_COMMAND_MASK (0x0F00)
59#define AUX_COMMAND_SHIFT (8)
60#define AUX_COMMAND_NBYTES (0x000F)
61
62#define DP_AUX_WRITE_FIFO (0x0104 >> 2)
63#define DP_AUX_ADDRESS (0x0108 >> 2)
64#define DP_AUX_CLOCK_DIVIDER (0x010C >> 2)
65#define DP_TX_USER_FIFO_OVERFLOW (0x0110 >> 2)
66#define DP_INTERRUPT_SIGNAL_STATE (0x0130 >> 2)
67#define DP_AUX_REPLY_DATA (0x0134 >> 2)
68#define DP_AUX_REPLY_CODE (0x0138 >> 2)
69#define DP_AUX_REPLY_COUNT (0x013C >> 2)
70#define DP_REPLY_DATA_COUNT (0x0148 >> 2)
71#define DP_REPLY_STATUS (0x014C >> 2)
72#define DP_HPD_DURATION (0x0150 >> 2)
73#define DP_MAIN_STREAM_HTOTAL (0x0180 >> 2)
74#define DP_MAIN_STREAM_VTOTAL (0x0184 >> 2)
75#define DP_MAIN_STREAM_POLARITY (0x0188 >> 2)
76#define DP_MAIN_STREAM_HSWIDTH (0x018C >> 2)
77#define DP_MAIN_STREAM_VSWIDTH (0x0190 >> 2)
78#define DP_MAIN_STREAM_HRES (0x0194 >> 2)
79#define DP_MAIN_STREAM_VRES (0x0198 >> 2)
80#define DP_MAIN_STREAM_HSTART (0x019C >> 2)
81#define DP_MAIN_STREAM_VSTART (0x01A0 >> 2)
82#define DP_MAIN_STREAM_MISC0 (0x01A4 >> 2)
83#define DP_MAIN_STREAM_MISC1 (0x01A8 >> 2)
84#define DP_MAIN_STREAM_M_VID (0x01AC >> 2)
85#define DP_MSA_TRANSFER_UNIT_SIZE (0x01B0 >> 2)
86#define DP_MAIN_STREAM_N_VID (0x01B4 >> 2)
87#define DP_USER_DATA_COUNT_PER_LANE (0x01BC >> 2)
88#define DP_MIN_BYTES_PER_TU (0x01C4 >> 2)
89#define DP_FRAC_BYTES_PER_TU (0x01C8 >> 2)
90#define DP_INIT_WAIT (0x01CC >> 2)
91#define DP_PHY_RESET (0x0200 >> 2)
92#define DP_PHY_VOLTAGE_DIFF_LANE_0 (0x0220 >> 2)
93#define DP_PHY_VOLTAGE_DIFF_LANE_1 (0x0224 >> 2)
94#define DP_TRANSMIT_PRBS7 (0x0230 >> 2)
95#define DP_PHY_CLOCK_SELECT (0x0234 >> 2)
96#define DP_TX_PHY_POWER_DOWN (0x0238 >> 2)
97#define DP_PHY_PRECURSOR_LANE_0 (0x023C >> 2)
98#define DP_PHY_PRECURSOR_LANE_1 (0x0240 >> 2)
99#define DP_PHY_POSTCURSOR_LANE_0 (0x024C >> 2)
100#define DP_PHY_POSTCURSOR_LANE_1 (0x0250 >> 2)
101#define DP_PHY_STATUS (0x0280 >> 2)
102
103#define DP_TX_AUDIO_CONTROL (0x0300 >> 2)
104#define DP_TX_AUD_CTRL (1)
105
106#define DP_TX_AUDIO_CHANNELS (0x0304 >> 2)
107#define DP_TX_AUDIO_INFO_DATA(n) ((0x0308 + 4 * n) >> 2)
108#define DP_TX_M_AUD (0x0328 >> 2)
109#define DP_TX_N_AUD (0x032C >> 2)
110#define DP_TX_AUDIO_EXT_DATA(n) ((0x0330 + 4 * n) >> 2)
111#define DP_INT_STATUS (0x03A0 >> 2)
112#define DP_INT_MASK (0x03A4 >> 2)
113#define DP_INT_EN (0x03A8 >> 2)
114#define DP_INT_DS (0x03AC >> 2)
115
116
117
118
119#define V_BLEND_OFFSET (0xA000)
120#define V_BLEND_BG_CLR_0 (0x0000 >> 2)
121#define V_BLEND_BG_CLR_1 (0x0004 >> 2)
122#define V_BLEND_BG_CLR_2 (0x0008 >> 2)
123#define V_BLEND_SET_GLOBAL_ALPHA_REG (0x000C >> 2)
124#define V_BLEND_OUTPUT_VID_FORMAT (0x0014 >> 2)
125#define V_BLEND_LAYER0_CONTROL (0x0018 >> 2)
126#define V_BLEND_LAYER1_CONTROL (0x001C >> 2)
127
128#define V_BLEND_RGB2YCBCR_COEFF(n) ((0x0020 + 4 * n) >> 2)
129#define V_BLEND_IN1CSC_COEFF(n) ((0x0044 + 4 * n) >> 2)
130
131#define V_BLEND_LUMA_IN1CSC_OFFSET (0x0068 >> 2)
132#define V_BLEND_CR_IN1CSC_OFFSET (0x006C >> 2)
133#define V_BLEND_CB_IN1CSC_OFFSET (0x0070 >> 2)
134#define V_BLEND_LUMA_OUTCSC_OFFSET (0x0074 >> 2)
135#define V_BLEND_CR_OUTCSC_OFFSET (0x0078 >> 2)
136#define V_BLEND_CB_OUTCSC_OFFSET (0x007C >> 2)
137
138#define V_BLEND_IN2CSC_COEFF(n) ((0x0080 + 4 * n) >> 2)
139
140#define V_BLEND_LUMA_IN2CSC_OFFSET (0x00A4 >> 2)
141#define V_BLEND_CR_IN2CSC_OFFSET (0x00A8 >> 2)
142#define V_BLEND_CB_IN2CSC_OFFSET (0x00AC >> 2)
143#define V_BLEND_CHROMA_KEY_ENABLE (0x01D0 >> 2)
144#define V_BLEND_CHROMA_KEY_COMP1 (0x01D4 >> 2)
145#define V_BLEND_CHROMA_KEY_COMP2 (0x01D8 >> 2)
146#define V_BLEND_CHROMA_KEY_COMP3 (0x01DC >> 2)
147
148
149
150
151#define AV_BUF_MANAGER_OFFSET (0xB000)
152#define AV_BUF_FORMAT (0x0000 >> 2)
153#define AV_BUF_NON_LIVE_LATENCY (0x0008 >> 2)
154#define AV_CHBUF0 (0x0010 >> 2)
155#define AV_CHBUF1 (0x0014 >> 2)
156#define AV_CHBUF2 (0x0018 >> 2)
157#define AV_CHBUF3 (0x001C >> 2)
158#define AV_CHBUF4 (0x0020 >> 2)
159#define AV_CHBUF5 (0x0024 >> 2)
160#define AV_BUF_STC_CONTROL (0x002C >> 2)
161#define AV_BUF_STC_INIT_VALUE0 (0x0030 >> 2)
162#define AV_BUF_STC_INIT_VALUE1 (0x0034 >> 2)
163#define AV_BUF_STC_ADJ (0x0038 >> 2)
164#define AV_BUF_STC_VIDEO_VSYNC_TS_REG0 (0x003C >> 2)
165#define AV_BUF_STC_VIDEO_VSYNC_TS_REG1 (0x0040 >> 2)
166#define AV_BUF_STC_EXT_VSYNC_TS_REG0 (0x0044 >> 2)
167#define AV_BUF_STC_EXT_VSYNC_TS_REG1 (0x0048 >> 2)
168#define AV_BUF_STC_CUSTOM_EVENT_TS_REG0 (0x004C >> 2)
169#define AV_BUF_STC_CUSTOM_EVENT_TS_REG1 (0x0050 >> 2)
170#define AV_BUF_STC_CUSTOM_EVENT2_TS_REG0 (0x0054 >> 2)
171#define AV_BUF_STC_CUSTOM_EVENT2_TS_REG1 (0x0058 >> 2)
172#define AV_BUF_STC_SNAPSHOT0 (0x0060 >> 2)
173#define AV_BUF_STC_SNAPSHOT1 (0x0064 >> 2)
174#define AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT (0x0070 >> 2)
175#define AV_BUF_HCOUNT_VCOUNT_INT0 (0x0074 >> 2)
176#define AV_BUF_HCOUNT_VCOUNT_INT1 (0x0078 >> 2)
177#define AV_BUF_DITHER_CONFIG (0x007C >> 2)
178#define AV_BUF_DITHER_CONFIG_MAX (0x008C >> 2)
179#define AV_BUF_DITHER_CONFIG_MIN (0x0090 >> 2)
180#define AV_BUF_PATTERN_GEN_SELECT (0x0100 >> 2)
181#define AV_BUF_AUD_VID_CLK_SOURCE (0x0120 >> 2)
182#define AV_BUF_SRST_REG (0x0124 >> 2)
183#define AV_BUF_AUDIO_RDY_INTERVAL (0x0128 >> 2)
184#define AV_BUF_AUDIO_CH_CONFIG (0x012C >> 2)
185
186#define AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(n)((0x0200 + 4 * n) >> 2)
187
188#define AV_BUF_VIDEO_COMP_SCALE_FACTOR(n) ((0x020C + 4 * n) >> 2)
189
190#define AV_BUF_LIVE_VIDEO_COMP_SF(n) ((0x0218 + 4 * n) >> 2)
191
192#define AV_BUF_LIVE_VID_CONFIG (0x0224 >> 2)
193
194#define AV_BUF_LIVE_GFX_COMP_SF(n) ((0x0228 + 4 * n) >> 2)
195
196#define AV_BUF_LIVE_GFX_CONFIG (0x0234 >> 2)
197
198#define AUDIO_MIXER_REGISTER_OFFSET (0xC000)
199#define AUDIO_MIXER_VOLUME_CONTROL (0x0000 >> 2)
200#define AUDIO_MIXER_META_DATA (0x0004 >> 2)
201#define AUD_CH_STATUS_REG(n) ((0x0008 + 4 * n) >> 2)
202#define AUD_CH_A_DATA_REG(n) ((0x0020 + 4 * n) >> 2)
203#define AUD_CH_B_DATA_REG(n) ((0x0038 + 4 * n) >> 2)
204
205#define DP_AUDIO_DMA_CHANNEL(n) (4 + n)
206#define DP_GRAPHIC_DMA_CHANNEL (3)
207#define DP_VIDEO_DMA_CHANNEL (0)
208
209enum DPGraphicFmt {
210 DP_GRAPHIC_RGBA8888 = 0 << 8,
211 DP_GRAPHIC_ABGR8888 = 1 << 8,
212 DP_GRAPHIC_RGB888 = 2 << 8,
213 DP_GRAPHIC_BGR888 = 3 << 8,
214 DP_GRAPHIC_RGBA5551 = 4 << 8,
215 DP_GRAPHIC_RGBA4444 = 5 << 8,
216 DP_GRAPHIC_RGB565 = 6 << 8,
217 DP_GRAPHIC_8BPP = 7 << 8,
218 DP_GRAPHIC_4BPP = 8 << 8,
219 DP_GRAPHIC_2BPP = 9 << 8,
220 DP_GRAPHIC_1BPP = 10 << 8,
221 DP_GRAPHIC_MASK = 0xF << 8
222};
223
224enum DPVideoFmt {
225 DP_NL_VID_CB_Y0_CR_Y1 = 0,
226 DP_NL_VID_CR_Y0_CB_Y1 = 1,
227 DP_NL_VID_Y0_CR_Y1_CB = 2,
228 DP_NL_VID_Y0_CB_Y1_CR = 3,
229 DP_NL_VID_YV16 = 4,
230 DP_NL_VID_YV24 = 5,
231 DP_NL_VID_YV16CL = 6,
232 DP_NL_VID_MONO = 7,
233 DP_NL_VID_YV16CL2 = 8,
234 DP_NL_VID_YUV444 = 9,
235 DP_NL_VID_RGB888 = 10,
236 DP_NL_VID_RGBA8880 = 11,
237 DP_NL_VID_RGB888_10BPC = 12,
238 DP_NL_VID_YUV444_10BPC = 13,
239 DP_NL_VID_YV16CL2_10BPC = 14,
240 DP_NL_VID_YV16CL_10BPC = 15,
241 DP_NL_VID_YV16_10BPC = 16,
242 DP_NL_VID_YV24_10BPC = 17,
243 DP_NL_VID_Y_ONLY_10BPC = 18,
244 DP_NL_VID_YV16_420 = 19,
245 DP_NL_VID_YV16CL_420 = 20,
246 DP_NL_VID_YV16CL2_420 = 21,
247 DP_NL_VID_YV16_420_10BPC = 22,
248 DP_NL_VID_YV16CL_420_10BPC = 23,
249 DP_NL_VID_YV16CL2_420_10BPC = 24,
250 DP_NL_VID_FMT_MASK = 0x1F
251};
252
253typedef enum DPGraphicFmt DPGraphicFmt;
254typedef enum DPVideoFmt DPVideoFmt;
255
256static const VMStateDescription vmstate_dp = {
257 .name = TYPE_XLNX_DP,
258 .version_id = 1,
259 .fields = (VMStateField[]){
260 VMSTATE_UINT32_ARRAY(core_registers, XlnxDPState,
261 DP_CORE_REG_ARRAY_SIZE),
262 VMSTATE_UINT32_ARRAY(avbufm_registers, XlnxDPState,
263 DP_AVBUF_REG_ARRAY_SIZE),
264 VMSTATE_UINT32_ARRAY(vblend_registers, XlnxDPState,
265 DP_VBLEND_REG_ARRAY_SIZE),
266 VMSTATE_UINT32_ARRAY(audio_registers, XlnxDPState,
267 DP_AUDIO_REG_ARRAY_SIZE),
268 VMSTATE_END_OF_LIST()
269 }
270};
271
272static void xlnx_dp_update_irq(XlnxDPState *s);
273
274static uint64_t xlnx_dp_audio_read(void *opaque, hwaddr offset, unsigned size)
275{
276 XlnxDPState *s = XLNX_DP(opaque);
277
278 offset = offset >> 2;
279 return s->audio_registers[offset];
280}
281
282static void xlnx_dp_audio_write(void *opaque, hwaddr offset, uint64_t value,
283 unsigned size)
284{
285 XlnxDPState *s = XLNX_DP(opaque);
286
287 offset = offset >> 2;
288
289 switch (offset) {
290 case AUDIO_MIXER_META_DATA:
291 s->audio_registers[offset] = value & 0x00000001;
292 break;
293 default:
294 s->audio_registers[offset] = value;
295 break;
296 }
297}
298
299static const MemoryRegionOps audio_ops = {
300 .read = xlnx_dp_audio_read,
301 .write = xlnx_dp_audio_write,
302 .endianness = DEVICE_NATIVE_ENDIAN,
303};
304
305static inline uint32_t xlnx_dp_audio_get_volume(XlnxDPState *s,
306 uint8_t channel)
307{
308 switch (channel) {
309 case 0:
310 return extract32(s->audio_registers[AUDIO_MIXER_VOLUME_CONTROL], 0, 16);
311 case 1:
312 return extract32(s->audio_registers[AUDIO_MIXER_VOLUME_CONTROL], 16,
313 16);
314 default:
315 return 0;
316 }
317}
318
319static inline void xlnx_dp_audio_activate(XlnxDPState *s)
320{
321 bool activated = ((s->core_registers[DP_TX_AUDIO_CONTROL]
322 & DP_TX_AUD_CTRL) != 0);
323 AUD_set_active_out(s->amixer_output_stream, activated);
324 xlnx_dpdma_set_host_data_location(s->dpdma, DP_AUDIO_DMA_CHANNEL(0),
325 &s->audio_buffer_0);
326 xlnx_dpdma_set_host_data_location(s->dpdma, DP_AUDIO_DMA_CHANNEL(1),
327 &s->audio_buffer_1);
328}
329
330static inline void xlnx_dp_audio_mix_buffer(XlnxDPState *s)
331{
332
333
334
335
336
337
338
339 int i;
340
341 if ((s->audio_data_available[0]) && (xlnx_dp_audio_get_volume(s, 0))) {
342 for (i = 0; i < s->audio_data_available[0] / 2; i++) {
343 s->temp_buffer[i] = (int64_t)(s->audio_buffer_0[i])
344 * xlnx_dp_audio_get_volume(s, 0) / 8192;
345 }
346 s->byte_left = s->audio_data_available[0];
347 } else {
348 memset(s->temp_buffer, 0, s->audio_data_available[1] / 2);
349 }
350
351 if ((s->audio_data_available[1]) && (xlnx_dp_audio_get_volume(s, 1))) {
352 if ((s->audio_data_available[0] == 0)
353 || (s->audio_data_available[1] == s->audio_data_available[0])) {
354 for (i = 0; i < s->audio_data_available[1] / 2; i++) {
355 s->temp_buffer[i] += (int64_t)(s->audio_buffer_1[i])
356 * xlnx_dp_audio_get_volume(s, 1) / 8192;
357 }
358 s->byte_left = s->audio_data_available[1];
359 }
360 }
361
362 for (i = 0; i < s->byte_left / 2; i++) {
363 s->out_buffer[i] = MAX(-32767, MIN(s->temp_buffer[i], 32767));
364 }
365
366 s->data_ptr = 0;
367}
368
369static void xlnx_dp_audio_callback(void *opaque, int avail)
370{
371
372
373
374
375 XlnxDPState *s = XLNX_DP(opaque);
376 size_t written = 0;
377
378
379 if (s->byte_left == 0) {
380 s->audio_data_available[0] = xlnx_dpdma_start_operation(s->dpdma, 4,
381 true);
382 s->audio_data_available[1] = xlnx_dpdma_start_operation(s->dpdma, 5,
383 true);
384 xlnx_dp_audio_mix_buffer(s);
385 }
386
387
388 if (s->byte_left <= MAX_QEMU_BUFFER_SIZE) {
389 if (s->byte_left != 0) {
390 written = AUD_write(s->amixer_output_stream,
391 &s->out_buffer[s->data_ptr], s->byte_left);
392 } else {
393
394
395
396
397 written = 0;
398 memset(s->out_buffer, 0, 1024);
399 AUD_write(s->amixer_output_stream, s->out_buffer, 1024);
400 }
401 } else {
402 written = AUD_write(s->amixer_output_stream,
403 &s->out_buffer[s->data_ptr], MAX_QEMU_BUFFER_SIZE);
404 }
405 s->byte_left -= written;
406 s->data_ptr += written;
407}
408
409
410
411
412static void xlnx_dp_aux_clear_rx_fifo(XlnxDPState *s)
413{
414 fifo8_reset(&s->rx_fifo);
415}
416
417static void xlnx_dp_aux_push_rx_fifo(XlnxDPState *s, uint8_t *buf, size_t len)
418{
419 DPRINTF("Push %u data in rx_fifo\n", (unsigned)len);
420 fifo8_push_all(&s->rx_fifo, buf, len);
421}
422
423static uint8_t xlnx_dp_aux_pop_rx_fifo(XlnxDPState *s)
424{
425 uint8_t ret;
426
427 if (fifo8_is_empty(&s->rx_fifo)) {
428 DPRINTF("rx_fifo underflow..\n");
429 abort();
430 }
431 ret = fifo8_pop(&s->rx_fifo);
432 DPRINTF("pop 0x%" PRIX8 " from rx_fifo.\n", ret);
433 return ret;
434}
435
436static void xlnx_dp_aux_clear_tx_fifo(XlnxDPState *s)
437{
438 fifo8_reset(&s->tx_fifo);
439}
440
441static void xlnx_dp_aux_push_tx_fifo(XlnxDPState *s, uint8_t *buf, size_t len)
442{
443 DPRINTF("Push %u data in tx_fifo\n", (unsigned)len);
444 fifo8_push_all(&s->tx_fifo, buf, len);
445}
446
447static uint8_t xlnx_dp_aux_pop_tx_fifo(XlnxDPState *s)
448{
449 uint8_t ret;
450
451 if (fifo8_is_empty(&s->tx_fifo)) {
452 DPRINTF("tx_fifo underflow..\n");
453 abort();
454 }
455 ret = fifo8_pop(&s->tx_fifo);
456 DPRINTF("pop 0x%2.2X from tx_fifo.\n", ret);
457 return ret;
458}
459
460static uint32_t xlnx_dp_aux_get_address(XlnxDPState *s)
461{
462 return s->core_registers[DP_AUX_ADDRESS];
463}
464
465
466
467
468static void xlnx_dp_aux_set_command(XlnxDPState *s, uint32_t value)
469{
470 bool address_only = (value & AUX_ADDR_ONLY_MASK) != 0;
471 AUXCommand cmd = (value & AUX_COMMAND_MASK) >> AUX_COMMAND_SHIFT;
472 uint8_t nbytes = (value & AUX_COMMAND_NBYTES) + 1;
473 uint8_t buf[16];
474 int i;
475
476
477
478
479
480 if (address_only) {
481 nbytes = 0;
482 }
483
484 switch (cmd) {
485 case READ_AUX:
486 case READ_I2C:
487 case READ_I2C_MOT:
488 s->core_registers[DP_AUX_REPLY_CODE] = aux_request(s->aux_bus, cmd,
489 xlnx_dp_aux_get_address(s),
490 nbytes, buf);
491 s->core_registers[DP_REPLY_DATA_COUNT] = nbytes;
492
493 if (s->core_registers[DP_AUX_REPLY_CODE] == AUX_I2C_ACK) {
494 xlnx_dp_aux_push_rx_fifo(s, buf, nbytes);
495 }
496 break;
497 case WRITE_AUX:
498 case WRITE_I2C:
499 case WRITE_I2C_MOT:
500 for (i = 0; i < nbytes; i++) {
501 buf[i] = xlnx_dp_aux_pop_tx_fifo(s);
502 }
503 s->core_registers[DP_AUX_REPLY_CODE] = aux_request(s->aux_bus, cmd,
504 xlnx_dp_aux_get_address(s),
505 nbytes, buf);
506 xlnx_dp_aux_clear_tx_fifo(s);
507 break;
508 case WRITE_I2C_STATUS:
509 qemu_log_mask(LOG_UNIMP, "xlnx_dp: Write i2c status not implemented\n");
510 break;
511 default:
512 abort();
513 }
514
515 s->core_registers[DP_INTERRUPT_SIGNAL_STATE] |= 0x04;
516}
517
518static void xlnx_dp_set_dpdma(const Object *obj, const char *name, Object *val,
519 Error **errp)
520{
521 XlnxDPState *s = XLNX_DP(obj);
522 if (s->console) {
523 DisplaySurface *surface = qemu_console_surface(s->console);
524 XlnxDPDMAState *dma = XLNX_DPDMA(val);
525 xlnx_dpdma_set_host_data_location(dma, DP_GRAPHIC_DMA_CHANNEL,
526 surface_data(surface));
527 }
528}
529
530static inline uint8_t xlnx_dp_global_alpha_value(XlnxDPState *s)
531{
532 return (s->vblend_registers[V_BLEND_SET_GLOBAL_ALPHA_REG] & 0x1FE) >> 1;
533}
534
535static inline bool xlnx_dp_global_alpha_enabled(XlnxDPState *s)
536{
537
538
539
540
541 return ((xlnx_dp_global_alpha_value(s) != 0xFF) &&
542 ((s->vblend_registers[V_BLEND_SET_GLOBAL_ALPHA_REG] & 0x01) != 0));
543}
544
545static void xlnx_dp_recreate_surface(XlnxDPState *s)
546{
547
548
549
550
551 uint16_t width = s->core_registers[DP_MAIN_STREAM_HRES];
552 uint16_t height = s->core_registers[DP_MAIN_STREAM_VRES];
553 DisplaySurface *current_console_surface = qemu_console_surface(s->console);
554
555 if ((width != 0) && (height != 0)) {
556
557
558
559
560
561 if (s->bout_plane.surface != current_console_surface) {
562 qemu_free_displaysurface(s->bout_plane.surface);
563 }
564 if (s->v_plane.surface != current_console_surface) {
565 qemu_free_displaysurface(s->v_plane.surface);
566 }
567 if (s->g_plane.surface != current_console_surface) {
568 qemu_free_displaysurface(s->g_plane.surface);
569 }
570
571 s->g_plane.surface
572 = qemu_create_displaysurface_from(width, height,
573 s->g_plane.format, 0, NULL);
574 s->v_plane.surface
575 = qemu_create_displaysurface_from(width, height,
576 s->v_plane.format, 0, NULL);
577 if (xlnx_dp_global_alpha_enabled(s)) {
578 s->bout_plane.surface =
579 qemu_create_displaysurface_from(width,
580 height,
581 s->g_plane.format,
582 0, NULL);
583 dpy_gfx_replace_surface(s->console, s->bout_plane.surface);
584 } else {
585 s->bout_plane.surface = NULL;
586 dpy_gfx_replace_surface(s->console, s->g_plane.surface);
587 }
588
589 xlnx_dpdma_set_host_data_location(s->dpdma, DP_GRAPHIC_DMA_CHANNEL,
590 surface_data(s->g_plane.surface));
591 xlnx_dpdma_set_host_data_location(s->dpdma, DP_VIDEO_DMA_CHANNEL,
592 surface_data(s->v_plane.surface));
593 }
594}
595
596
597
598
599static void xlnx_dp_change_graphic_fmt(XlnxDPState *s)
600{
601 switch (s->avbufm_registers[AV_BUF_FORMAT] & DP_GRAPHIC_MASK) {
602 case DP_GRAPHIC_RGBA8888:
603 s->g_plane.format = PIXMAN_r8g8b8a8;
604 break;
605 case DP_GRAPHIC_ABGR8888:
606 s->g_plane.format = PIXMAN_a8b8g8r8;
607 break;
608 case DP_GRAPHIC_RGB565:
609 s->g_plane.format = PIXMAN_r5g6b5;
610 break;
611 case DP_GRAPHIC_RGB888:
612 s->g_plane.format = PIXMAN_r8g8b8;
613 break;
614 case DP_GRAPHIC_BGR888:
615 s->g_plane.format = PIXMAN_b8g8r8;
616 break;
617 default:
618 DPRINTF("error: unsupported graphic format %u.\n",
619 s->avbufm_registers[AV_BUF_FORMAT] & DP_GRAPHIC_MASK);
620 abort();
621 }
622
623 switch (s->avbufm_registers[AV_BUF_FORMAT] & DP_NL_VID_FMT_MASK) {
624 case 0:
625 s->v_plane.format = PIXMAN_x8b8g8r8;
626 break;
627 case DP_NL_VID_Y0_CB_Y1_CR:
628 s->v_plane.format = PIXMAN_yuy2;
629 break;
630 case DP_NL_VID_RGBA8880:
631 s->v_plane.format = PIXMAN_x8b8g8r8;
632 break;
633 default:
634 DPRINTF("error: unsupported video format %u.\n",
635 s->avbufm_registers[AV_BUF_FORMAT] & DP_NL_VID_FMT_MASK);
636 abort();
637 }
638
639 xlnx_dp_recreate_surface(s);
640}
641
642static void xlnx_dp_update_irq(XlnxDPState *s)
643{
644 uint32_t flags;
645
646 flags = s->core_registers[DP_INT_STATUS] & ~s->core_registers[DP_INT_MASK];
647 DPRINTF("update IRQ value = %" PRIx32 "\n", flags);
648 qemu_set_irq(s->irq, flags != 0);
649}
650
651static uint64_t xlnx_dp_read(void *opaque, hwaddr offset, unsigned size)
652{
653 XlnxDPState *s = XLNX_DP(opaque);
654 uint64_t ret = 0;
655
656 offset = offset >> 2;
657
658 switch (offset) {
659 case DP_TX_USER_FIFO_OVERFLOW:
660
661 ret = s->core_registers[DP_TX_USER_FIFO_OVERFLOW];
662 s->core_registers[DP_TX_USER_FIFO_OVERFLOW] = 0;
663 break;
664 case DP_AUX_REPLY_DATA:
665 ret = xlnx_dp_aux_pop_rx_fifo(s);
666 break;
667 case DP_INTERRUPT_SIGNAL_STATE:
668
669
670
671
672
673 ret = s->core_registers[DP_INTERRUPT_SIGNAL_STATE];
674 s->core_registers[DP_INTERRUPT_SIGNAL_STATE] &= ~0x04;
675 break;
676 case DP_AUX_WRITE_FIFO:
677 case DP_TX_AUDIO_INFO_DATA(0):
678 case DP_TX_AUDIO_INFO_DATA(1):
679 case DP_TX_AUDIO_INFO_DATA(2):
680 case DP_TX_AUDIO_INFO_DATA(3):
681 case DP_TX_AUDIO_INFO_DATA(4):
682 case DP_TX_AUDIO_INFO_DATA(5):
683 case DP_TX_AUDIO_INFO_DATA(6):
684 case DP_TX_AUDIO_INFO_DATA(7):
685 case DP_TX_AUDIO_EXT_DATA(0):
686 case DP_TX_AUDIO_EXT_DATA(1):
687 case DP_TX_AUDIO_EXT_DATA(2):
688 case DP_TX_AUDIO_EXT_DATA(3):
689 case DP_TX_AUDIO_EXT_DATA(4):
690 case DP_TX_AUDIO_EXT_DATA(5):
691 case DP_TX_AUDIO_EXT_DATA(6):
692 case DP_TX_AUDIO_EXT_DATA(7):
693 case DP_TX_AUDIO_EXT_DATA(8):
694
695 ret = 0;
696 break;
697 default:
698 assert(offset <= (0x3AC >> 2));
699 ret = s->core_registers[offset];
700 break;
701 }
702
703 DPRINTF("core read @%" PRIx64 " = 0x%8.8" PRIX64 "\n", offset << 2, ret);
704 return ret;
705}
706
707static void xlnx_dp_write(void *opaque, hwaddr offset, uint64_t value,
708 unsigned size)
709{
710 XlnxDPState *s = XLNX_DP(opaque);
711
712 DPRINTF("core write @%" PRIx64 " = 0x%8.8" PRIX64 "\n", offset, value);
713
714 offset = offset >> 2;
715
716 switch (offset) {
717
718
719
720 case DP_LINK_BW_SET:
721 s->core_registers[offset] = value & 0x000000FF;
722 break;
723 case DP_LANE_COUNT_SET:
724 case DP_MAIN_STREAM_MISC0:
725 s->core_registers[offset] = value & 0x0000000F;
726 break;
727 case DP_TRAINING_PATTERN_SET:
728 case DP_LINK_QUAL_PATTERN_SET:
729 case DP_MAIN_STREAM_POLARITY:
730 case DP_PHY_VOLTAGE_DIFF_LANE_0:
731 case DP_PHY_VOLTAGE_DIFF_LANE_1:
732 s->core_registers[offset] = value & 0x00000003;
733 break;
734 case DP_ENHANCED_FRAME_EN:
735 case DP_SCRAMBLING_DISABLE:
736 case DP_DOWNSPREAD_CTRL:
737 case DP_MAIN_STREAM_ENABLE:
738 case DP_TRANSMIT_PRBS7:
739 s->core_registers[offset] = value & 0x00000001;
740 break;
741 case DP_PHY_CLOCK_SELECT:
742 s->core_registers[offset] = value & 0x00000007;
743 break;
744 case DP_SOFTWARE_RESET:
745
746
747
748
749
750
751 break;
752 case DP_TRANSMITTER_ENABLE:
753 s->core_registers[offset] = value & 0x01;
754 break;
755 case DP_FORCE_SCRAMBLER_RESET:
756
757
758
759
760
761
762 break;
763 case DP_AUX_COMMAND_REGISTER:
764 s->core_registers[offset] = value & 0x00001F0F;
765 xlnx_dp_aux_set_command(s, s->core_registers[offset]);
766 break;
767 case DP_MAIN_STREAM_HTOTAL:
768 case DP_MAIN_STREAM_VTOTAL:
769 case DP_MAIN_STREAM_HSTART:
770 case DP_MAIN_STREAM_VSTART:
771 s->core_registers[offset] = value & 0x0000FFFF;
772 break;
773 case DP_MAIN_STREAM_HRES:
774 case DP_MAIN_STREAM_VRES:
775 s->core_registers[offset] = value & 0x0000FFFF;
776 xlnx_dp_recreate_surface(s);
777 break;
778 case DP_MAIN_STREAM_HSWIDTH:
779 case DP_MAIN_STREAM_VSWIDTH:
780 s->core_registers[offset] = value & 0x00007FFF;
781 break;
782 case DP_MAIN_STREAM_MISC1:
783 s->core_registers[offset] = value & 0x00000086;
784 break;
785 case DP_MAIN_STREAM_M_VID:
786 case DP_MAIN_STREAM_N_VID:
787 s->core_registers[offset] = value & 0x00FFFFFF;
788 break;
789 case DP_MSA_TRANSFER_UNIT_SIZE:
790 case DP_MIN_BYTES_PER_TU:
791 case DP_INIT_WAIT:
792 s->core_registers[offset] = value & 0x00000007;
793 break;
794 case DP_USER_DATA_COUNT_PER_LANE:
795 s->core_registers[offset] = value & 0x0003FFFF;
796 break;
797 case DP_FRAC_BYTES_PER_TU:
798 s->core_registers[offset] = value & 0x000003FF;
799 break;
800 case DP_PHY_RESET:
801 s->core_registers[offset] = value & 0x00010003;
802
803
804
805 break;
806 case DP_TX_PHY_POWER_DOWN:
807 s->core_registers[offset] = value & 0x0000000F;
808
809
810
811 break;
812 case DP_AUX_WRITE_FIFO: {
813 uint8_t c = value;
814 xlnx_dp_aux_push_tx_fifo(s, &c, 1);
815 break;
816 }
817 case DP_AUX_CLOCK_DIVIDER:
818 break;
819 case DP_AUX_REPLY_COUNT:
820
821
822
823 s->core_registers[offset] = 0x00000000;
824 break;
825 case DP_AUX_ADDRESS:
826 s->core_registers[offset] = value & 0x000FFFFF;
827 break;
828 case DP_VERSION_REGISTER:
829 case DP_CORE_ID:
830 case DP_TX_USER_FIFO_OVERFLOW:
831 case DP_AUX_REPLY_DATA:
832 case DP_AUX_REPLY_CODE:
833 case DP_REPLY_DATA_COUNT:
834 case DP_REPLY_STATUS:
835 case DP_HPD_DURATION:
836
837
838
839 break;
840 case DP_TX_AUDIO_CONTROL:
841 s->core_registers[offset] = value & 0x00000001;
842 xlnx_dp_audio_activate(s);
843 break;
844 case DP_TX_AUDIO_CHANNELS:
845 s->core_registers[offset] = value & 0x00000007;
846 xlnx_dp_audio_activate(s);
847 break;
848 case DP_INT_STATUS:
849 s->core_registers[DP_INT_STATUS] &= ~value;
850 xlnx_dp_update_irq(s);
851 break;
852 case DP_INT_EN:
853 s->core_registers[DP_INT_MASK] &= ~value;
854 xlnx_dp_update_irq(s);
855 break;
856 case DP_INT_DS:
857 s->core_registers[DP_INT_MASK] |= ~value;
858 xlnx_dp_update_irq(s);
859 break;
860 default:
861 assert(offset <= (0x504C >> 2));
862 s->core_registers[offset] = value;
863 break;
864 }
865}
866
867static const MemoryRegionOps dp_ops = {
868 .read = xlnx_dp_read,
869 .write = xlnx_dp_write,
870 .endianness = DEVICE_NATIVE_ENDIAN,
871 .valid = {
872 .min_access_size = 4,
873 .max_access_size = 4,
874 },
875 .impl = {
876 .min_access_size = 4,
877 .max_access_size = 4,
878 },
879};
880
881
882
883
884static void xlnx_dp_vblend_write(void *opaque, hwaddr offset,
885 uint64_t value, unsigned size)
886{
887 XlnxDPState *s = XLNX_DP(opaque);
888 bool alpha_was_enabled;
889
890 DPRINTF("vblend: write @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n", offset,
891 (uint32_t)value);
892 offset = offset >> 2;
893
894 switch (offset) {
895 case V_BLEND_BG_CLR_0:
896 case V_BLEND_BG_CLR_1:
897 case V_BLEND_BG_CLR_2:
898 s->vblend_registers[offset] = value & 0x00000FFF;
899 break;
900 case V_BLEND_SET_GLOBAL_ALPHA_REG:
901
902
903
904
905 alpha_was_enabled = xlnx_dp_global_alpha_enabled(s);
906 s->vblend_registers[offset] = value & 0x000001FF;
907 if (xlnx_dp_global_alpha_enabled(s) != alpha_was_enabled) {
908 xlnx_dp_recreate_surface(s);
909 }
910 break;
911 case V_BLEND_OUTPUT_VID_FORMAT:
912 s->vblend_registers[offset] = value & 0x00000017;
913 break;
914 case V_BLEND_LAYER0_CONTROL:
915 case V_BLEND_LAYER1_CONTROL:
916 s->vblend_registers[offset] = value & 0x00000103;
917 break;
918 case V_BLEND_RGB2YCBCR_COEFF(0):
919 case V_BLEND_RGB2YCBCR_COEFF(1):
920 case V_BLEND_RGB2YCBCR_COEFF(2):
921 case V_BLEND_RGB2YCBCR_COEFF(3):
922 case V_BLEND_RGB2YCBCR_COEFF(4):
923 case V_BLEND_RGB2YCBCR_COEFF(5):
924 case V_BLEND_RGB2YCBCR_COEFF(6):
925 case V_BLEND_RGB2YCBCR_COEFF(7):
926 case V_BLEND_RGB2YCBCR_COEFF(8):
927 case V_BLEND_IN1CSC_COEFF(0):
928 case V_BLEND_IN1CSC_COEFF(1):
929 case V_BLEND_IN1CSC_COEFF(2):
930 case V_BLEND_IN1CSC_COEFF(3):
931 case V_BLEND_IN1CSC_COEFF(4):
932 case V_BLEND_IN1CSC_COEFF(5):
933 case V_BLEND_IN1CSC_COEFF(6):
934 case V_BLEND_IN1CSC_COEFF(7):
935 case V_BLEND_IN1CSC_COEFF(8):
936 case V_BLEND_IN2CSC_COEFF(0):
937 case V_BLEND_IN2CSC_COEFF(1):
938 case V_BLEND_IN2CSC_COEFF(2):
939 case V_BLEND_IN2CSC_COEFF(3):
940 case V_BLEND_IN2CSC_COEFF(4):
941 case V_BLEND_IN2CSC_COEFF(5):
942 case V_BLEND_IN2CSC_COEFF(6):
943 case V_BLEND_IN2CSC_COEFF(7):
944 case V_BLEND_IN2CSC_COEFF(8):
945 s->vblend_registers[offset] = value & 0x0000FFFF;
946 break;
947 case V_BLEND_LUMA_IN1CSC_OFFSET:
948 case V_BLEND_CR_IN1CSC_OFFSET:
949 case V_BLEND_CB_IN1CSC_OFFSET:
950 case V_BLEND_LUMA_IN2CSC_OFFSET:
951 case V_BLEND_CR_IN2CSC_OFFSET:
952 case V_BLEND_CB_IN2CSC_OFFSET:
953 case V_BLEND_LUMA_OUTCSC_OFFSET:
954 case V_BLEND_CR_OUTCSC_OFFSET:
955 case V_BLEND_CB_OUTCSC_OFFSET:
956 s->vblend_registers[offset] = value & 0x3FFF7FFF;
957 break;
958 case V_BLEND_CHROMA_KEY_ENABLE:
959 s->vblend_registers[offset] = value & 0x00000003;
960 break;
961 case V_BLEND_CHROMA_KEY_COMP1:
962 case V_BLEND_CHROMA_KEY_COMP2:
963 case V_BLEND_CHROMA_KEY_COMP3:
964 s->vblend_registers[offset] = value & 0x0FFF0FFF;
965 break;
966 default:
967 s->vblend_registers[offset] = value;
968 break;
969 }
970}
971
972static uint64_t xlnx_dp_vblend_read(void *opaque, hwaddr offset,
973 unsigned size)
974{
975 XlnxDPState *s = XLNX_DP(opaque);
976
977 DPRINTF("vblend: read @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n", offset,
978 s->vblend_registers[offset >> 2]);
979 return s->vblend_registers[offset >> 2];
980}
981
982static const MemoryRegionOps vblend_ops = {
983 .read = xlnx_dp_vblend_read,
984 .write = xlnx_dp_vblend_write,
985 .endianness = DEVICE_NATIVE_ENDIAN,
986 .valid = {
987 .min_access_size = 4,
988 .max_access_size = 4,
989 },
990 .impl = {
991 .min_access_size = 4,
992 .max_access_size = 4,
993 },
994};
995
996
997
998
999static void xlnx_dp_avbufm_write(void *opaque, hwaddr offset, uint64_t value,
1000 unsigned size)
1001{
1002 XlnxDPState *s = XLNX_DP(opaque);
1003
1004 DPRINTF("avbufm: write @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n", offset,
1005 (uint32_t)value);
1006 offset = offset >> 2;
1007
1008 switch (offset) {
1009 case AV_BUF_FORMAT:
1010 s->avbufm_registers[offset] = value & 0x00000FFF;
1011 xlnx_dp_change_graphic_fmt(s);
1012 break;
1013 case AV_CHBUF0:
1014 case AV_CHBUF1:
1015 case AV_CHBUF2:
1016 case AV_CHBUF3:
1017 case AV_CHBUF4:
1018 case AV_CHBUF5:
1019 s->avbufm_registers[offset] = value & 0x0000007F;
1020 break;
1021 case AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT:
1022 s->avbufm_registers[offset] = value & 0x0000007F;
1023 break;
1024 case AV_BUF_DITHER_CONFIG:
1025 s->avbufm_registers[offset] = value & 0x000007FF;
1026 break;
1027 case AV_BUF_DITHER_CONFIG_MAX:
1028 case AV_BUF_DITHER_CONFIG_MIN:
1029 s->avbufm_registers[offset] = value & 0x00000FFF;
1030 break;
1031 case AV_BUF_PATTERN_GEN_SELECT:
1032 s->avbufm_registers[offset] = value & 0xFFFFFF03;
1033 break;
1034 case AV_BUF_AUD_VID_CLK_SOURCE:
1035 s->avbufm_registers[offset] = value & 0x00000007;
1036 break;
1037 case AV_BUF_SRST_REG:
1038 s->avbufm_registers[offset] = value & 0x00000002;
1039 break;
1040 case AV_BUF_AUDIO_CH_CONFIG:
1041 s->avbufm_registers[offset] = value & 0x00000003;
1042 break;
1043 case AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(0):
1044 case AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(1):
1045 case AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(2):
1046 case AV_BUF_VIDEO_COMP_SCALE_FACTOR(0):
1047 case AV_BUF_VIDEO_COMP_SCALE_FACTOR(1):
1048 case AV_BUF_VIDEO_COMP_SCALE_FACTOR(2):
1049 s->avbufm_registers[offset] = value & 0x0000FFFF;
1050 break;
1051 case AV_BUF_LIVE_VIDEO_COMP_SF(0):
1052 case AV_BUF_LIVE_VIDEO_COMP_SF(1):
1053 case AV_BUF_LIVE_VIDEO_COMP_SF(2):
1054 case AV_BUF_LIVE_VID_CONFIG:
1055 case AV_BUF_LIVE_GFX_COMP_SF(0):
1056 case AV_BUF_LIVE_GFX_COMP_SF(1):
1057 case AV_BUF_LIVE_GFX_COMP_SF(2):
1058 case AV_BUF_LIVE_GFX_CONFIG:
1059 case AV_BUF_NON_LIVE_LATENCY:
1060 case AV_BUF_STC_CONTROL:
1061 case AV_BUF_STC_INIT_VALUE0:
1062 case AV_BUF_STC_INIT_VALUE1:
1063 case AV_BUF_STC_ADJ:
1064 case AV_BUF_STC_VIDEO_VSYNC_TS_REG0:
1065 case AV_BUF_STC_VIDEO_VSYNC_TS_REG1:
1066 case AV_BUF_STC_EXT_VSYNC_TS_REG0:
1067 case AV_BUF_STC_EXT_VSYNC_TS_REG1:
1068 case AV_BUF_STC_CUSTOM_EVENT_TS_REG0:
1069 case AV_BUF_STC_CUSTOM_EVENT_TS_REG1:
1070 case AV_BUF_STC_CUSTOM_EVENT2_TS_REG0:
1071 case AV_BUF_STC_CUSTOM_EVENT2_TS_REG1:
1072 case AV_BUF_STC_SNAPSHOT0:
1073 case AV_BUF_STC_SNAPSHOT1:
1074 case AV_BUF_HCOUNT_VCOUNT_INT0:
1075 case AV_BUF_HCOUNT_VCOUNT_INT1:
1076 qemu_log_mask(LOG_UNIMP, "avbufm: unimplmented");
1077 break;
1078 default:
1079 s->avbufm_registers[offset] = value;
1080 break;
1081 }
1082}
1083
1084static uint64_t xlnx_dp_avbufm_read(void *opaque, hwaddr offset,
1085 unsigned size)
1086{
1087 XlnxDPState *s = XLNX_DP(opaque);
1088
1089 offset = offset >> 2;
1090 return s->avbufm_registers[offset];
1091}
1092
1093static const MemoryRegionOps avbufm_ops = {
1094 .read = xlnx_dp_avbufm_read,
1095 .write = xlnx_dp_avbufm_write,
1096 .endianness = DEVICE_NATIVE_ENDIAN,
1097 .valid = {
1098 .min_access_size = 4,
1099 .max_access_size = 4,
1100 },
1101 .impl = {
1102 .min_access_size = 4,
1103 .max_access_size = 4,
1104 },
1105};
1106
1107
1108
1109
1110
1111
1112static inline void xlnx_dp_blend_surface(XlnxDPState *s)
1113{
1114 pixman_fixed_t alpha1[] = { pixman_double_to_fixed(1),
1115 pixman_double_to_fixed(1),
1116 pixman_double_to_fixed(1.0) };
1117 pixman_fixed_t alpha2[] = { pixman_double_to_fixed(1),
1118 pixman_double_to_fixed(1),
1119 pixman_double_to_fixed(1.0) };
1120
1121 if ((surface_width(s->g_plane.surface)
1122 != surface_width(s->v_plane.surface)) ||
1123 (surface_height(s->g_plane.surface)
1124 != surface_height(s->v_plane.surface))) {
1125 return;
1126 }
1127
1128 alpha1[2] = pixman_double_to_fixed((double)(xlnx_dp_global_alpha_value(s))
1129 / 256.0);
1130 alpha2[2] = pixman_double_to_fixed((255.0
1131 - (double)xlnx_dp_global_alpha_value(s))
1132 / 256.0);
1133
1134 pixman_image_set_filter(s->g_plane.surface->image,
1135 PIXMAN_FILTER_CONVOLUTION, alpha1, 3);
1136 pixman_image_composite(PIXMAN_OP_SRC, s->g_plane.surface->image, 0,
1137 s->bout_plane.surface->image, 0, 0, 0, 0, 0, 0,
1138 surface_width(s->g_plane.surface),
1139 surface_height(s->g_plane.surface));
1140 pixman_image_set_filter(s->v_plane.surface->image,
1141 PIXMAN_FILTER_CONVOLUTION, alpha2, 3);
1142 pixman_image_composite(PIXMAN_OP_ADD, s->v_plane.surface->image, 0,
1143 s->bout_plane.surface->image, 0, 0, 0, 0, 0, 0,
1144 surface_width(s->g_plane.surface),
1145 surface_height(s->g_plane.surface));
1146}
1147
1148static void xlnx_dp_update_display(void *opaque)
1149{
1150 XlnxDPState *s = XLNX_DP(opaque);
1151
1152 if ((s->core_registers[DP_TRANSMITTER_ENABLE] & 0x01) == 0) {
1153 return;
1154 }
1155
1156 s->core_registers[DP_INT_STATUS] |= (1 << 13);
1157 xlnx_dp_update_irq(s);
1158
1159 xlnx_dpdma_trigger_vsync_irq(s->dpdma);
1160
1161
1162
1163
1164 if (!xlnx_dpdma_start_operation(s->dpdma, 3, false)) {
1165
1166
1167
1168
1169 s->core_registers[DP_INT_STATUS] |= (1 << 21);
1170 xlnx_dp_update_irq(s);
1171 return;
1172 }
1173
1174 if (xlnx_dp_global_alpha_enabled(s)) {
1175 if (!xlnx_dpdma_start_operation(s->dpdma, 0, false)) {
1176 s->core_registers[DP_INT_STATUS] |= (1 << 21);
1177 xlnx_dp_update_irq(s);
1178 return;
1179 }
1180 xlnx_dp_blend_surface(s);
1181 }
1182
1183
1184
1185
1186 dpy_gfx_update(s->console, 0, 0, surface_width(s->g_plane.surface),
1187 surface_height(s->g_plane.surface));
1188}
1189
1190static const GraphicHwOps xlnx_dp_gfx_ops = {
1191 .gfx_update = xlnx_dp_update_display,
1192};
1193
1194static void xlnx_dp_init(Object *obj)
1195{
1196 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1197 XlnxDPState *s = XLNX_DP(obj);
1198
1199 memory_region_init(&s->container, obj, TYPE_XLNX_DP, 0xC050);
1200
1201 memory_region_init_io(&s->core_iomem, obj, &dp_ops, s, TYPE_XLNX_DP
1202 ".core", 0x3AF);
1203 memory_region_add_subregion(&s->container, 0x0000, &s->core_iomem);
1204
1205 memory_region_init_io(&s->vblend_iomem, obj, &vblend_ops, s, TYPE_XLNX_DP
1206 ".v_blend", 0x1DF);
1207 memory_region_add_subregion(&s->container, 0xA000, &s->vblend_iomem);
1208
1209 memory_region_init_io(&s->avbufm_iomem, obj, &avbufm_ops, s, TYPE_XLNX_DP
1210 ".av_buffer_manager", 0x238);
1211 memory_region_add_subregion(&s->container, 0xB000, &s->avbufm_iomem);
1212
1213 memory_region_init_io(&s->audio_iomem, obj, &audio_ops, s, TYPE_XLNX_DP
1214 ".audio", sizeof(s->audio_registers));
1215 memory_region_add_subregion(&s->container, 0xC000, &s->audio_iomem);
1216
1217 sysbus_init_mmio(sbd, &s->container);
1218 sysbus_init_irq(sbd, &s->irq);
1219
1220 object_property_add_link(obj, "dpdma", TYPE_XLNX_DPDMA,
1221 (Object **) &s->dpdma,
1222 xlnx_dp_set_dpdma,
1223 OBJ_PROP_LINK_UNREF_ON_RELEASE,
1224 &error_abort);
1225
1226
1227
1228
1229 s->aux_bus = aux_init_bus(DEVICE(obj), "aux");
1230
1231
1232
1233
1234 s->dpcd = DPCD(aux_create_slave(s->aux_bus, "dpcd", 0x00000));
1235 s->edid = I2CDDC(qdev_create(BUS(aux_get_i2c_bus(s->aux_bus)), "i2c-ddc"));
1236 i2c_set_slave_address(I2C_SLAVE(s->edid), 0x50);
1237
1238 fifo8_create(&s->rx_fifo, 16);
1239 fifo8_create(&s->tx_fifo, 16);
1240}
1241
1242static void xlnx_dp_realize(DeviceState *dev, Error **errp)
1243{
1244 XlnxDPState *s = XLNX_DP(dev);
1245 DisplaySurface *surface;
1246 struct audsettings as;
1247
1248 s->console = graphic_console_init(dev, 0, &xlnx_dp_gfx_ops, s);
1249 surface = qemu_console_surface(s->console);
1250 xlnx_dpdma_set_host_data_location(s->dpdma, DP_GRAPHIC_DMA_CHANNEL,
1251 surface_data(surface));
1252
1253 as.freq = 44100;
1254 as.nchannels = 2;
1255 as.fmt = AUD_FMT_S16;
1256 as.endianness = 0;
1257
1258 AUD_register_card("xlnx_dp.audio", &s->aud_card);
1259
1260 s->amixer_output_stream = AUD_open_out(&s->aud_card,
1261 s->amixer_output_stream,
1262 "xlnx_dp.audio.out",
1263 s,
1264 xlnx_dp_audio_callback,
1265 &as);
1266 AUD_set_volume_out(s->amixer_output_stream, 0, 255, 255);
1267 xlnx_dp_audio_activate(s);
1268}
1269
1270static void xlnx_dp_reset(DeviceState *dev)
1271{
1272 XlnxDPState *s = XLNX_DP(dev);
1273
1274 memset(s->core_registers, 0, sizeof(s->core_registers));
1275 s->core_registers[DP_VERSION_REGISTER] = 0x04010000;
1276 s->core_registers[DP_CORE_ID] = 0x01020000;
1277 s->core_registers[DP_REPLY_STATUS] = 0x00000010;
1278 s->core_registers[DP_MSA_TRANSFER_UNIT_SIZE] = 0x00000040;
1279 s->core_registers[DP_INIT_WAIT] = 0x00000020;
1280 s->core_registers[DP_PHY_RESET] = 0x00010003;
1281 s->core_registers[DP_INT_MASK] = 0xFFFFF03F;
1282 s->core_registers[DP_PHY_STATUS] = 0x00000043;
1283 s->core_registers[DP_INTERRUPT_SIGNAL_STATE] = 0x00000001;
1284
1285 s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF(0)] = 0x00001000;
1286 s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF(4)] = 0x00001000;
1287 s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF(8)] = 0x00001000;
1288 s->vblend_registers[V_BLEND_IN1CSC_COEFF(0)] = 0x00001000;
1289 s->vblend_registers[V_BLEND_IN1CSC_COEFF(4)] = 0x00001000;
1290 s->vblend_registers[V_BLEND_IN1CSC_COEFF(8)] = 0x00001000;
1291 s->vblend_registers[V_BLEND_IN2CSC_COEFF(0)] = 0x00001000;
1292 s->vblend_registers[V_BLEND_IN2CSC_COEFF(4)] = 0x00001000;
1293 s->vblend_registers[V_BLEND_IN2CSC_COEFF(8)] = 0x00001000;
1294
1295 s->avbufm_registers[AV_BUF_NON_LIVE_LATENCY] = 0x00000180;
1296 s->avbufm_registers[AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT] = 0x00000008;
1297 s->avbufm_registers[AV_BUF_DITHER_CONFIG_MAX] = 0x00000FFF;
1298 s->avbufm_registers[AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(0)] = 0x00010101;
1299 s->avbufm_registers[AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(1)] = 0x00010101;
1300 s->avbufm_registers[AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(2)] = 0x00010101;
1301 s->avbufm_registers[AV_BUF_VIDEO_COMP_SCALE_FACTOR(0)] = 0x00010101;
1302 s->avbufm_registers[AV_BUF_VIDEO_COMP_SCALE_FACTOR(1)] = 0x00010101;
1303 s->avbufm_registers[AV_BUF_VIDEO_COMP_SCALE_FACTOR(2)] = 0x00010101;
1304 s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP_SF(0)] = 0x00010101;
1305 s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP_SF(1)] = 0x00010101;
1306 s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP_SF(2)] = 0x00010101;
1307 s->avbufm_registers[AV_BUF_LIVE_GFX_COMP_SF(0)] = 0x00010101;
1308 s->avbufm_registers[AV_BUF_LIVE_GFX_COMP_SF(1)] = 0x00010101;
1309 s->avbufm_registers[AV_BUF_LIVE_GFX_COMP_SF(2)] = 0x00010101;
1310
1311 memset(s->audio_registers, 0, sizeof(s->audio_registers));
1312 s->byte_left = 0;
1313
1314 xlnx_dp_aux_clear_rx_fifo(s);
1315 xlnx_dp_change_graphic_fmt(s);
1316 xlnx_dp_update_irq(s);
1317}
1318
1319static void xlnx_dp_class_init(ObjectClass *oc, void *data)
1320{
1321 DeviceClass *dc = DEVICE_CLASS(oc);
1322
1323 dc->realize = xlnx_dp_realize;
1324 dc->vmsd = &vmstate_dp;
1325 dc->reset = xlnx_dp_reset;
1326}
1327
1328static const TypeInfo xlnx_dp_info = {
1329 .name = TYPE_XLNX_DP,
1330 .parent = TYPE_SYS_BUS_DEVICE,
1331 .instance_size = sizeof(XlnxDPState),
1332 .instance_init = xlnx_dp_init,
1333 .class_init = xlnx_dp_class_init,
1334};
1335
1336static void xlnx_dp_register_types(void)
1337{
1338 type_register_static(&xlnx_dp_info);
1339}
1340
1341type_init(xlnx_dp_register_types)
1342
