LXR qemu/hw/ide/ahci

   1/*
   2 * QEMU AHCI Emulation
   3 *
   4 * Copyright (c) 2010 qiaochong@loongson.cn
   5 * Copyright (c) 2010 Roland Elek <elek.roland@gmail.com>
   6 * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de>
   7 * Copyright (c) 2010 Alexander Graf <agraf@suse.de>
   8 *
   9 * This library is free software; you can redistribute it and/or
  10 * modify it under the terms of the GNU Lesser General Public
  11 * License as published by the Free Software Foundation; either
  12 * version 2 of the License, or (at your option) any later version.
  13 *
  14 * This library is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17 * Lesser General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU Lesser General Public
  20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21 *
  22 */
  23
  24#ifndef HW_IDE_AHCI_INTERNAL_H
  25#define HW_IDE_AHCI_INTERNAL_H
  26
  27#include "hw/ide/ahci.h"
  28#include "hw/sysbus.h"
  29
  30#define AHCI_MEM_BAR_SIZE         0x1000
  31#define AHCI_MAX_PORTS            32
  32#define AHCI_MAX_SG               168 /* hardware max is 64K */
  33#define AHCI_DMA_BOUNDARY         0xffffffff
  34#define AHCI_USE_CLUSTERING       0
  35#define AHCI_MAX_CMDS             32
  36#define AHCI_CMD_SZ               32
  37#define AHCI_CMD_SLOT_SZ          (AHCI_MAX_CMDS * AHCI_CMD_SZ)
  38#define AHCI_RX_FIS_SZ            256
  39#define AHCI_CMD_TBL_CDB          0x40
  40#define AHCI_CMD_TBL_HDR_SZ       0x80
  41#define AHCI_CMD_TBL_SZ           (AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16))
  42#define AHCI_CMD_TBL_AR_SZ        (AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS)
  43#define AHCI_PORT_PRIV_DMA_SZ     (AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + \
  44                                   AHCI_RX_FIS_SZ)
  45
  46#define AHCI_IRQ_ON_SG            (1U << 31)
  47#define AHCI_CMD_ATAPI            (1 << 5)
  48#define AHCI_CMD_WRITE            (1 << 6)
  49#define AHCI_CMD_PREFETCH         (1 << 7)
  50#define AHCI_CMD_RESET            (1 << 8)
  51#define AHCI_CMD_CLR_BUSY         (1 << 10)
  52
  53#define RX_FIS_D2H_REG            0x40 /* offset of D2H Register FIS data */
  54#define RX_FIS_SDB                0x58 /* offset of SDB FIS data */
  55#define RX_FIS_UNK                0x60 /* offset of Unknown FIS data */
  56
  57/* global controller registers */
  58#define HOST_CAP                  0x00 /* host capabilities */
  59#define HOST_CTL                  0x04 /* global host control */
  60#define HOST_IRQ_STAT             0x08 /* interrupt status */
  61#define HOST_PORTS_IMPL           0x0c /* bitmap of implemented ports */
  62#define HOST_VERSION              0x10 /* AHCI spec. version compliancy */
  63
  64/* HOST_CTL bits */
  65#define HOST_CTL_RESET            (1 << 0)  /* reset controller; self-clear */
  66#define HOST_CTL_IRQ_EN           (1 << 1)  /* global IRQ enable */
  67#define HOST_CTL_AHCI_EN          (1U << 31) /* AHCI enabled */
  68
  69/* HOST_CAP bits */
  70#define HOST_CAP_SSC              (1 << 14) /* Slumber capable */
  71#define HOST_CAP_AHCI             (1 << 18) /* AHCI only */
  72#define HOST_CAP_CLO              (1 << 24) /* Command List Override support */
  73#define HOST_CAP_SSS              (1 << 27) /* Staggered Spin-up */
  74#define HOST_CAP_NCQ              (1 << 30) /* Native Command Queueing */
  75#define HOST_CAP_64               (1U << 31) /* PCI DAC (64-bit DMA) support */
  76
  77/* registers for each SATA port */
  78#define PORT_LST_ADDR             0x00 /* command list DMA addr */
  79#define PORT_LST_ADDR_HI          0x04 /* command list DMA addr hi */
  80#define PORT_FIS_ADDR             0x08 /* FIS rx buf addr */
  81#define PORT_FIS_ADDR_HI          0x0c /* FIS rx buf addr hi */
  82#define PORT_IRQ_STAT             0x10 /* interrupt status */
  83#define PORT_IRQ_MASK             0x14 /* interrupt enable/disable mask */
  84#define PORT_CMD                  0x18 /* port command */
  85#define PORT_TFDATA               0x20 /* taskfile data */
  86#define PORT_SIG                  0x24 /* device TF signature */
  87#define PORT_SCR_STAT             0x28 /* SATA phy register: SStatus */
  88#define PORT_SCR_CTL              0x2c /* SATA phy register: SControl */
  89#define PORT_SCR_ERR              0x30 /* SATA phy register: SError */
  90#define PORT_SCR_ACT              0x34 /* SATA phy register: SActive */
  91#define PORT_CMD_ISSUE            0x38 /* command issue */
  92#define PORT_RESERVED             0x3c /* reserved */
  93
  94/* PORT_IRQ_{STAT,MASK} bits */
  95#define PORT_IRQ_COLD_PRES        (1U << 31) /* cold presence detect */
  96#define PORT_IRQ_TF_ERR           (1 << 30) /* task file error */
  97#define PORT_IRQ_HBUS_ERR         (1 << 29) /* host bus fatal error */
  98#define PORT_IRQ_HBUS_DATA_ERR    (1 << 28) /* host bus data error */
  99#define PORT_IRQ_IF_ERR           (1 << 27) /* interface fatal error */
 100#define PORT_IRQ_IF_NONFATAL      (1 << 26) /* interface non-fatal error */
 101#define PORT_IRQ_OVERFLOW         (1 << 24) /* xfer exhausted available S/G */
 102#define PORT_IRQ_BAD_PMP          (1 << 23) /* incorrect port multiplier */
 103
 104#define PORT_IRQ_PHYRDY           (1 << 22) /* PhyRdy changed */
 105#define PORT_IRQ_DEV_ILCK         (1 << 7) /* device interlock */
 106#define PORT_IRQ_CONNECT          (1 << 6) /* port connect change status */
 107#define PORT_IRQ_SG_DONE          (1 << 5) /* descriptor processed */
 108#define PORT_IRQ_UNK_FIS          (1 << 4) /* unknown FIS rx'd */
 109#define PORT_IRQ_SDB_FIS          (1 << 3) /* Set Device Bits FIS rx'd */
 110#define PORT_IRQ_DMAS_FIS         (1 << 2) /* DMA Setup FIS rx'd */
 111#define PORT_IRQ_PIOS_FIS         (1 << 1) /* PIO Setup FIS rx'd */
 112#define PORT_IRQ_D2H_REG_FIS      (1 << 0) /* D2H Register FIS rx'd */
 113
 114#define PORT_IRQ_FREEZE           (PORT_IRQ_HBUS_ERR | PORT_IRQ_IF_ERR |   \
 115                                   PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY |    \
 116                                   PORT_IRQ_UNK_FIS)
 117#define PORT_IRQ_ERROR            (PORT_IRQ_FREEZE | PORT_IRQ_TF_ERR |     \
 118                                   PORT_IRQ_HBUS_DATA_ERR)
 119#define DEF_PORT_IRQ              (PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |     \
 120                                   PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |  \
 121                                   PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS)
 122
 123/* PORT_CMD bits */
 124#define PORT_CMD_ATAPI            (1 << 24) /* Device is ATAPI */
 125#define PORT_CMD_LIST_ON          (1 << 15) /* cmd list DMA engine running */
 126#define PORT_CMD_FIS_ON           (1 << 14) /* FIS DMA engine running */
 127#define PORT_CMD_FIS_RX           (1 << 4) /* Enable FIS receive DMA engine */
 128#define PORT_CMD_CLO              (1 << 3) /* Command list override */
 129#define PORT_CMD_POWER_ON         (1 << 2) /* Power up device */
 130#define PORT_CMD_SPIN_UP          (1 << 1) /* Spin up device */
 131#define PORT_CMD_START            (1 << 0) /* Enable port DMA engine */
 132
 133#define PORT_CMD_ICC_MASK        (0xfU << 28) /* i/f ICC state mask */
 134#define PORT_CMD_ICC_ACTIVE       (0x1 << 28) /* Put i/f in active state */
 135#define PORT_CMD_ICC_PARTIAL      (0x2 << 28) /* Put i/f in partial state */
 136#define PORT_CMD_ICC_SLUMBER      (0x6 << 28) /* Put i/f in slumber state */
 137
 138#define PORT_CMD_RO_MASK          0x007dffe0 /* Which CMD bits are read only? */
 139
 140/* ap->flags bits */
 141#define AHCI_FLAG_NO_NCQ                  (1 << 24)
 142#define AHCI_FLAG_IGN_IRQ_IF_ERR          (1 << 25) /* ignore IRQ_IF_ERR */
 143#define AHCI_FLAG_HONOR_PI                (1 << 26) /* honor PORTS_IMPL */
 144#define AHCI_FLAG_IGN_SERR_INTERNAL       (1 << 27) /* ignore SERR_INTERNAL */
 145#define AHCI_FLAG_32BIT_ONLY              (1 << 28) /* force 32bit */
 146
 147#define ATA_SRST                          (1 << 2)  /* software reset */
 148
 149#define STATE_RUN                         0
 150#define STATE_RESET                       1
 151
 152#define SATA_SCR_SSTATUS_DET_NODEV        0x0
 153#define SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP 0x3
 154
 155#define SATA_SCR_SSTATUS_SPD_NODEV        0x00
 156#define SATA_SCR_SSTATUS_SPD_GEN1         0x10
 157
 158#define SATA_SCR_SSTATUS_IPM_NODEV        0x000
 159#define SATA_SCR_SSTATUS_IPM_ACTIVE       0X100
 160
 161#define AHCI_SCR_SCTL_DET                 0xf
 162
 163#define SATA_FIS_TYPE_REGISTER_H2D        0x27
 164#define   SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER 0x80
 165#define SATA_FIS_TYPE_REGISTER_D2H        0x34
 166#define SATA_FIS_TYPE_PIO_SETUP           0x5f
 167#define SATA_FIS_TYPE_SDB                 0xA1
 168
 169#define AHCI_CMD_HDR_CMD_FIS_LEN           0x1f
 170#define AHCI_CMD_HDR_PRDT_LEN              16
 171
 172#define SATA_SIGNATURE_CDROM               0xeb140101
 173#define SATA_SIGNATURE_DISK                0x00000101
 174
 175#define AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR 0x20
 176                                            /* Shouldn't this be 0x2c? */
 177
 178#define AHCI_PORT_REGS_START_ADDR          0x100
 179#define AHCI_PORT_ADDR_OFFSET_MASK         0x7f
 180#define AHCI_PORT_ADDR_OFFSET_LEN          0x80
 181
 182#define AHCI_NUM_COMMAND_SLOTS             31
 183#define AHCI_SUPPORTED_SPEED               20
 184#define AHCI_SUPPORTED_SPEED_GEN1          1
 185#define AHCI_VERSION_1_0                   0x10000
 186
 187#define AHCI_PROGMODE_MAJOR_REV_1          1
 188
 189#define AHCI_COMMAND_TABLE_ACMD            0x40
 190
 191#define AHCI_PRDT_SIZE_MASK                0x3fffff
 192
 193#define IDE_FEATURE_DMA                    1
 194
 195#define READ_FPDMA_QUEUED                  0x60
 196#define WRITE_FPDMA_QUEUED                 0x61
 197#define NCQ_NON_DATA                       0x63
 198#define RECEIVE_FPDMA_QUEUED               0x65
 199#define SEND_FPDMA_QUEUED                  0x64
 200
 201#define NCQ_FIS_FUA_MASK                   0x80
 202#define NCQ_FIS_RARC_MASK                  0x01
 203
 204#define RES_FIS_DSFIS                      0x00
 205#define RES_FIS_PSFIS                      0x20
 206#define RES_FIS_RFIS                       0x40
 207#define RES_FIS_SDBFIS                     0x58
 208#define RES_FIS_UFIS                       0x60
 209
 210#define SATA_CAP_SIZE           0x8
 211#define SATA_CAP_REV            0x2
 212#define SATA_CAP_BAR            0x4
 213
 214typedef struct AHCIPortRegs {
 215    uint32_t    lst_addr;
 216    uint32_t    lst_addr_hi;
 217    uint32_t    fis_addr;
 218    uint32_t    fis_addr_hi;
 219    uint32_t    irq_stat;
 220    uint32_t    irq_mask;
 221    uint32_t    cmd;
 222    uint32_t    unused0;
 223    uint32_t    tfdata;
 224    uint32_t    sig;
 225    uint32_t    scr_stat;
 226    uint32_t    scr_ctl;
 227    uint32_t    scr_err;
 228    uint32_t    scr_act;
 229    uint32_t    cmd_issue;
 230    uint32_t    reserved;
 231} AHCIPortRegs;
 232
 233typedef struct AHCICmdHdr {
 234    uint16_t    opts;
 235    uint16_t    prdtl;
 236    uint32_t    status;
 237    uint64_t    tbl_addr;
 238    uint32_t    reserved[4];
 239} QEMU_PACKED AHCICmdHdr;
 240
 241typedef struct AHCI_SG {
 242    uint64_t    addr;
 243    uint32_t    reserved;
 244    uint32_t    flags_size;
 245} QEMU_PACKED AHCI_SG;
 246
 247typedef struct NCQTransferState {
 248    AHCIDevice *drive;
 249    BlockAIOCB *aiocb;
 250    AHCICmdHdr *cmdh;
 251    QEMUSGList sglist;
 252    BlockAcctCookie acct;
 253    uint32_t sector_count;
 254    uint64_t lba;
 255    uint8_t tag;
 256    uint8_t cmd;
 257    uint8_t slot;
 258    bool used;
 259    bool halt;
 260} NCQTransferState;
 261
 262struct AHCIDevice {
 263    IDEDMA dma;
 264    IDEBus port;
 265    int port_no;
 266    uint32_t port_state;
 267    uint32_t finished;
 268    AHCIPortRegs port_regs;
 269    struct AHCIState *hba;
 270    QEMUBH *check_bh;
 271    uint8_t *lst;
 272    uint8_t *res_fis;
 273    bool done_atapi_packet;
 274    int32_t busy_slot;
 275    bool init_d2h_sent;
 276    AHCICmdHdr *cur_cmd;
 277    NCQTransferState ncq_tfs[AHCI_MAX_CMDS];
 278};
 279
 280struct AHCIPCIState {
 281    /*< private >*/
 282    PCIDevice parent_obj;
 283    /*< public >*/
 284
 285    AHCIState ahci;
 286};
 287
 288#define TYPE_ICH9_AHCI "ich9-ahci"
 289
 290#define ICH_AHCI(obj) \
 291    OBJECT_CHECK(AHCIPCIState, (obj), TYPE_ICH9_AHCI)
 292
 293extern const VMStateDescription vmstate_ahci;
 294
 295#define VMSTATE_AHCI(_field, _state) {                               \
 296    .name       = (stringify(_field)),                               \
 297    .size       = sizeof(AHCIState),                                 \
 298    .vmsd       = &vmstate_ahci,                                     \
 299    .flags      = VMS_STRUCT,                                        \
 300    .offset     = vmstate_offset_value(_state, _field, AHCIState),   \
 301}
 302
 303/**
 304 * NCQFrame is the same as a Register H2D FIS (described in SATA 3.2),
 305 * but some fields have been re-mapped and re-purposed, as seen in
 306 * SATA 3.2 section 13.6.4.1 ("READ FPDMA QUEUED")
 307 *
 308 * cmd_fis[3], feature 7:0, becomes sector count 7:0.
 309 * cmd_fis[7], device 7:0, uses bit 7 as the Force Unit Access bit.
 310 * cmd_fis[11], feature 15:8, becomes sector count 15:8.
 311 * cmd_fis[12], count 7:0, becomes the NCQ TAG (7:3) and RARC bit (0)
 312 * cmd_fis[13], count 15:8, becomes the priority value (7:6)
 313 * bytes 16-19 become an le32 "auxiliary" field.
 314 */
 315typedef struct NCQFrame {
 316    uint8_t fis_type;
 317    uint8_t c;
 318    uint8_t command;
 319    uint8_t sector_count_low;  /* (feature 7:0) */
 320    uint8_t lba0;
 321    uint8_t lba1;
 322    uint8_t lba2;
 323    uint8_t fua;               /* (device 7:0) */
 324    uint8_t lba3;
 325    uint8_t lba4;
 326    uint8_t lba5;
 327    uint8_t sector_count_high; /* (feature 15:8) */
 328    uint8_t tag;               /* (count 0:7) */
 329    uint8_t prio;              /* (count 15:8) */
 330    uint8_t icc;
 331    uint8_t control;
 332    uint8_t aux0;
 333    uint8_t aux1;
 334    uint8_t aux2;
 335    uint8_t aux3;
 336} QEMU_PACKED NCQFrame;
 337
 338typedef struct SDBFIS {
 339    uint8_t type;
 340    uint8_t flags;
 341    uint8_t status;
 342    uint8_t error;
 343    uint32_t payload;
 344} QEMU_PACKED SDBFIS;
 345
 346void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports);
 347void ahci_init(AHCIState *s, DeviceState *qdev);
 348void ahci_uninit(AHCIState *s);
 349
 350void ahci_reset(AHCIState *s);
 351
 352#define TYPE_SYSBUS_AHCI "sysbus-ahci"
 353#define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_AHCI)
 354
 355#define TYPE_ALLWINNER_AHCI "allwinner-ahci"
 356#define ALLWINNER_AHCI(obj) OBJECT_CHECK(AllwinnerAHCIState, (obj), \
 357                       TYPE_ALLWINNER_AHCI)
 358
 359#endif /* HW_IDE_AHCI_H */
 360