qemu/hw/intc/arm_gicv3_its_common.c
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   1/*
   2 * ITS base class for a GICv3-based system
   3 *
   4 * Copyright (c) 2015 Samsung Electronics Co., Ltd.
   5 * Written by Pavel Fedin
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License as published by
   9 * the Free Software Foundation, either version 2 of the License, or
  10 * (at your option) any later version.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License along
  18 * with this program; if not, see <http://www.gnu.org/licenses/>.
  19 */
  20
  21#include "qemu/osdep.h"
  22#include "hw/pci/msi.h"
  23#include "hw/intc/arm_gicv3_its_common.h"
  24#include "qemu/log.h"
  25
  26static void gicv3_its_pre_save(void *opaque)
  27{
  28    GICv3ITSState *s = (GICv3ITSState *)opaque;
  29    GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s);
  30
  31    if (c->pre_save) {
  32        c->pre_save(s);
  33    }
  34}
  35
  36static int gicv3_its_post_load(void *opaque, int version_id)
  37{
  38    GICv3ITSState *s = (GICv3ITSState *)opaque;
  39    GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s);
  40
  41    if (c->post_load) {
  42        c->post_load(s);
  43    }
  44    return 0;
  45}
  46
  47static const VMStateDescription vmstate_its = {
  48    .name = "arm_gicv3_its",
  49    .pre_save = gicv3_its_pre_save,
  50    .post_load = gicv3_its_post_load,
  51    .priority = MIG_PRI_GICV3_ITS,
  52    .fields = (VMStateField[]) {
  53        VMSTATE_UINT32(ctlr, GICv3ITSState),
  54        VMSTATE_UINT32(iidr, GICv3ITSState),
  55        VMSTATE_UINT64(cbaser, GICv3ITSState),
  56        VMSTATE_UINT64(cwriter, GICv3ITSState),
  57        VMSTATE_UINT64(creadr, GICv3ITSState),
  58        VMSTATE_UINT64_ARRAY(baser, GICv3ITSState, 8),
  59        VMSTATE_END_OF_LIST()
  60    },
  61};
  62
  63static MemTxResult gicv3_its_trans_read(void *opaque, hwaddr offset,
  64                                        uint64_t *data, unsigned size,
  65                                        MemTxAttrs attrs)
  66{
  67    qemu_log_mask(LOG_GUEST_ERROR, "ITS read at offset 0x%"PRIx64"\n", offset);
  68    return MEMTX_ERROR;
  69}
  70
  71static MemTxResult gicv3_its_trans_write(void *opaque, hwaddr offset,
  72                                         uint64_t value, unsigned size,
  73                                         MemTxAttrs attrs)
  74{
  75    if (offset == 0x0040 && ((size == 2) || (size == 4))) {
  76        GICv3ITSState *s = ARM_GICV3_ITS_COMMON(opaque);
  77        GICv3ITSCommonClass *c = ARM_GICV3_ITS_COMMON_GET_CLASS(s);
  78        int ret = c->send_msi(s, le64_to_cpu(value), attrs.requester_id);
  79
  80        if (ret <= 0) {
  81            qemu_log_mask(LOG_GUEST_ERROR,
  82                          "ITS: Error sending MSI: %s\n", strerror(-ret));
  83            return MEMTX_DECODE_ERROR;
  84        }
  85
  86        return MEMTX_OK;
  87    } else {
  88        qemu_log_mask(LOG_GUEST_ERROR,
  89                      "ITS write at bad offset 0x%"PRIx64"\n", offset);
  90        return MEMTX_DECODE_ERROR;
  91    }
  92}
  93
  94static const MemoryRegionOps gicv3_its_trans_ops = {
  95    .read_with_attrs = gicv3_its_trans_read,
  96    .write_with_attrs = gicv3_its_trans_write,
  97    .endianness = DEVICE_NATIVE_ENDIAN,
  98};
  99
 100void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops)
 101{
 102    SysBusDevice *sbd = SYS_BUS_DEVICE(s);
 103
 104    memory_region_init_io(&s->iomem_its_cntrl, OBJECT(s), ops, s,
 105                          "control", ITS_CONTROL_SIZE);
 106    memory_region_init_io(&s->iomem_its_translation, OBJECT(s),
 107                          &gicv3_its_trans_ops, s,
 108                          "translation", ITS_TRANS_SIZE);
 109
 110    /* Our two regions are always adjacent, therefore we now combine them
 111     * into a single one in order to make our users' life easier.
 112     */
 113    memory_region_init(&s->iomem_main, OBJECT(s), "gicv3_its", ITS_SIZE);
 114    memory_region_add_subregion(&s->iomem_main, 0, &s->iomem_its_cntrl);
 115    memory_region_add_subregion(&s->iomem_main, ITS_CONTROL_SIZE,
 116                                &s->iomem_its_translation);
 117    sysbus_init_mmio(sbd, &s->iomem_main);
 118
 119    msi_nonbroken = true;
 120}
 121
 122static void gicv3_its_common_reset(DeviceState *dev)
 123{
 124    GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
 125
 126    s->ctlr = 0;
 127    s->cbaser = 0;
 128    s->cwriter = 0;
 129    s->creadr = 0;
 130    s->iidr = 0;
 131    memset(&s->baser, 0, sizeof(s->baser));
 132
 133    gicv3_its_post_load(s, 0);
 134}
 135
 136static void gicv3_its_common_class_init(ObjectClass *klass, void *data)
 137{
 138    DeviceClass *dc = DEVICE_CLASS(klass);
 139
 140    dc->reset = gicv3_its_common_reset;
 141    dc->vmsd = &vmstate_its;
 142}
 143
 144static const TypeInfo gicv3_its_common_info = {
 145    .name = TYPE_ARM_GICV3_ITS_COMMON,
 146    .parent = TYPE_SYS_BUS_DEVICE,
 147    .instance_size = sizeof(GICv3ITSState),
 148    .class_size = sizeof(GICv3ITSCommonClass),
 149    .class_init = gicv3_its_common_class_init,
 150    .abstract = true,
 151};
 152
 153static void gicv3_its_common_register_types(void)
 154{
 155    type_register_static(&gicv3_its_common_info);
 156}
 157
 158type_init(gicv3_its_common_register_types)
 159