1
2
3
4
5
6
7
8
9
10
11
12
13#include "qemu/osdep.h"
14#include "qapi/error.h"
15#include "qemu-common.h"
16#include "cpu.h"
17#include "hw/sysbus.h"
18#include "qemu/timer.h"
19#include "hw/arm/arm.h"
20#include "hw/arm/armv7m_nvic.h"
21#include "target/arm/cpu.h"
22#include "exec/exec-all.h"
23#include "qemu/log.h"
24#include "trace.h"
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50#define NVIC_FIRST_IRQ 16
51#define NVIC_MAX_IRQ (NVIC_MAX_VECTORS - NVIC_FIRST_IRQ)
52
53
54
55
56#define NVIC_NOEXC_PRIO 0x100
57
58static const uint8_t nvic_id[] = {
59 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
60};
61
62static int nvic_pending_prio(NVICState *s)
63{
64
65
66
67 return s->vectpending ? s->vectors[s->vectpending].prio : NVIC_NOEXC_PRIO;
68}
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84static bool nvic_rettobase(NVICState *s)
85{
86 int irq, nhand = 0;
87
88 for (irq = ARMV7M_EXCP_RESET; irq < s->num_irq; irq++) {
89 if (s->vectors[irq].active) {
90 nhand++;
91 if (nhand == 2) {
92 return 0;
93 }
94 }
95 }
96
97 return 1;
98}
99
100
101
102
103
104static bool nvic_isrpending(NVICState *s)
105{
106 int irq;
107
108
109
110
111 if (s->vectpending > NVIC_FIRST_IRQ) {
112 return true;
113 }
114 if (s->vectpending == 0) {
115 return false;
116 }
117
118 for (irq = NVIC_FIRST_IRQ; irq < s->num_irq; irq++) {
119 if (s->vectors[irq].pending) {
120 return true;
121 }
122 }
123 return false;
124}
125
126
127
128
129
130static inline uint32_t nvic_gprio_mask(NVICState *s)
131{
132 return ~0U << (s->prigroup + 1);
133}
134
135
136static void nvic_recompute_state(NVICState *s)
137{
138 int i;
139 int pend_prio = NVIC_NOEXC_PRIO;
140 int active_prio = NVIC_NOEXC_PRIO;
141 int pend_irq = 0;
142
143 for (i = 1; i < s->num_irq; i++) {
144 VecInfo *vec = &s->vectors[i];
145
146 if (vec->enabled && vec->pending && vec->prio < pend_prio) {
147 pend_prio = vec->prio;
148 pend_irq = i;
149 }
150 if (vec->active && vec->prio < active_prio) {
151 active_prio = vec->prio;
152 }
153 }
154
155 s->vectpending = pend_irq;
156 s->exception_prio = active_prio & nvic_gprio_mask(s);
157
158 trace_nvic_recompute_state(s->vectpending, s->exception_prio);
159}
160
161
162
163
164
165static inline int nvic_exec_prio(NVICState *s)
166{
167 CPUARMState *env = &s->cpu->env;
168 int running;
169
170 if (env->daif & PSTATE_F) {
171 running = -1;
172 } else if (env->daif & PSTATE_I) {
173 running = 0;
174 } else if (env->v7m.basepri > 0) {
175 running = env->v7m.basepri & nvic_gprio_mask(s);
176 } else {
177 running = NVIC_NOEXC_PRIO;
178 }
179
180 return MIN(running, s->exception_prio);
181}
182
183bool armv7m_nvic_can_take_pending_exception(void *opaque)
184{
185 NVICState *s = opaque;
186
187 return nvic_exec_prio(s) > nvic_pending_prio(s);
188}
189
190
191static void set_prio(NVICState *s, unsigned irq, uint8_t prio)
192{
193 assert(irq > ARMV7M_EXCP_NMI);
194 assert(irq < s->num_irq);
195
196 s->vectors[irq].prio = prio;
197
198 trace_nvic_set_prio(irq, prio);
199}
200
201
202
203
204
205
206static void nvic_irq_update(NVICState *s)
207{
208 int lvl;
209 int pend_prio;
210
211 nvic_recompute_state(s);
212 pend_prio = nvic_pending_prio(s);
213
214
215
216
217
218
219
220 lvl = (pend_prio < s->exception_prio);
221 trace_nvic_irq_update(s->vectpending, pend_prio, s->exception_prio, lvl);
222 qemu_set_irq(s->excpout, lvl);
223}
224
225static void armv7m_nvic_clear_pending(void *opaque, int irq)
226{
227 NVICState *s = (NVICState *)opaque;
228 VecInfo *vec;
229
230 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
231
232 vec = &s->vectors[irq];
233 trace_nvic_clear_pending(irq, vec->enabled, vec->prio);
234 if (vec->pending) {
235 vec->pending = 0;
236 nvic_irq_update(s);
237 }
238}
239
240void armv7m_nvic_set_pending(void *opaque, int irq)
241{
242 NVICState *s = (NVICState *)opaque;
243 VecInfo *vec;
244
245 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
246
247 vec = &s->vectors[irq];
248 trace_nvic_set_pending(irq, vec->enabled, vec->prio);
249
250
251 if (irq >= ARMV7M_EXCP_HARD && irq < ARMV7M_EXCP_PENDSV) {
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272 int running = nvic_exec_prio(s);
273 bool escalate = false;
274
275 if (vec->prio >= running) {
276 trace_nvic_escalate_prio(irq, vec->prio, running);
277 escalate = true;
278 } else if (!vec->enabled) {
279 trace_nvic_escalate_disabled(irq);
280 escalate = true;
281 }
282
283 if (escalate) {
284 if (running < 0) {
285
286
287
288
289
290 cpu_abort(&s->cpu->parent_obj,
291 "Lockup: can't escalate %d to HardFault "
292 "(current priority %d)\n", irq, running);
293 }
294
295
296 irq = ARMV7M_EXCP_HARD;
297 vec = &s->vectors[irq];
298 s->cpu->env.v7m.hfsr |= R_V7M_HFSR_FORCED_MASK;
299 }
300 }
301
302 if (!vec->pending) {
303 vec->pending = 1;
304 nvic_irq_update(s);
305 }
306}
307
308
309void armv7m_nvic_acknowledge_irq(void *opaque)
310{
311 NVICState *s = (NVICState *)opaque;
312 CPUARMState *env = &s->cpu->env;
313 const int pending = s->vectpending;
314 const int running = nvic_exec_prio(s);
315 int pendgroupprio;
316 VecInfo *vec;
317
318 assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq);
319
320 vec = &s->vectors[pending];
321
322 assert(vec->enabled);
323 assert(vec->pending);
324
325 pendgroupprio = vec->prio & nvic_gprio_mask(s);
326 assert(pendgroupprio < running);
327
328 trace_nvic_acknowledge_irq(pending, vec->prio);
329
330 vec->active = 1;
331 vec->pending = 0;
332
333 env->v7m.exception = s->vectpending;
334
335 nvic_irq_update(s);
336}
337
338int armv7m_nvic_complete_irq(void *opaque, int irq)
339{
340 NVICState *s = (NVICState *)opaque;
341 VecInfo *vec;
342 int ret;
343
344 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
345
346 vec = &s->vectors[irq];
347
348 trace_nvic_complete_irq(irq);
349
350 if (!vec->active) {
351
352 return -1;
353 }
354
355 ret = nvic_rettobase(s);
356
357 vec->active = 0;
358 if (vec->level) {
359
360
361
362 assert(irq >= NVIC_FIRST_IRQ);
363 vec->pending = 1;
364 }
365
366 nvic_irq_update(s);
367
368 return ret;
369}
370
371
372static void set_irq_level(void *opaque, int n, int level)
373{
374 NVICState *s = opaque;
375 VecInfo *vec;
376
377 n += NVIC_FIRST_IRQ;
378
379 assert(n >= NVIC_FIRST_IRQ && n < s->num_irq);
380
381 trace_nvic_set_irq_level(n, level);
382
383
384
385
386
387
388
389
390 vec = &s->vectors[n];
391 if (level != vec->level) {
392 vec->level = level;
393 if (level) {
394 armv7m_nvic_set_pending(s, n);
395 }
396 }
397}
398
399static uint32_t nvic_readl(NVICState *s, uint32_t offset)
400{
401 ARMCPU *cpu = s->cpu;
402 uint32_t val;
403
404 switch (offset) {
405 case 4:
406 return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1;
407 case 0xd00:
408 return cpu->midr;
409 case 0xd04:
410
411 val = cpu->env.v7m.exception;
412
413 val |= (s->vectpending & 0xff) << 12;
414
415 if (nvic_isrpending(s)) {
416 val |= (1 << 22);
417 }
418
419 if (nvic_rettobase(s)) {
420 val |= (1 << 11);
421 }
422
423 if (s->vectors[ARMV7M_EXCP_SYSTICK].pending) {
424 val |= (1 << 26);
425 }
426
427 if (s->vectors[ARMV7M_EXCP_PENDSV].pending) {
428 val |= (1 << 28);
429 }
430
431 if (s->vectors[ARMV7M_EXCP_NMI].pending) {
432 val |= (1 << 31);
433 }
434
435 return val;
436 case 0xd08:
437 return cpu->env.v7m.vecbase;
438 case 0xd0c:
439 return 0xfa050000 | (s->prigroup << 8);
440 case 0xd10:
441
442 return 0;
443 case 0xd14:
444 return cpu->env.v7m.ccr;
445 case 0xd24:
446 val = 0;
447 if (s->vectors[ARMV7M_EXCP_MEM].active) {
448 val |= (1 << 0);
449 }
450 if (s->vectors[ARMV7M_EXCP_BUS].active) {
451 val |= (1 << 1);
452 }
453 if (s->vectors[ARMV7M_EXCP_USAGE].active) {
454 val |= (1 << 3);
455 }
456 if (s->vectors[ARMV7M_EXCP_SVC].active) {
457 val |= (1 << 7);
458 }
459 if (s->vectors[ARMV7M_EXCP_DEBUG].active) {
460 val |= (1 << 8);
461 }
462 if (s->vectors[ARMV7M_EXCP_PENDSV].active) {
463 val |= (1 << 10);
464 }
465 if (s->vectors[ARMV7M_EXCP_SYSTICK].active) {
466 val |= (1 << 11);
467 }
468 if (s->vectors[ARMV7M_EXCP_USAGE].pending) {
469 val |= (1 << 12);
470 }
471 if (s->vectors[ARMV7M_EXCP_MEM].pending) {
472 val |= (1 << 13);
473 }
474 if (s->vectors[ARMV7M_EXCP_BUS].pending) {
475 val |= (1 << 14);
476 }
477 if (s->vectors[ARMV7M_EXCP_SVC].pending) {
478 val |= (1 << 15);
479 }
480 if (s->vectors[ARMV7M_EXCP_MEM].enabled) {
481 val |= (1 << 16);
482 }
483 if (s->vectors[ARMV7M_EXCP_BUS].enabled) {
484 val |= (1 << 17);
485 }
486 if (s->vectors[ARMV7M_EXCP_USAGE].enabled) {
487 val |= (1 << 18);
488 }
489 return val;
490 case 0xd28:
491 return cpu->env.v7m.cfsr;
492 case 0xd2c:
493 return cpu->env.v7m.hfsr;
494 case 0xd30:
495 return cpu->env.v7m.dfsr;
496 case 0xd34:
497 return cpu->env.v7m.mmfar;
498 case 0xd38:
499 return cpu->env.v7m.bfar;
500 case 0xd3c:
501
502 qemu_log_mask(LOG_UNIMP,
503 "Aux Fault status registers unimplemented\n");
504 return 0;
505 case 0xd40:
506 return 0x00000030;
507 case 0xd44:
508 return 0x00000200;
509 case 0xd48:
510 return 0x00100000;
511 case 0xd4c:
512 return 0x00000000;
513 case 0xd50:
514 return 0x00000030;
515 case 0xd54:
516 return 0x00000000;
517 case 0xd58:
518 return 0x00000000;
519 case 0xd5c:
520 return 0x00000000;
521 case 0xd60:
522 return 0x01141110;
523 case 0xd64:
524 return 0x02111000;
525 case 0xd68:
526 return 0x21112231;
527 case 0xd6c:
528 return 0x01111110;
529 case 0xd70:
530 return 0x01310102;
531
532 case 0xd90:
533
534 return cpu->pmsav7_dregion << 8;
535 break;
536 case 0xd94:
537 return cpu->env.v7m.mpu_ctrl;
538 case 0xd98:
539 return cpu->env.pmsav7.rnr;
540 case 0xd9c:
541 case 0xda4:
542 case 0xdac:
543 case 0xdb4:
544 {
545 int region = cpu->env.pmsav7.rnr;
546
547 if (region >= cpu->pmsav7_dregion) {
548 return 0;
549 }
550 return (cpu->env.pmsav7.drbar[region] & 0x1f) | (region & 0xf);
551 }
552 case 0xda0:
553 case 0xda8:
554 case 0xdb0:
555 case 0xdb8:
556 {
557 int region = cpu->env.pmsav7.rnr;
558
559 if (region >= cpu->pmsav7_dregion) {
560 return 0;
561 }
562 return ((cpu->env.pmsav7.dracr[region] & 0xffff) << 16) |
563 (cpu->env.pmsav7.drsr[region] & 0xffff);
564 }
565 default:
566 qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset);
567 return 0;
568 }
569}
570
571static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value)
572{
573 ARMCPU *cpu = s->cpu;
574
575 switch (offset) {
576 case 0xd04:
577 if (value & (1 << 31)) {
578 armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI);
579 }
580 if (value & (1 << 28)) {
581 armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV);
582 } else if (value & (1 << 27)) {
583 armv7m_nvic_clear_pending(s, ARMV7M_EXCP_PENDSV);
584 }
585 if (value & (1 << 26)) {
586 armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
587 } else if (value & (1 << 25)) {
588 armv7m_nvic_clear_pending(s, ARMV7M_EXCP_SYSTICK);
589 }
590 break;
591 case 0xd08:
592 cpu->env.v7m.vecbase = value & 0xffffff80;
593 break;
594 case 0xd0c:
595 if ((value >> 16) == 0x05fa) {
596 if (value & 4) {
597 qemu_irq_pulse(s->sysresetreq);
598 }
599 if (value & 2) {
600 qemu_log_mask(LOG_GUEST_ERROR,
601 "Setting VECTCLRACTIVE when not in DEBUG mode "
602 "is UNPREDICTABLE\n");
603 }
604 if (value & 1) {
605 qemu_log_mask(LOG_GUEST_ERROR,
606 "Setting VECTRESET when not in DEBUG mode "
607 "is UNPREDICTABLE\n");
608 }
609 s->prigroup = extract32(value, 8, 3);
610 nvic_irq_update(s);
611 }
612 break;
613 case 0xd10:
614
615 qemu_log_mask(LOG_UNIMP, "NVIC: SCR unimplemented\n");
616 break;
617 case 0xd14:
618
619 value &= (R_V7M_CCR_STKALIGN_MASK |
620 R_V7M_CCR_BFHFNMIGN_MASK |
621 R_V7M_CCR_DIV_0_TRP_MASK |
622 R_V7M_CCR_UNALIGN_TRP_MASK |
623 R_V7M_CCR_USERSETMPEND_MASK |
624 R_V7M_CCR_NONBASETHRDENA_MASK);
625
626 cpu->env.v7m.ccr = value;
627 break;
628 case 0xd24:
629 s->vectors[ARMV7M_EXCP_MEM].active = (value & (1 << 0)) != 0;
630 s->vectors[ARMV7M_EXCP_BUS].active = (value & (1 << 1)) != 0;
631 s->vectors[ARMV7M_EXCP_USAGE].active = (value & (1 << 3)) != 0;
632 s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0;
633 s->vectors[ARMV7M_EXCP_DEBUG].active = (value & (1 << 8)) != 0;
634 s->vectors[ARMV7M_EXCP_PENDSV].active = (value & (1 << 10)) != 0;
635 s->vectors[ARMV7M_EXCP_SYSTICK].active = (value & (1 << 11)) != 0;
636 s->vectors[ARMV7M_EXCP_USAGE].pending = (value & (1 << 12)) != 0;
637 s->vectors[ARMV7M_EXCP_MEM].pending = (value & (1 << 13)) != 0;
638 s->vectors[ARMV7M_EXCP_BUS].pending = (value & (1 << 14)) != 0;
639 s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0;
640 s->vectors[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
641 s->vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
642 s->vectors[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;
643 nvic_irq_update(s);
644 break;
645 case 0xd28:
646 cpu->env.v7m.cfsr &= ~value;
647 break;
648 case 0xd2c:
649 cpu->env.v7m.hfsr &= ~value;
650 break;
651 case 0xd30:
652 cpu->env.v7m.dfsr &= ~value;
653 break;
654 case 0xd34:
655 cpu->env.v7m.mmfar = value;
656 return;
657 case 0xd38:
658 cpu->env.v7m.bfar = value;
659 return;
660 case 0xd3c:
661 qemu_log_mask(LOG_UNIMP,
662 "NVIC: Aux fault status registers unimplemented\n");
663 break;
664 case 0xd90:
665 return;
666 case 0xd94:
667 if ((value &
668 (R_V7M_MPU_CTRL_HFNMIENA_MASK | R_V7M_MPU_CTRL_ENABLE_MASK))
669 == R_V7M_MPU_CTRL_HFNMIENA_MASK) {
670 qemu_log_mask(LOG_GUEST_ERROR, "MPU_CTRL: HFNMIENA and !ENABLE is "
671 "UNPREDICTABLE\n");
672 }
673 cpu->env.v7m.mpu_ctrl = value & (R_V7M_MPU_CTRL_ENABLE_MASK |
674 R_V7M_MPU_CTRL_HFNMIENA_MASK |
675 R_V7M_MPU_CTRL_PRIVDEFENA_MASK);
676 tlb_flush(CPU(cpu));
677 break;
678 case 0xd98:
679 if (value >= cpu->pmsav7_dregion) {
680 qemu_log_mask(LOG_GUEST_ERROR, "MPU region out of range %"
681 PRIu32 "/%" PRIu32 "\n",
682 value, cpu->pmsav7_dregion);
683 } else {
684 cpu->env.pmsav7.rnr = value;
685 }
686 break;
687 case 0xd9c:
688 case 0xda4:
689 case 0xdac:
690 case 0xdb4:
691 {
692 int region;
693
694 if (value & (1 << 4)) {
695
696
697
698 region = extract32(value, 0, 4);
699 if (region >= cpu->pmsav7_dregion) {
700 qemu_log_mask(LOG_GUEST_ERROR,
701 "MPU region out of range %u/%" PRIu32 "\n",
702 region, cpu->pmsav7_dregion);
703 return;
704 }
705 cpu->env.pmsav7.rnr = region;
706 } else {
707 region = cpu->env.pmsav7.rnr;
708 }
709
710 if (region >= cpu->pmsav7_dregion) {
711 return;
712 }
713
714 cpu->env.pmsav7.drbar[region] = value & ~0x1f;
715 tlb_flush(CPU(cpu));
716 break;
717 }
718 case 0xda0:
719 case 0xda8:
720 case 0xdb0:
721 case 0xdb8:
722 {
723 int region = cpu->env.pmsav7.rnr;
724
725 if (region >= cpu->pmsav7_dregion) {
726 return;
727 }
728
729 cpu->env.pmsav7.drsr[region] = value & 0xff3f;
730 cpu->env.pmsav7.dracr[region] = (value >> 16) & 0x173f;
731 tlb_flush(CPU(cpu));
732 break;
733 }
734 case 0xf00:
735 {
736
737 int excnum = (value & 0x1ff) + NVIC_FIRST_IRQ;
738 if (excnum < s->num_irq &&
739 (arm_current_el(&cpu->env) ||
740 (cpu->env.v7m.ccr & R_V7M_CCR_USERSETMPEND_MASK))) {
741 armv7m_nvic_set_pending(s, excnum);
742 }
743 break;
744 }
745 default:
746 qemu_log_mask(LOG_GUEST_ERROR,
747 "NVIC: Bad write offset 0x%x\n", offset);
748 }
749}
750
751static uint64_t nvic_sysreg_read(void *opaque, hwaddr addr,
752 unsigned size)
753{
754 NVICState *s = (NVICState *)opaque;
755 uint32_t offset = addr;
756 unsigned i, startvec, end;
757 uint32_t val;
758
759 switch (offset) {
760
761 case 0x100 ... 0x13f:
762 offset += 0x80;
763
764 case 0x180 ... 0x1bf:
765 val = 0;
766 startvec = offset - 0x180 + NVIC_FIRST_IRQ;
767
768 for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
769 if (s->vectors[startvec + i].enabled) {
770 val |= (1 << i);
771 }
772 }
773 break;
774 case 0x200 ... 0x23f:
775 offset += 0x80;
776
777 case 0x280 ... 0x2bf:
778 val = 0;
779 startvec = offset - 0x280 + NVIC_FIRST_IRQ;
780 for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
781 if (s->vectors[startvec + i].pending) {
782 val |= (1 << i);
783 }
784 }
785 break;
786 case 0x300 ... 0x33f:
787 val = 0;
788 startvec = offset - 0x300 + NVIC_FIRST_IRQ;
789
790 for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
791 if (s->vectors[startvec + i].active) {
792 val |= (1 << i);
793 }
794 }
795 break;
796 case 0x400 ... 0x5ef:
797 val = 0;
798 startvec = offset - 0x400 + NVIC_FIRST_IRQ;
799
800 for (i = 0; i < size && startvec + i < s->num_irq; i++) {
801 val |= s->vectors[startvec + i].prio << (8 * i);
802 }
803 break;
804 case 0xd18 ... 0xd23:
805 val = 0;
806 for (i = 0; i < size; i++) {
807 val |= s->vectors[(offset - 0xd14) + i].prio << (i * 8);
808 }
809 break;
810 case 0xfe0 ... 0xfff:
811 if (offset & 3) {
812 val = 0;
813 } else {
814 val = nvic_id[(offset - 0xfe0) >> 2];
815 }
816 break;
817 default:
818 if (size == 4) {
819 val = nvic_readl(s, offset);
820 } else {
821 qemu_log_mask(LOG_GUEST_ERROR,
822 "NVIC: Bad read of size %d at offset 0x%x\n",
823 size, offset);
824 val = 0;
825 }
826 }
827
828 trace_nvic_sysreg_read(addr, val, size);
829 return val;
830}
831
832static void nvic_sysreg_write(void *opaque, hwaddr addr,
833 uint64_t value, unsigned size)
834{
835 NVICState *s = (NVICState *)opaque;
836 uint32_t offset = addr;
837 unsigned i, startvec, end;
838 unsigned setval = 0;
839
840 trace_nvic_sysreg_write(addr, value, size);
841
842 switch (offset) {
843 case 0x100 ... 0x13f:
844 offset += 0x80;
845 setval = 1;
846
847 case 0x180 ... 0x1bf:
848 startvec = 8 * (offset - 0x180) + NVIC_FIRST_IRQ;
849
850 for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
851 if (value & (1 << i)) {
852 s->vectors[startvec + i].enabled = setval;
853 }
854 }
855 nvic_irq_update(s);
856 return;
857 case 0x200 ... 0x23f:
858
859
860
861 offset += 0x80;
862 setval = 1;
863
864 case 0x280 ... 0x2bf:
865 startvec = 8 * (offset - 0x280) + NVIC_FIRST_IRQ;
866
867 for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {
868 if (value & (1 << i)) {
869 s->vectors[startvec + i].pending = setval;
870 }
871 }
872 nvic_irq_update(s);
873 return;
874 case 0x300 ... 0x33f:
875 return;
876 case 0x400 ... 0x5ef:
877 startvec = 8 * (offset - 0x400) + NVIC_FIRST_IRQ;
878
879 for (i = 0; i < size && startvec + i < s->num_irq; i++) {
880 set_prio(s, startvec + i, (value >> (i * 8)) & 0xff);
881 }
882 nvic_irq_update(s);
883 return;
884 case 0xd18 ... 0xd23:
885 for (i = 0; i < size; i++) {
886 unsigned hdlidx = (offset - 0xd14) + i;
887 set_prio(s, hdlidx, (value >> (i * 8)) & 0xff);
888 }
889 nvic_irq_update(s);
890 return;
891 }
892 if (size == 4) {
893 nvic_writel(s, offset, value);
894 return;
895 }
896 qemu_log_mask(LOG_GUEST_ERROR,
897 "NVIC: Bad write of size %d at offset 0x%x\n", size, offset);
898}
899
900static const MemoryRegionOps nvic_sysreg_ops = {
901 .read = nvic_sysreg_read,
902 .write = nvic_sysreg_write,
903 .endianness = DEVICE_NATIVE_ENDIAN,
904};
905
906static int nvic_post_load(void *opaque, int version_id)
907{
908 NVICState *s = opaque;
909 unsigned i;
910
911
912 if (s->vectors[ARMV7M_EXCP_RESET].prio != -3 ||
913 s->vectors[ARMV7M_EXCP_NMI].prio != -2 ||
914 s->vectors[ARMV7M_EXCP_HARD].prio != -1) {
915 return 1;
916 }
917 for (i = ARMV7M_EXCP_MEM; i < s->num_irq; i++) {
918 if (s->vectors[i].prio & ~0xff) {
919 return 1;
920 }
921 }
922
923 nvic_recompute_state(s);
924
925 return 0;
926}
927
928static const VMStateDescription vmstate_VecInfo = {
929 .name = "armv7m_nvic_info",
930 .version_id = 1,
931 .minimum_version_id = 1,
932 .fields = (VMStateField[]) {
933 VMSTATE_INT16(prio, VecInfo),
934 VMSTATE_UINT8(enabled, VecInfo),
935 VMSTATE_UINT8(pending, VecInfo),
936 VMSTATE_UINT8(active, VecInfo),
937 VMSTATE_UINT8(level, VecInfo),
938 VMSTATE_END_OF_LIST()
939 }
940};
941
942static const VMStateDescription vmstate_nvic = {
943 .name = "armv7m_nvic",
944 .version_id = 4,
945 .minimum_version_id = 4,
946 .post_load = &nvic_post_load,
947 .fields = (VMStateField[]) {
948 VMSTATE_STRUCT_ARRAY(vectors, NVICState, NVIC_MAX_VECTORS, 1,
949 vmstate_VecInfo, VecInfo),
950 VMSTATE_UINT32(prigroup, NVICState),
951 VMSTATE_END_OF_LIST()
952 }
953};
954
955static Property props_nvic[] = {
956
957 DEFINE_PROP_UINT32("num-irq", NVICState, num_irq, 64),
958 DEFINE_PROP_END_OF_LIST()
959};
960
961static void armv7m_nvic_reset(DeviceState *dev)
962{
963 NVICState *s = NVIC(dev);
964
965 s->vectors[ARMV7M_EXCP_NMI].enabled = 1;
966 s->vectors[ARMV7M_EXCP_HARD].enabled = 1;
967
968
969
970 s->vectors[ARMV7M_EXCP_SVC].enabled = 1;
971 s->vectors[ARMV7M_EXCP_DEBUG].enabled = 1;
972 s->vectors[ARMV7M_EXCP_PENDSV].enabled = 1;
973 s->vectors[ARMV7M_EXCP_SYSTICK].enabled = 1;
974
975 s->vectors[ARMV7M_EXCP_RESET].prio = -3;
976 s->vectors[ARMV7M_EXCP_NMI].prio = -2;
977 s->vectors[ARMV7M_EXCP_HARD].prio = -1;
978
979
980
981
982
983
984
985 s->exception_prio = NVIC_NOEXC_PRIO;
986 s->vectpending = 0;
987}
988
989static void nvic_systick_trigger(void *opaque, int n, int level)
990{
991 NVICState *s = opaque;
992
993 if (level) {
994
995
996
997
998 armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
999 }
1000}
1001
1002static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
1003{
1004 NVICState *s = NVIC(dev);
1005 SysBusDevice *systick_sbd;
1006 Error *err = NULL;
1007
1008 s->cpu = ARM_CPU(qemu_get_cpu(0));
1009 assert(s->cpu);
1010
1011 if (s->num_irq > NVIC_MAX_IRQ) {
1012 error_setg(errp, "num-irq %d exceeds NVIC maximum", s->num_irq);
1013 return;
1014 }
1015
1016 qdev_init_gpio_in(dev, set_irq_level, s->num_irq);
1017
1018
1019 s->num_irq += NVIC_FIRST_IRQ;
1020
1021 object_property_set_bool(OBJECT(&s->systick), true, "realized", &err);
1022 if (err != NULL) {
1023 error_propagate(errp, err);
1024 return;
1025 }
1026 systick_sbd = SYS_BUS_DEVICE(&s->systick);
1027 sysbus_connect_irq(systick_sbd, 0,
1028 qdev_get_gpio_in_named(dev, "systick-trigger", 0));
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044 memory_region_init(&s->container, OBJECT(s), "nvic", 0x1000);
1045
1046
1047
1048 memory_region_init_io(&s->sysregmem, OBJECT(s), &nvic_sysreg_ops, s,
1049 "nvic_sysregs", 0x1000);
1050 memory_region_add_subregion(&s->container, 0, &s->sysregmem);
1051 memory_region_add_subregion_overlap(&s->container, 0x10,
1052 sysbus_mmio_get_region(systick_sbd, 0),
1053 1);
1054
1055 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container);
1056}
1057
1058static void armv7m_nvic_instance_init(Object *obj)
1059{
1060
1061
1062
1063
1064
1065
1066 DeviceState *dev = DEVICE(obj);
1067 NVICState *nvic = NVIC(obj);
1068 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1069
1070 object_initialize(&nvic->systick, sizeof(nvic->systick), TYPE_SYSTICK);
1071 qdev_set_parent_bus(DEVICE(&nvic->systick), sysbus_get_default());
1072
1073 sysbus_init_irq(sbd, &nvic->excpout);
1074 qdev_init_gpio_out_named(dev, &nvic->sysresetreq, "SYSRESETREQ", 1);
1075 qdev_init_gpio_in_named(dev, nvic_systick_trigger, "systick-trigger", 1);
1076}
1077
1078static void armv7m_nvic_class_init(ObjectClass *klass, void *data)
1079{
1080 DeviceClass *dc = DEVICE_CLASS(klass);
1081
1082 dc->vmsd = &vmstate_nvic;
1083 dc->props = props_nvic;
1084 dc->reset = armv7m_nvic_reset;
1085 dc->realize = armv7m_nvic_realize;
1086}
1087
1088static const TypeInfo armv7m_nvic_info = {
1089 .name = TYPE_NVIC,
1090 .parent = TYPE_SYS_BUS_DEVICE,
1091 .instance_init = armv7m_nvic_instance_init,
1092 .instance_size = sizeof(NVICState),
1093 .class_init = armv7m_nvic_class_init,
1094 .class_size = sizeof(SysBusDeviceClass),
1095};
1096
1097static void armv7m_nvic_register_types(void)
1098{
1099 type_register_static(&armv7m_nvic_info);
1100}
1101
1102type_init(armv7m_nvic_register_types)
1103