1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28#include "qemu/osdep.h"
29#include "qapi/error.h"
30#include "qemu-common.h"
31#include "cpu.h"
32#include "hw/hw.h"
33#include "trace.h"
34#include "qemu/timer.h"
35#include "hw/ppc/xics.h"
36#include "qemu/error-report.h"
37#include "qapi/visitor.h"
38#include "monitor/monitor.h"
39#include "hw/intc/intc.h"
40
41void icp_pic_print_info(ICPState *icp, Monitor *mon)
42{
43 int cpu_index = icp->cs ? icp->cs->cpu_index : -1;
44
45 if (!icp->output) {
46 return;
47 }
48 monitor_printf(mon, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n",
49 cpu_index, icp->xirr, icp->xirr_owner,
50 icp->pending_priority, icp->mfrr);
51}
52
53void ics_pic_print_info(ICSState *ics, Monitor *mon)
54{
55 uint32_t i;
56
57 monitor_printf(mon, "ICS %4x..%4x %p\n",
58 ics->offset, ics->offset + ics->nr_irqs - 1, ics);
59
60 if (!ics->irqs) {
61 return;
62 }
63
64 for (i = 0; i < ics->nr_irqs; i++) {
65 ICSIRQState *irq = ics->irqs + i;
66
67 if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) {
68 continue;
69 }
70 monitor_printf(mon, " %4x %s %02x %02x\n",
71 ics->offset + i,
72 (irq->flags & XICS_FLAGS_IRQ_LSI) ?
73 "LSI" : "MSI",
74 irq->priority, irq->status);
75 }
76}
77
78
79
80
81
82#define XISR_MASK 0x00ffffff
83#define CPPR_MASK 0xff000000
84
85#define XISR(icp) (((icp)->xirr) & XISR_MASK)
86#define CPPR(icp) (((icp)->xirr) >> 24)
87
88static void ics_reject(ICSState *ics, uint32_t nr)
89{
90 ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
91
92 if (k->reject) {
93 k->reject(ics, nr);
94 }
95}
96
97void ics_resend(ICSState *ics)
98{
99 ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
100
101 if (k->resend) {
102 k->resend(ics);
103 }
104}
105
106static void ics_eoi(ICSState *ics, int nr)
107{
108 ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
109
110 if (k->eoi) {
111 k->eoi(ics, nr);
112 }
113}
114
115static void icp_check_ipi(ICPState *icp)
116{
117 if (XISR(icp) && (icp->pending_priority <= icp->mfrr)) {
118 return;
119 }
120
121 trace_xics_icp_check_ipi(icp->cs->cpu_index, icp->mfrr);
122
123 if (XISR(icp) && icp->xirr_owner) {
124 ics_reject(icp->xirr_owner, XISR(icp));
125 }
126
127 icp->xirr = (icp->xirr & ~XISR_MASK) | XICS_IPI;
128 icp->pending_priority = icp->mfrr;
129 icp->xirr_owner = NULL;
130 qemu_irq_raise(icp->output);
131}
132
133void icp_resend(ICPState *icp)
134{
135 XICSFabric *xi = icp->xics;
136 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
137
138 if (icp->mfrr < CPPR(icp)) {
139 icp_check_ipi(icp);
140 }
141
142 xic->ics_resend(xi);
143}
144
145void icp_set_cppr(ICPState *icp, uint8_t cppr)
146{
147 uint8_t old_cppr;
148 uint32_t old_xisr;
149
150 old_cppr = CPPR(icp);
151 icp->xirr = (icp->xirr & ~CPPR_MASK) | (cppr << 24);
152
153 if (cppr < old_cppr) {
154 if (XISR(icp) && (cppr <= icp->pending_priority)) {
155 old_xisr = XISR(icp);
156 icp->xirr &= ~XISR_MASK;
157 icp->pending_priority = 0xff;
158 qemu_irq_lower(icp->output);
159 if (icp->xirr_owner) {
160 ics_reject(icp->xirr_owner, old_xisr);
161 icp->xirr_owner = NULL;
162 }
163 }
164 } else {
165 if (!XISR(icp)) {
166 icp_resend(icp);
167 }
168 }
169}
170
171void icp_set_mfrr(ICPState *icp, uint8_t mfrr)
172{
173 icp->mfrr = mfrr;
174 if (mfrr < CPPR(icp)) {
175 icp_check_ipi(icp);
176 }
177}
178
179uint32_t icp_accept(ICPState *icp)
180{
181 uint32_t xirr = icp->xirr;
182
183 qemu_irq_lower(icp->output);
184 icp->xirr = icp->pending_priority << 24;
185 icp->pending_priority = 0xff;
186 icp->xirr_owner = NULL;
187
188 trace_xics_icp_accept(xirr, icp->xirr);
189
190 return xirr;
191}
192
193uint32_t icp_ipoll(ICPState *icp, uint32_t *mfrr)
194{
195 if (mfrr) {
196 *mfrr = icp->mfrr;
197 }
198 return icp->xirr;
199}
200
201void icp_eoi(ICPState *icp, uint32_t xirr)
202{
203 XICSFabric *xi = icp->xics;
204 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
205 ICSState *ics;
206 uint32_t irq;
207
208
209 icp->xirr = (icp->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
210 trace_xics_icp_eoi(icp->cs->cpu_index, xirr, icp->xirr);
211 irq = xirr & XISR_MASK;
212
213 ics = xic->ics_get(xi, irq);
214 if (ics) {
215 ics_eoi(ics, irq);
216 }
217 if (!XISR(icp)) {
218 icp_resend(icp);
219 }
220}
221
222static void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)
223{
224 ICPState *icp = xics_icp_get(ics->xics, server);
225
226 trace_xics_icp_irq(server, nr, priority);
227
228 if ((priority >= CPPR(icp))
229 || (XISR(icp) && (icp->pending_priority <= priority))) {
230 ics_reject(ics, nr);
231 } else {
232 if (XISR(icp) && icp->xirr_owner) {
233 ics_reject(icp->xirr_owner, XISR(icp));
234 icp->xirr_owner = NULL;
235 }
236 icp->xirr = (icp->xirr & ~XISR_MASK) | (nr & XISR_MASK);
237 icp->xirr_owner = ics;
238 icp->pending_priority = priority;
239 trace_xics_icp_raise(icp->xirr, icp->pending_priority);
240 qemu_irq_raise(icp->output);
241 }
242}
243
244static void icp_dispatch_pre_save(void *opaque)
245{
246 ICPState *icp = opaque;
247 ICPStateClass *info = ICP_GET_CLASS(icp);
248
249 if (info->pre_save) {
250 info->pre_save(icp);
251 }
252}
253
254static int icp_dispatch_post_load(void *opaque, int version_id)
255{
256 ICPState *icp = opaque;
257 ICPStateClass *info = ICP_GET_CLASS(icp);
258
259 if (info->post_load) {
260 return info->post_load(icp, version_id);
261 }
262
263 return 0;
264}
265
266static const VMStateDescription vmstate_icp_server = {
267 .name = "icp/server",
268 .version_id = 1,
269 .minimum_version_id = 1,
270 .pre_save = icp_dispatch_pre_save,
271 .post_load = icp_dispatch_post_load,
272 .fields = (VMStateField[]) {
273
274 VMSTATE_UINT32(xirr, ICPState),
275 VMSTATE_UINT8(pending_priority, ICPState),
276 VMSTATE_UINT8(mfrr, ICPState),
277 VMSTATE_END_OF_LIST()
278 },
279};
280
281static void icp_reset(void *dev)
282{
283 ICPState *icp = ICP(dev);
284 ICPStateClass *icpc = ICP_GET_CLASS(icp);
285
286 icp->xirr = 0;
287 icp->pending_priority = 0xff;
288 icp->mfrr = 0xff;
289
290
291 qemu_set_irq(icp->output, 0);
292
293 if (icpc->reset) {
294 icpc->reset(icp);
295 }
296}
297
298static void icp_realize(DeviceState *dev, Error **errp)
299{
300 ICPState *icp = ICP(dev);
301 ICPStateClass *icpc = ICP_GET_CLASS(dev);
302 PowerPCCPU *cpu;
303 CPUPPCState *env;
304 Object *obj;
305 Error *err = NULL;
306
307 obj = object_property_get_link(OBJECT(dev), ICP_PROP_XICS, &err);
308 if (!obj) {
309 error_setg(errp, "%s: required link '" ICP_PROP_XICS "' not found: %s",
310 __func__, error_get_pretty(err));
311 return;
312 }
313
314 icp->xics = XICS_FABRIC(obj);
315
316 obj = object_property_get_link(OBJECT(dev), ICP_PROP_CPU, &err);
317 if (!obj) {
318 error_setg(errp, "%s: required link '" ICP_PROP_CPU "' not found: %s",
319 __func__, error_get_pretty(err));
320 return;
321 }
322
323 cpu = POWERPC_CPU(obj);
324 cpu->intc = OBJECT(icp);
325 icp->cs = CPU(obj);
326
327 env = &cpu->env;
328 switch (PPC_INPUT(env)) {
329 case PPC_FLAGS_INPUT_POWER7:
330 icp->output = env->irq_inputs[POWER7_INPUT_INT];
331 break;
332
333 case PPC_FLAGS_INPUT_970:
334 icp->output = env->irq_inputs[PPC970_INPUT_INT];
335 break;
336
337 default:
338 error_setg(errp, "XICS interrupt controller does not support this CPU bus model");
339 return;
340 }
341
342 if (icpc->realize) {
343 icpc->realize(icp, errp);
344 }
345
346 qemu_register_reset(icp_reset, dev);
347 vmstate_register(NULL, icp->cs->cpu_index, &vmstate_icp_server, icp);
348}
349
350static void icp_unrealize(DeviceState *dev, Error **errp)
351{
352 ICPState *icp = ICP(dev);
353
354 vmstate_unregister(NULL, &vmstate_icp_server, icp);
355 qemu_unregister_reset(icp_reset, dev);
356}
357
358static void icp_class_init(ObjectClass *klass, void *data)
359{
360 DeviceClass *dc = DEVICE_CLASS(klass);
361
362 dc->realize = icp_realize;
363 dc->unrealize = icp_unrealize;
364}
365
366static const TypeInfo icp_info = {
367 .name = TYPE_ICP,
368 .parent = TYPE_DEVICE,
369 .instance_size = sizeof(ICPState),
370 .class_init = icp_class_init,
371 .class_size = sizeof(ICPStateClass),
372};
373
374
375
376
377static void ics_simple_resend_msi(ICSState *ics, int srcno)
378{
379 ICSIRQState *irq = ics->irqs + srcno;
380
381
382 if (irq->status & XICS_STATUS_REJECTED) {
383 irq->status &= ~XICS_STATUS_REJECTED;
384 if (irq->priority != 0xff) {
385 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
386 }
387 }
388}
389
390static void ics_simple_resend_lsi(ICSState *ics, int srcno)
391{
392 ICSIRQState *irq = ics->irqs + srcno;
393
394 if ((irq->priority != 0xff)
395 && (irq->status & XICS_STATUS_ASSERTED)
396 && !(irq->status & XICS_STATUS_SENT)) {
397 irq->status |= XICS_STATUS_SENT;
398 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
399 }
400}
401
402static void ics_simple_set_irq_msi(ICSState *ics, int srcno, int val)
403{
404 ICSIRQState *irq = ics->irqs + srcno;
405
406 trace_xics_ics_simple_set_irq_msi(srcno, srcno + ics->offset);
407
408 if (val) {
409 if (irq->priority == 0xff) {
410 irq->status |= XICS_STATUS_MASKED_PENDING;
411 trace_xics_masked_pending();
412 } else {
413 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
414 }
415 }
416}
417
418static void ics_simple_set_irq_lsi(ICSState *ics, int srcno, int val)
419{
420 ICSIRQState *irq = ics->irqs + srcno;
421
422 trace_xics_ics_simple_set_irq_lsi(srcno, srcno + ics->offset);
423 if (val) {
424 irq->status |= XICS_STATUS_ASSERTED;
425 } else {
426 irq->status &= ~XICS_STATUS_ASSERTED;
427 }
428 ics_simple_resend_lsi(ics, srcno);
429}
430
431static void ics_simple_set_irq(void *opaque, int srcno, int val)
432{
433 ICSState *ics = (ICSState *)opaque;
434
435 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
436 ics_simple_set_irq_lsi(ics, srcno, val);
437 } else {
438 ics_simple_set_irq_msi(ics, srcno, val);
439 }
440}
441
442static void ics_simple_write_xive_msi(ICSState *ics, int srcno)
443{
444 ICSIRQState *irq = ics->irqs + srcno;
445
446 if (!(irq->status & XICS_STATUS_MASKED_PENDING)
447 || (irq->priority == 0xff)) {
448 return;
449 }
450
451 irq->status &= ~XICS_STATUS_MASKED_PENDING;
452 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
453}
454
455static void ics_simple_write_xive_lsi(ICSState *ics, int srcno)
456{
457 ics_simple_resend_lsi(ics, srcno);
458}
459
460void ics_simple_write_xive(ICSState *ics, int srcno, int server,
461 uint8_t priority, uint8_t saved_priority)
462{
463 ICSIRQState *irq = ics->irqs + srcno;
464
465 irq->server = server;
466 irq->priority = priority;
467 irq->saved_priority = saved_priority;
468
469 trace_xics_ics_simple_write_xive(ics->offset + srcno, srcno, server,
470 priority);
471
472 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
473 ics_simple_write_xive_lsi(ics, srcno);
474 } else {
475 ics_simple_write_xive_msi(ics, srcno);
476 }
477}
478
479static void ics_simple_reject(ICSState *ics, uint32_t nr)
480{
481 ICSIRQState *irq = ics->irqs + nr - ics->offset;
482
483 trace_xics_ics_simple_reject(nr, nr - ics->offset);
484 if (irq->flags & XICS_FLAGS_IRQ_MSI) {
485 irq->status |= XICS_STATUS_REJECTED;
486 } else if (irq->flags & XICS_FLAGS_IRQ_LSI) {
487 irq->status &= ~XICS_STATUS_SENT;
488 }
489}
490
491static void ics_simple_resend(ICSState *ics)
492{
493 int i;
494
495 for (i = 0; i < ics->nr_irqs; i++) {
496
497 if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) {
498 ics_simple_resend_lsi(ics, i);
499 } else {
500 ics_simple_resend_msi(ics, i);
501 }
502 }
503}
504
505static void ics_simple_eoi(ICSState *ics, uint32_t nr)
506{
507 int srcno = nr - ics->offset;
508 ICSIRQState *irq = ics->irqs + srcno;
509
510 trace_xics_ics_simple_eoi(nr);
511
512 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
513 irq->status &= ~XICS_STATUS_SENT;
514 }
515}
516
517static void ics_simple_reset(void *dev)
518{
519 ICSState *ics = ICS_SIMPLE(dev);
520 int i;
521 uint8_t flags[ics->nr_irqs];
522
523 for (i = 0; i < ics->nr_irqs; i++) {
524 flags[i] = ics->irqs[i].flags;
525 }
526
527 memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs);
528
529 for (i = 0; i < ics->nr_irqs; i++) {
530 ics->irqs[i].priority = 0xff;
531 ics->irqs[i].saved_priority = 0xff;
532 ics->irqs[i].flags = flags[i];
533 }
534}
535
536static void ics_simple_dispatch_pre_save(void *opaque)
537{
538 ICSState *ics = opaque;
539 ICSStateClass *info = ICS_BASE_GET_CLASS(ics);
540
541 if (info->pre_save) {
542 info->pre_save(ics);
543 }
544}
545
546static int ics_simple_dispatch_post_load(void *opaque, int version_id)
547{
548 ICSState *ics = opaque;
549 ICSStateClass *info = ICS_BASE_GET_CLASS(ics);
550
551 if (info->post_load) {
552 return info->post_load(ics, version_id);
553 }
554
555 return 0;
556}
557
558static const VMStateDescription vmstate_ics_simple_irq = {
559 .name = "ics/irq",
560 .version_id = 2,
561 .minimum_version_id = 1,
562 .fields = (VMStateField[]) {
563 VMSTATE_UINT32(server, ICSIRQState),
564 VMSTATE_UINT8(priority, ICSIRQState),
565 VMSTATE_UINT8(saved_priority, ICSIRQState),
566 VMSTATE_UINT8(status, ICSIRQState),
567 VMSTATE_UINT8(flags, ICSIRQState),
568 VMSTATE_END_OF_LIST()
569 },
570};
571
572static const VMStateDescription vmstate_ics_simple = {
573 .name = "ics",
574 .version_id = 1,
575 .minimum_version_id = 1,
576 .pre_save = ics_simple_dispatch_pre_save,
577 .post_load = ics_simple_dispatch_post_load,
578 .fields = (VMStateField[]) {
579
580 VMSTATE_UINT32_EQUAL(nr_irqs, ICSState, NULL),
581
582 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs,
583 vmstate_ics_simple_irq,
584 ICSIRQState),
585 VMSTATE_END_OF_LIST()
586 },
587};
588
589static void ics_simple_initfn(Object *obj)
590{
591 ICSState *ics = ICS_SIMPLE(obj);
592
593 ics->offset = XICS_IRQ_BASE;
594}
595
596static void ics_simple_realize(ICSState *ics, Error **errp)
597{
598 if (!ics->nr_irqs) {
599 error_setg(errp, "Number of interrupts needs to be greater 0");
600 return;
601 }
602 ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState));
603 ics->qirqs = qemu_allocate_irqs(ics_simple_set_irq, ics, ics->nr_irqs);
604
605 qemu_register_reset(ics_simple_reset, ics);
606}
607
608static Property ics_simple_properties[] = {
609 DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0),
610 DEFINE_PROP_END_OF_LIST(),
611};
612
613static void ics_simple_class_init(ObjectClass *klass, void *data)
614{
615 DeviceClass *dc = DEVICE_CLASS(klass);
616 ICSStateClass *isc = ICS_BASE_CLASS(klass);
617
618 isc->realize = ics_simple_realize;
619 dc->props = ics_simple_properties;
620 dc->vmsd = &vmstate_ics_simple;
621 isc->reject = ics_simple_reject;
622 isc->resend = ics_simple_resend;
623 isc->eoi = ics_simple_eoi;
624}
625
626static const TypeInfo ics_simple_info = {
627 .name = TYPE_ICS_SIMPLE,
628 .parent = TYPE_ICS_BASE,
629 .instance_size = sizeof(ICSState),
630 .class_init = ics_simple_class_init,
631 .class_size = sizeof(ICSStateClass),
632 .instance_init = ics_simple_initfn,
633};
634
635static void ics_base_realize(DeviceState *dev, Error **errp)
636{
637 ICSStateClass *icsc = ICS_BASE_GET_CLASS(dev);
638 ICSState *ics = ICS_BASE(dev);
639 Object *obj;
640 Error *err = NULL;
641
642 obj = object_property_get_link(OBJECT(dev), ICS_PROP_XICS, &err);
643 if (!obj) {
644 error_setg(errp, "%s: required link '" ICS_PROP_XICS "' not found: %s",
645 __func__, error_get_pretty(err));
646 return;
647 }
648 ics->xics = XICS_FABRIC(obj);
649
650
651 if (icsc->realize) {
652 icsc->realize(ics, errp);
653 }
654}
655
656static void ics_base_class_init(ObjectClass *klass, void *data)
657{
658 DeviceClass *dc = DEVICE_CLASS(klass);
659
660 dc->realize = ics_base_realize;
661}
662
663static const TypeInfo ics_base_info = {
664 .name = TYPE_ICS_BASE,
665 .parent = TYPE_DEVICE,
666 .abstract = true,
667 .instance_size = sizeof(ICSState),
668 .class_init = ics_base_class_init,
669 .class_size = sizeof(ICSStateClass),
670};
671
672static const TypeInfo xics_fabric_info = {
673 .name = TYPE_XICS_FABRIC,
674 .parent = TYPE_INTERFACE,
675 .class_size = sizeof(XICSFabricClass),
676};
677
678
679
680
681qemu_irq xics_get_qirq(XICSFabric *xi, int irq)
682{
683 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
684 ICSState *ics = xic->ics_get(xi, irq);
685
686 if (ics) {
687 return ics->qirqs[irq - ics->offset];
688 }
689
690 return NULL;
691}
692
693ICPState *xics_icp_get(XICSFabric *xi, int server)
694{
695 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
696
697 return xic->icp_get(xi, server);
698}
699
700void ics_set_irq_type(ICSState *ics, int srcno, bool lsi)
701{
702 assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK));
703
704 ics->irqs[srcno].flags |=
705 lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI;
706}
707
708static void xics_register_types(void)
709{
710 type_register_static(&ics_simple_info);
711 type_register_static(&ics_base_info);
712 type_register_static(&icp_info);
713 type_register_static(&xics_fabric_info);
714}
715
716type_init(xics_register_types)
717
