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23#include "qemu/osdep.h"
24#include "hw/hw.h"
25#include "hw/mips/cpudevs.h"
26#include "cpu.h"
27#include "sysemu/kvm.h"
28#include "kvm_mips.h"
29
30static void cpu_mips_irq_request(void *opaque, int irq, int level)
31{
32 MIPSCPU *cpu = opaque;
33 CPUMIPSState *env = &cpu->env;
34 CPUState *cs = CPU(cpu);
35
36 if (irq < 0 || irq > 7)
37 return;
38
39 if (level) {
40 env->CP0_Cause |= 1 << (irq + CP0Ca_IP);
41
42 if (kvm_enabled() && irq == 2) {
43 kvm_mips_set_interrupt(cpu, irq, level);
44 }
45
46 } else {
47 env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP));
48
49 if (kvm_enabled() && irq == 2) {
50 kvm_mips_set_interrupt(cpu, irq, level);
51 }
52 }
53
54 if (env->CP0_Cause & CP0Ca_IP_mask) {
55 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
56 } else {
57 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
58 }
59}
60
61void cpu_mips_irq_init_cpu(MIPSCPU *cpu)
62{
63 CPUMIPSState *env = &cpu->env;
64 qemu_irq *qi;
65 int i;
66
67 qi = qemu_allocate_irqs(cpu_mips_irq_request, mips_env_get_cpu(env), 8);
68 for (i = 0; i < 8; i++) {
69 env->irq[i] = qi[i];
70 }
71}
72
73void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level)
74{
75 if (irq < 0 || irq > 2) {
76 return;
77 }
78
79 qemu_set_irq(env->irq[irq], level);
80}
81