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25#include "qemu/osdep.h"
26#include "hw/hw.h"
27#include "hw/mips/mips.h"
28#include "hw/mips/cpudevs.h"
29#include "hw/i386/pc.h"
30#include "hw/char/serial.h"
31#include "hw/isa/isa.h"
32#include "hw/block/fdc.h"
33#include "sysemu/sysemu.h"
34#include "sysemu/arch_init.h"
35#include "hw/boards.h"
36#include "net/net.h"
37#include "hw/scsi/esp.h"
38#include "hw/mips/bios.h"
39#include "hw/loader.h"
40#include "hw/timer/mc146818rtc.h"
41#include "hw/timer/i8254.h"
42#include "hw/audio/pcspk.h"
43#include "sysemu/block-backend.h"
44#include "hw/sysbus.h"
45#include "exec/address-spaces.h"
46#include "sysemu/qtest.h"
47#include "qemu/error-report.h"
48#include "qemu/help_option.h"
49
50enum jazz_model_e
51{
52 JAZZ_MAGNUM,
53 JAZZ_PICA61,
54};
55
56static void main_cpu_reset(void *opaque)
57{
58 MIPSCPU *cpu = opaque;
59
60 cpu_reset(CPU(cpu));
61}
62
63static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size)
64{
65 uint8_t val;
66 address_space_read(&address_space_memory, 0x90000071,
67 MEMTXATTRS_UNSPECIFIED, &val, 1);
68 return val;
69}
70
71static void rtc_write(void *opaque, hwaddr addr,
72 uint64_t val, unsigned size)
73{
74 uint8_t buf = val & 0xff;
75 address_space_write(&address_space_memory, 0x90000071,
76 MEMTXATTRS_UNSPECIFIED, &buf, 1);
77}
78
79static const MemoryRegionOps rtc_ops = {
80 .read = rtc_read,
81 .write = rtc_write,
82 .endianness = DEVICE_NATIVE_ENDIAN,
83};
84
85static uint64_t dma_dummy_read(void *opaque, hwaddr addr,
86 unsigned size)
87{
88
89
90 return 0xff;
91}
92
93static void dma_dummy_write(void *opaque, hwaddr addr,
94 uint64_t val, unsigned size)
95{
96
97
98}
99
100static const MemoryRegionOps dma_dummy_ops = {
101 .read = dma_dummy_read,
102 .write = dma_dummy_write,
103 .endianness = DEVICE_NATIVE_ENDIAN,
104};
105
106#define MAGNUM_BIOS_SIZE_MAX 0x7e000
107#define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
108
109static CPUUnassignedAccess real_do_unassigned_access;
110static void mips_jazz_do_unassigned_access(CPUState *cpu, hwaddr addr,
111 bool is_write, bool is_exec,
112 int opaque, unsigned size)
113{
114 if (!is_exec) {
115
116 return;
117 }
118 (*real_do_unassigned_access)(cpu, addr, is_write, is_exec, opaque, size);
119}
120
121static void mips_jazz_init(MachineState *machine,
122 enum jazz_model_e jazz_model)
123{
124 MemoryRegion *address_space = get_system_memory();
125 const char *cpu_model = machine->cpu_model;
126 char *filename;
127 int bios_size, n;
128 MIPSCPU *cpu;
129 CPUClass *cc;
130 CPUMIPSState *env;
131 qemu_irq *i8259;
132 rc4030_dma *dmas;
133 IOMMUMemoryRegion *rc4030_dma_mr;
134 MemoryRegion *isa_mem = g_new(MemoryRegion, 1);
135 MemoryRegion *isa_io = g_new(MemoryRegion, 1);
136 MemoryRegion *rtc = g_new(MemoryRegion, 1);
137 MemoryRegion *i8042 = g_new(MemoryRegion, 1);
138 MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
139 NICInfo *nd;
140 DeviceState *dev, *rc4030;
141 SysBusDevice *sysbus;
142 ISABus *isa_bus;
143 ISADevice *pit;
144 DriveInfo *fds[MAX_FD];
145 qemu_irq esp_reset, dma_enable;
146 MemoryRegion *ram = g_new(MemoryRegion, 1);
147 MemoryRegion *bios = g_new(MemoryRegion, 1);
148 MemoryRegion *bios2 = g_new(MemoryRegion, 1);
149
150
151 if (cpu_model == NULL) {
152 cpu_model = "R4000";
153 }
154 cpu = cpu_mips_init(cpu_model);
155 if (cpu == NULL) {
156 fprintf(stderr, "Unable to find CPU definition\n");
157 exit(1);
158 }
159 env = &cpu->env;
160 qemu_register_reset(main_cpu_reset, cpu);
161
162
163
164
165
166
167
168
169 cc = CPU_GET_CLASS(cpu);
170 real_do_unassigned_access = cc->do_unassigned_access;
171 cc->do_unassigned_access = mips_jazz_do_unassigned_access;
172
173
174 memory_region_allocate_system_memory(ram, NULL, "mips_jazz.ram",
175 machine->ram_size);
176 memory_region_add_subregion(address_space, 0, ram);
177
178 memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE,
179 &error_fatal);
180 memory_region_set_readonly(bios, true);
181 memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios,
182 0, MAGNUM_BIOS_SIZE);
183 memory_region_add_subregion(address_space, 0x1fc00000LL, bios);
184 memory_region_add_subregion(address_space, 0xfff00000LL, bios2);
185
186
187 if (bios_name == NULL)
188 bios_name = BIOS_FILENAME;
189 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
190 if (filename) {
191 bios_size = load_image_targphys(filename, 0xfff00000LL,
192 MAGNUM_BIOS_SIZE);
193 g_free(filename);
194 } else {
195 bios_size = -1;
196 }
197 if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) && !qtest_enabled()) {
198 error_report("Could not load MIPS bios '%s'", bios_name);
199 exit(1);
200 }
201
202
203 cpu_mips_irq_init_cpu(cpu);
204 cpu_mips_clock_init(cpu);
205
206
207 rc4030 = rc4030_init(&dmas, &rc4030_dma_mr);
208 sysbus = SYS_BUS_DEVICE(rc4030);
209 sysbus_connect_irq(sysbus, 0, env->irq[6]);
210 sysbus_connect_irq(sysbus, 1, env->irq[3]);
211 memory_region_add_subregion(address_space, 0x80000000,
212 sysbus_mmio_get_region(sysbus, 0));
213 memory_region_add_subregion(address_space, 0xf0000000,
214 sysbus_mmio_get_region(sysbus, 1));
215 memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops, NULL, "dummy_dma", 0x1000);
216 memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
217
218
219 memory_region_init(isa_io, NULL, "isa-io", 0x00010000);
220 memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000);
221 memory_region_add_subregion(address_space, 0x90000000, isa_io);
222 memory_region_add_subregion(address_space, 0x91000000, isa_mem);
223 isa_bus = isa_bus_new(NULL, isa_mem, isa_io, &error_abort);
224
225
226 i8259 = i8259_init(isa_bus, env->irq[4]);
227 isa_bus_irqs(isa_bus, i8259);
228 DMA_init(isa_bus, 0);
229 pit = pit_init(isa_bus, 0x40, 0, NULL);
230 pcspk_init(isa_bus, pit);
231
232
233 switch (jazz_model) {
234 case JAZZ_MAGNUM:
235 dev = qdev_create(NULL, "sysbus-g364");
236 qdev_init_nofail(dev);
237 sysbus = SYS_BUS_DEVICE(dev);
238 sysbus_mmio_map(sysbus, 0, 0x60080000);
239 sysbus_mmio_map(sysbus, 1, 0x40000000);
240 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 3));
241 {
242
243 MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
244 memory_region_init_ram(rom_mr, NULL, "g364fb.rom", 0x80000,
245 &error_fatal);
246 memory_region_set_readonly(rom_mr, true);
247 uint8_t *rom = memory_region_get_ram_ptr(rom_mr);
248 memory_region_add_subregion(address_space, 0x60000000, rom_mr);
249 rom[0] = 0x10;
250 }
251 break;
252 case JAZZ_PICA61:
253 isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
254 break;
255 default:
256 break;
257 }
258
259
260 for (n = 0; n < nb_nics; n++) {
261 nd = &nd_table[n];
262 if (!nd->model)
263 nd->model = g_strdup("dp83932");
264 if (strcmp(nd->model, "dp83932") == 0) {
265 qemu_check_nic_model(nd, "dp83932");
266
267 dev = qdev_create(NULL, "dp8393x");
268 qdev_set_nic_properties(dev, nd);
269 qdev_prop_set_uint8(dev, "it_shift", 2);
270 qdev_prop_set_ptr(dev, "dma_mr", rc4030_dma_mr);
271 qdev_init_nofail(dev);
272 sysbus = SYS_BUS_DEVICE(dev);
273 sysbus_mmio_map(sysbus, 0, 0x80001000);
274 sysbus_mmio_map(sysbus, 1, 0x8000b000);
275 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4));
276 break;
277 } else if (is_help_option(nd->model)) {
278 fprintf(stderr, "qemu: Supported NICs: dp83932\n");
279 exit(1);
280 } else {
281 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
282 exit(1);
283 }
284 }
285
286
287 esp_init(0x80002000, 0,
288 rc4030_dma_read, rc4030_dma_write, dmas[0],
289 qdev_get_gpio_in(rc4030, 5), &esp_reset, &dma_enable);
290
291
292 for (n = 0; n < MAX_FD; n++) {
293 fds[n] = drive_get(IF_FLOPPY, 0, n);
294 }
295
296 fdctrl_init_sysbus(qdev_get_gpio_in(rc4030, 1), -1, 0x80003000, fds);
297
298
299 rtc_init(isa_bus, 1980, NULL);
300 memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000);
301 memory_region_add_subregion(address_space, 0x80004000, rtc);
302
303
304 i8042_mm_init(qdev_get_gpio_in(rc4030, 6), qdev_get_gpio_in(rc4030, 7),
305 i8042, 0x1000, 0x1);
306 memory_region_add_subregion(address_space, 0x80005000, i8042);
307
308
309 if (serial_hds[0]) {
310 serial_mm_init(address_space, 0x80006000, 0,
311 qdev_get_gpio_in(rc4030, 8), 8000000/16,
312 serial_hds[0], DEVICE_NATIVE_ENDIAN);
313 }
314 if (serial_hds[1]) {
315 serial_mm_init(address_space, 0x80007000, 0,
316 qdev_get_gpio_in(rc4030, 9), 8000000/16,
317 serial_hds[1], DEVICE_NATIVE_ENDIAN);
318 }
319
320
321 if (parallel_hds[0])
322 parallel_mm_init(address_space, 0x80008000, 0,
323 qdev_get_gpio_in(rc4030, 0), parallel_hds[0]);
324
325
326
327
328 dev = qdev_create(NULL, "ds1225y");
329 qdev_init_nofail(dev);
330 sysbus = SYS_BUS_DEVICE(dev);
331 sysbus_mmio_map(sysbus, 0, 0x80009000);
332
333
334 sysbus_create_simple("jazz-led", 0x8000f000, NULL);
335}
336
337static
338void mips_magnum_init(MachineState *machine)
339{
340 mips_jazz_init(machine, JAZZ_MAGNUM);
341}
342
343static
344void mips_pica61_init(MachineState *machine)
345{
346 mips_jazz_init(machine, JAZZ_PICA61);
347}
348
349static void mips_magnum_class_init(ObjectClass *oc, void *data)
350{
351 MachineClass *mc = MACHINE_CLASS(oc);
352
353 mc->desc = "MIPS Magnum";
354 mc->init = mips_magnum_init;
355 mc->block_default_type = IF_SCSI;
356}
357
358static const TypeInfo mips_magnum_type = {
359 .name = MACHINE_TYPE_NAME("magnum"),
360 .parent = TYPE_MACHINE,
361 .class_init = mips_magnum_class_init,
362};
363
364static void mips_pica61_class_init(ObjectClass *oc, void *data)
365{
366 MachineClass *mc = MACHINE_CLASS(oc);
367
368 mc->desc = "Acer Pica 61";
369 mc->init = mips_pica61_init;
370 mc->block_default_type = IF_SCSI;
371}
372
373static const TypeInfo mips_pica61_type = {
374 .name = MACHINE_TYPE_NAME("pica61"),
375 .parent = TYPE_MACHINE,
376 .class_init = mips_pica61_class_init,
377};
378
379static void mips_jazz_machine_init(void)
380{
381 type_register_static(&mips_magnum_type);
382 type_register_static(&mips_pica61_type);
383}
384
385type_init(mips_jazz_machine_init)
386
