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25#include "qemu/osdep.h"
26#include "qemu-common.h"
27#include "cpu.h"
28#include "hw/hw.h"
29#include "hw/i386/pc.h"
30#include "hw/char/serial.h"
31#include "hw/block/fdc.h"
32#include "net/net.h"
33#include "hw/boards.h"
34#include "hw/i2c/smbus.h"
35#include "sysemu/block-backend.h"
36#include "hw/block/flash.h"
37#include "hw/mips/mips.h"
38#include "hw/mips/cpudevs.h"
39#include "hw/pci/pci.h"
40#include "sysemu/sysemu.h"
41#include "sysemu/arch_init.h"
42#include "qemu/log.h"
43#include "hw/mips/bios.h"
44#include "hw/ide.h"
45#include "hw/loader.h"
46#include "elf.h"
47#include "hw/timer/mc146818rtc.h"
48#include "hw/timer/i8254.h"
49#include "sysemu/blockdev.h"
50#include "exec/address-spaces.h"
51#include "hw/sysbus.h"
52#include "qemu/host-utils.h"
53#include "sysemu/qtest.h"
54#include "qemu/error-report.h"
55#include "hw/empty_slot.h"
56#include "sysemu/kvm.h"
57#include "exec/semihost.h"
58#include "hw/mips/cps.h"
59
60
61
62#define ENVP_ADDR 0x80002000l
63#define ENVP_NB_ENTRIES 16
64#define ENVP_ENTRY_SIZE 256
65
66
67#define FLASH_ADDRESS 0x1e000000ULL
68#define FPGA_ADDRESS 0x1f000000ULL
69#define RESET_ADDRESS 0x1fc00000ULL
70
71#define FLASH_SIZE 0x400000
72
73#define MAX_IDE_BUS 2
74
75typedef struct {
76 MemoryRegion iomem;
77 MemoryRegion iomem_lo;
78 MemoryRegion iomem_hi;
79 uint32_t leds;
80 uint32_t brk;
81 uint32_t gpout;
82 uint32_t i2cin;
83 uint32_t i2coe;
84 uint32_t i2cout;
85 uint32_t i2csel;
86 CharBackend display;
87 char display_text[9];
88 SerialState *uart;
89 bool display_inited;
90} MaltaFPGAState;
91
92#define TYPE_MIPS_MALTA "mips-malta"
93#define MIPS_MALTA(obj) OBJECT_CHECK(MaltaState, (obj), TYPE_MIPS_MALTA)
94
95typedef struct {
96 SysBusDevice parent_obj;
97
98 MIPSCPSState *cps;
99 qemu_irq *i8259;
100} MaltaState;
101
102static ISADevice *pit;
103
104static struct _loaderparams {
105 int ram_size, ram_low_size;
106 const char *kernel_filename;
107 const char *kernel_cmdline;
108 const char *initrd_filename;
109} loaderparams;
110
111
112static void malta_fpga_update_display(void *opaque)
113{
114 char leds_text[9];
115 int i;
116 MaltaFPGAState *s = opaque;
117
118 for (i = 7 ; i >= 0 ; i--) {
119 if (s->leds & (1 << i))
120 leds_text[i] = '#';
121 else
122 leds_text[i] = ' ';
123 }
124 leds_text[8] = '\0';
125
126 qemu_chr_fe_printf(&s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n",
127 leds_text);
128 qemu_chr_fe_printf(&s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|",
129 s->display_text);
130}
131
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141
142
143
144#if defined(DEBUG)
145# define logout(fmt, ...) fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ## __VA_ARGS__)
146#else
147# define logout(fmt, ...) ((void)0)
148#endif
149
150struct _eeprom24c0x_t {
151 uint8_t tick;
152 uint8_t address;
153 uint8_t command;
154 uint8_t ack;
155 uint8_t scl;
156 uint8_t sda;
157 uint8_t data;
158
159 uint8_t contents[256];
160};
161
162typedef struct _eeprom24c0x_t eeprom24c0x_t;
163
164static eeprom24c0x_t spd_eeprom = {
165 .contents = {
166 0x80,0x08,0xFF,0x0D,0x0A,0xFF,0x40,0x00,
167 0x01,0x75,0x54,0x00,0x82,0x08,0x00,0x01,
168 0x8F,0x04,0x02,0x01,0x01,0x00,0x00,0x00,
169 0x00,0x00,0x00,0x14,0x0F,0x14,0x2D,0xFF,
170 0x15,0x08,0x15,0x08,0x00,0x00,0x00,0x00,
171 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
172 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
173 0x00,0x00,0x00,0x00,0x00,0x00,0x12,0xD0,
174 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
175 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
176 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
177 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
178 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
179 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
180 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
181 0x00,0x00,0x00,0x00,0x00,0x00,0x64,0xF4,
182 },
183};
184
185static void generate_eeprom_spd(uint8_t *eeprom, ram_addr_t ram_size)
186{
187 enum { SDR = 0x4, DDR2 = 0x8 } type;
188 uint8_t *spd = spd_eeprom.contents;
189 uint8_t nbanks = 0;
190 uint16_t density = 0;
191 int i;
192
193
194 ram_size >>= 20;
195
196 while ((ram_size >= 4) && (nbanks <= 2)) {
197 int sz_log2 = MIN(31 - clz32(ram_size), 14);
198 nbanks++;
199 density |= 1 << (sz_log2 - 2);
200 ram_size -= 1 << sz_log2;
201 }
202
203
204 if ((nbanks == 1) && (density > 1)) {
205 nbanks++;
206 density >>= 1;
207 }
208
209 if (density & 0xff00) {
210 density = (density & 0xe0) | ((density >> 8) & 0x1f);
211 type = DDR2;
212 } else if (!(density & 0x1f)) {
213 type = DDR2;
214 } else {
215 type = SDR;
216 }
217
218 if (ram_size) {
219 fprintf(stderr, "Warning: SPD cannot represent final %dMB"
220 " of SDRAM\n", (int)ram_size);
221 }
222
223
224 spd[2] = type;
225 spd[5] = nbanks;
226 spd[31] = density;
227
228
229 spd[63] = 0;
230 for (i = 0; i < 63; i++) {
231 spd[63] += spd[i];
232 }
233
234
235 memcpy(eeprom, spd, sizeof(spd_eeprom.contents));
236}
237
238static void generate_eeprom_serial(uint8_t *eeprom)
239{
240 int i, pos = 0;
241 uint8_t mac[6] = { 0x00 };
242 uint8_t sn[5] = { 0x01, 0x23, 0x45, 0x67, 0x89 };
243
244
245 eeprom[pos++] = 0x01;
246
247
248 eeprom[pos++] = 0x02;
249
250
251 eeprom[pos++] = 0x01;
252 eeprom[pos++] = 0x06;
253 memcpy(&eeprom[pos], mac, sizeof(mac));
254 pos += sizeof(mac);
255
256
257 eeprom[pos++] = 0x02;
258 eeprom[pos++] = 0x05;
259 memcpy(&eeprom[pos], sn, sizeof(sn));
260 pos += sizeof(sn);
261
262
263 eeprom[pos] = 0;
264 for (i = 0; i < pos; i++) {
265 eeprom[pos] += eeprom[i];
266 }
267}
268
269static uint8_t eeprom24c0x_read(eeprom24c0x_t *eeprom)
270{
271 logout("%u: scl = %u, sda = %u, data = 0x%02x\n",
272 eeprom->tick, eeprom->scl, eeprom->sda, eeprom->data);
273 return eeprom->sda;
274}
275
276static void eeprom24c0x_write(eeprom24c0x_t *eeprom, int scl, int sda)
277{
278 if (eeprom->scl && scl && (eeprom->sda != sda)) {
279 logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n",
280 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda,
281 sda ? "stop" : "start");
282 if (!sda) {
283 eeprom->tick = 1;
284 eeprom->command = 0;
285 }
286 } else if (eeprom->tick == 0 && !eeprom->ack) {
287
288 logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n",
289 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda);
290 } else if (!eeprom->scl && scl) {
291 logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n",
292 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda);
293 if (eeprom->ack) {
294 logout("\ti2c ack bit = 0\n");
295 sda = 0;
296 eeprom->ack = 0;
297 } else if (eeprom->sda == sda) {
298 uint8_t bit = (sda != 0);
299 logout("\ti2c bit = %d\n", bit);
300 if (eeprom->tick < 9) {
301 eeprom->command <<= 1;
302 eeprom->command += bit;
303 eeprom->tick++;
304 if (eeprom->tick == 9) {
305 logout("\tcommand 0x%04x, %s\n", eeprom->command,
306 bit ? "read" : "write");
307 eeprom->ack = 1;
308 }
309 } else if (eeprom->tick < 17) {
310 if (eeprom->command & 1) {
311 sda = ((eeprom->data & 0x80) != 0);
312 }
313 eeprom->address <<= 1;
314 eeprom->address += bit;
315 eeprom->tick++;
316 eeprom->data <<= 1;
317 if (eeprom->tick == 17) {
318 eeprom->data = eeprom->contents[eeprom->address];
319 logout("\taddress 0x%04x, data 0x%02x\n",
320 eeprom->address, eeprom->data);
321 eeprom->ack = 1;
322 eeprom->tick = 0;
323 }
324 } else if (eeprom->tick >= 17) {
325 sda = 0;
326 }
327 } else {
328 logout("\tsda changed with raising scl\n");
329 }
330 } else {
331 logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom->tick, eeprom->scl,
332 scl, eeprom->sda, sda);
333 }
334 eeprom->scl = scl;
335 eeprom->sda = sda;
336}
337
338static uint64_t malta_fpga_read(void *opaque, hwaddr addr,
339 unsigned size)
340{
341 MaltaFPGAState *s = opaque;
342 uint32_t val = 0;
343 uint32_t saddr;
344
345 saddr = (addr & 0xfffff);
346
347 switch (saddr) {
348
349
350 case 0x00200:
351 val = 0x00000000;
352 break;
353
354
355 case 0x00208:
356#ifdef TARGET_WORDS_BIGENDIAN
357 val = 0x00000012;
358#else
359 val = 0x00000010;
360#endif
361 break;
362
363
364 case 0x00210:
365 val = 0x00;
366 break;
367
368
369 case 0x00408:
370 val = s->leds;
371 break;
372
373
374 case 0x00508:
375 val = s->brk;
376 break;
377
378
379
380
381 case 0x00a00:
382 val = s->gpout;
383 break;
384
385
386
387
388 case 0x00a08:
389
390 if (s->i2csel)
391 val = s->i2cout;
392 else
393 val = 0x00;
394 break;
395
396
397 case 0x00b00:
398 val = ((s->i2cin & ~1) | eeprom24c0x_read(&spd_eeprom));
399 break;
400
401
402 case 0x00b08:
403 val = s->i2coe;
404 break;
405
406
407 case 0x00b10:
408 val = s->i2cout;
409 break;
410
411
412 case 0x00b18:
413 val = s->i2csel;
414 break;
415
416 default:
417#if 0
418 printf ("malta_fpga_read: Bad register offset 0x" TARGET_FMT_lx "\n",
419 addr);
420#endif
421 break;
422 }
423 return val;
424}
425
426static void malta_fpga_write(void *opaque, hwaddr addr,
427 uint64_t val, unsigned size)
428{
429 MaltaFPGAState *s = opaque;
430 uint32_t saddr;
431
432 saddr = (addr & 0xfffff);
433
434 switch (saddr) {
435
436
437 case 0x00200:
438 break;
439
440
441 case 0x00210:
442 break;
443
444
445 case 0x00408:
446 s->leds = val & 0xff;
447 malta_fpga_update_display(s);
448 break;
449
450
451 case 0x00410:
452 snprintf(s->display_text, 9, "%08X", (uint32_t)val);
453 malta_fpga_update_display(s);
454 break;
455
456
457 case 0x00418:
458 case 0x00420:
459 case 0x00428:
460 case 0x00430:
461 case 0x00438:
462 case 0x00440:
463 case 0x00448:
464 case 0x00450:
465 s->display_text[(saddr - 0x00418) >> 3] = (char) val;
466 malta_fpga_update_display(s);
467 break;
468
469
470 case 0x00500:
471 if (val == 0x42)
472 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
473 break;
474
475
476 case 0x00508:
477 s->brk = val & 0xff;
478 break;
479
480
481
482
483 case 0x00a00:
484 s->gpout = val & 0xff;
485 break;
486
487
488 case 0x00b08:
489 s->i2coe = val & 0x03;
490 break;
491
492
493 case 0x00b10:
494 eeprom24c0x_write(&spd_eeprom, val & 0x02, val & 0x01);
495 s->i2cout = val;
496 break;
497
498
499 case 0x00b18:
500 s->i2csel = val & 0x01;
501 break;
502
503 default:
504#if 0
505 printf ("malta_fpga_write: Bad register offset 0x" TARGET_FMT_lx "\n",
506 addr);
507#endif
508 break;
509 }
510}
511
512static const MemoryRegionOps malta_fpga_ops = {
513 .read = malta_fpga_read,
514 .write = malta_fpga_write,
515 .endianness = DEVICE_NATIVE_ENDIAN,
516};
517
518static void malta_fpga_reset(void *opaque)
519{
520 MaltaFPGAState *s = opaque;
521
522 s->leds = 0x00;
523 s->brk = 0x0a;
524 s->gpout = 0x00;
525 s->i2cin = 0x3;
526 s->i2coe = 0x0;
527 s->i2cout = 0x3;
528 s->i2csel = 0x1;
529
530 s->display_text[8] = '\0';
531 snprintf(s->display_text, 9, " ");
532}
533
534static void malta_fgpa_display_event(void *opaque, int event)
535{
536 MaltaFPGAState *s = opaque;
537
538 if (event == CHR_EVENT_OPENED && !s->display_inited) {
539 qemu_chr_fe_printf(&s->display, "\e[HMalta LEDBAR\r\n");
540 qemu_chr_fe_printf(&s->display, "+--------+\r\n");
541 qemu_chr_fe_printf(&s->display, "+ +\r\n");
542 qemu_chr_fe_printf(&s->display, "+--------+\r\n");
543 qemu_chr_fe_printf(&s->display, "\n");
544 qemu_chr_fe_printf(&s->display, "Malta ASCII\r\n");
545 qemu_chr_fe_printf(&s->display, "+--------+\r\n");
546 qemu_chr_fe_printf(&s->display, "+ +\r\n");
547 qemu_chr_fe_printf(&s->display, "+--------+\r\n");
548 s->display_inited = true;
549 }
550}
551
552static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space,
553 hwaddr base, qemu_irq uart_irq, Chardev *uart_chr)
554{
555 MaltaFPGAState *s;
556 Chardev *chr;
557
558 s = (MaltaFPGAState *)g_malloc0(sizeof(MaltaFPGAState));
559
560 memory_region_init_io(&s->iomem, NULL, &malta_fpga_ops, s,
561 "malta-fpga", 0x100000);
562 memory_region_init_alias(&s->iomem_lo, NULL, "malta-fpga",
563 &s->iomem, 0, 0x900);
564 memory_region_init_alias(&s->iomem_hi, NULL, "malta-fpga",
565 &s->iomem, 0xa00, 0x10000-0xa00);
566
567 memory_region_add_subregion(address_space, base, &s->iomem_lo);
568 memory_region_add_subregion(address_space, base + 0xa00, &s->iomem_hi);
569
570 chr = qemu_chr_new("fpga", "vc:320x200");
571 qemu_chr_fe_init(&s->display, chr, NULL);
572 qemu_chr_fe_set_handlers(&s->display, NULL, NULL,
573 malta_fgpa_display_event, NULL, s, NULL, true);
574
575 s->uart = serial_mm_init(address_space, base + 0x900, 3, uart_irq,
576 230400, uart_chr, DEVICE_NATIVE_ENDIAN);
577
578 malta_fpga_reset(s);
579 qemu_register_reset(malta_fpga_reset, s);
580
581 return s;
582}
583
584
585static void network_init(PCIBus *pci_bus)
586{
587 int i;
588
589 for(i = 0; i < nb_nics; i++) {
590 NICInfo *nd = &nd_table[i];
591 const char *default_devaddr = NULL;
592
593 if (i == 0 && (!nd->model || strcmp(nd->model, "pcnet") == 0))
594
595 default_devaddr = "0b";
596
597 pci_nic_init_nofail(nd, pci_bus, "pcnet", default_devaddr);
598 }
599}
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622
623static void write_bootloader(uint8_t *base, int64_t run_addr,
624 int64_t kernel_entry)
625{
626 uint32_t *p;
627
628
629 p = (uint32_t *)base;
630
631 stl_p(p++, 0x08000000 |
632 ((run_addr + 0x580) & 0x0fffffff) >> 2);
633 stl_p(p++, 0x00000000);
634
635
636 stl_p(base + 0x500, run_addr + 0x0580);
637 stl_p(base + 0x504, run_addr + 0x083c);
638 stl_p(base + 0x520, run_addr + 0x0580);
639 stl_p(base + 0x52c, run_addr + 0x0800);
640 stl_p(base + 0x534, run_addr + 0x0808);
641 stl_p(base + 0x538, run_addr + 0x0800);
642 stl_p(base + 0x53c, run_addr + 0x0800);
643 stl_p(base + 0x540, run_addr + 0x0800);
644 stl_p(base + 0x544, run_addr + 0x0800);
645 stl_p(base + 0x548, run_addr + 0x0800);
646 stl_p(base + 0x54c, run_addr + 0x0800);
647 stl_p(base + 0x550, run_addr + 0x0800);
648 stl_p(base + 0x554, run_addr + 0x0800);
649
650
651
652 p = (uint32_t *) (base + 0x580);
653
654 if (semihosting_get_argc()) {
655
656 stl_p(p++, 0x00000000);
657 } else {
658 stl_p(p++, 0x24040002);
659 }
660 stl_p(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff));
661 stl_p(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff));
662 stl_p(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff));
663 stl_p(p++, 0x34a50000 | (ENVP_ADDR & 0xffff));
664 stl_p(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff));
665 stl_p(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff));
666 stl_p(p++, 0x3c070000 | (loaderparams.ram_low_size >> 16));
667 stl_p(p++, 0x34e70000 | (loaderparams.ram_low_size & 0xffff));
668
669
670 stl_p(p++, 0x3c09b400);
671
672#ifdef TARGET_WORDS_BIGENDIAN
673 stl_p(p++, 0x3c08df00);
674#else
675 stl_p(p++, 0x340800df);
676#endif
677 stl_p(p++, 0xad280068);
678
679 stl_p(p++, 0x3c09bbe0);
680
681#ifdef TARGET_WORDS_BIGENDIAN
682 stl_p(p++, 0x3c08c000);
683#else
684 stl_p(p++, 0x340800c0);
685#endif
686 stl_p(p++, 0xad280048);
687#ifdef TARGET_WORDS_BIGENDIAN
688 stl_p(p++, 0x3c084000);
689#else
690 stl_p(p++, 0x34080040);
691#endif
692 stl_p(p++, 0xad280050);
693
694#ifdef TARGET_WORDS_BIGENDIAN
695 stl_p(p++, 0x3c088000);
696#else
697 stl_p(p++, 0x34080080);
698#endif
699 stl_p(p++, 0xad280058);
700#ifdef TARGET_WORDS_BIGENDIAN
701 stl_p(p++, 0x3c083f00);
702#else
703 stl_p(p++, 0x3408003f);
704#endif
705 stl_p(p++, 0xad280060);
706
707#ifdef TARGET_WORDS_BIGENDIAN
708 stl_p(p++, 0x3c08c100);
709#else
710 stl_p(p++, 0x340800c1);
711#endif
712 stl_p(p++, 0xad280080);
713#ifdef TARGET_WORDS_BIGENDIAN
714 stl_p(p++, 0x3c085e00);
715#else
716 stl_p(p++, 0x3408005e);
717#endif
718 stl_p(p++, 0xad280088);
719
720
721 stl_p(p++, 0x3c1f0000 | ((kernel_entry >> 16) & 0xffff));
722 stl_p(p++, 0x37ff0000 | (kernel_entry & 0xffff));
723 stl_p(p++, 0x03e00009);
724 stl_p(p++, 0x00000000);
725
726
727 p = (uint32_t *) (base + 0x800);
728 stl_p(p++, 0x03e00009);
729 stl_p(p++, 0x24020000);
730
731 stl_p(p++, 0x03e06821);
732 stl_p(p++, 0x00805821);
733 stl_p(p++, 0x00a05021);
734 stl_p(p++, 0x91440000);
735 stl_p(p++, 0x254a0001);
736 stl_p(p++, 0x10800005);
737 stl_p(p++, 0x00000000);
738 stl_p(p++, 0x0ff0021c);
739 stl_p(p++, 0x00000000);
740 stl_p(p++, 0x1000fff9);
741 stl_p(p++, 0x00000000);
742 stl_p(p++, 0x01a00009);
743 stl_p(p++, 0x01602021);
744
745 stl_p(p++, 0x03e06821);
746 stl_p(p++, 0x00805821);
747 stl_p(p++, 0x00a05021);
748 stl_p(p++, 0x00c06021);
749 stl_p(p++, 0x91440000);
750 stl_p(p++, 0x0ff0021c);
751 stl_p(p++, 0x00000000);
752 stl_p(p++, 0x254a0001);
753 stl_p(p++, 0x258cffff);
754 stl_p(p++, 0x1580fffa);
755 stl_p(p++, 0x00000000);
756 stl_p(p++, 0x01a00009);
757 stl_p(p++, 0x01602021);
758
759 stl_p(p++, 0x3c08b800);
760 stl_p(p++, 0x350803f8);
761 stl_p(p++, 0x91090005);
762 stl_p(p++, 0x00000000);
763 stl_p(p++, 0x31290040);
764 stl_p(p++, 0x1120fffc);
765 stl_p(p++, 0x00000000);
766 stl_p(p++, 0x03e00009);
767 stl_p(p++, 0xa1040000);
768
769}
770
771static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf, int index,
772 const char *string, ...)
773{
774 va_list ap;
775 int32_t table_addr;
776
777 if (index >= ENVP_NB_ENTRIES)
778 return;
779
780 if (string == NULL) {
781 prom_buf[index] = 0;
782 return;
783 }
784
785 table_addr = sizeof(int32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE;
786 prom_buf[index] = tswap32(ENVP_ADDR + table_addr);
787
788 va_start(ap, string);
789 vsnprintf((char *)prom_buf + table_addr, ENVP_ENTRY_SIZE, string, ap);
790 va_end(ap);
791}
792
793
794static int64_t load_kernel (void)
795{
796 int64_t kernel_entry, kernel_high;
797 long kernel_size, initrd_size;
798 ram_addr_t initrd_offset;
799 int big_endian;
800 uint32_t *prom_buf;
801 long prom_size;
802 int prom_index = 0;
803 uint64_t (*xlate_to_kseg0) (void *opaque, uint64_t addr);
804
805#ifdef TARGET_WORDS_BIGENDIAN
806 big_endian = 1;
807#else
808 big_endian = 0;
809#endif
810
811 kernel_size = load_elf(loaderparams.kernel_filename, cpu_mips_kseg0_to_phys,
812 NULL, (uint64_t *)&kernel_entry, NULL,
813 (uint64_t *)&kernel_high, big_endian, EM_MIPS, 1, 0);
814 if (kernel_size < 0) {
815 error_report("qemu: could not load kernel '%s': %s",
816 loaderparams.kernel_filename,
817 load_elf_strerror(kernel_size));
818 exit(1);
819 }
820
821
822 if (kernel_entry & 0x80000000ll) {
823 if (kvm_enabled()) {
824 error_report("KVM guest kernels must be linked in useg. "
825 "Did you forget to enable CONFIG_KVM_GUEST?");
826 exit(1);
827 }
828
829 xlate_to_kseg0 = cpu_mips_phys_to_kseg0;
830 } else {
831
832 mips_um_ksegs_enable();
833
834 xlate_to_kseg0 = cpu_mips_kvm_um_phys_to_kseg0;
835 }
836
837
838 initrd_size = 0;
839 initrd_offset = 0;
840 if (loaderparams.initrd_filename) {
841 initrd_size = get_image_size (loaderparams.initrd_filename);
842 if (initrd_size > 0) {
843
844
845
846 initrd_offset = (loaderparams.ram_low_size - initrd_size - 131072
847 - ~INITRD_PAGE_MASK) & INITRD_PAGE_MASK;
848 if (kernel_high >= initrd_offset) {
849 fprintf(stderr,
850 "qemu: memory too small for initial ram disk '%s'\n",
851 loaderparams.initrd_filename);
852 exit(1);
853 }
854 initrd_size = load_image_targphys(loaderparams.initrd_filename,
855 initrd_offset,
856 ram_size - initrd_offset);
857 }
858 if (initrd_size == (target_ulong) -1) {
859 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
860 loaderparams.initrd_filename);
861 exit(1);
862 }
863 }
864
865
866 prom_size = ENVP_NB_ENTRIES * (sizeof(int32_t) + ENVP_ENTRY_SIZE);
867 prom_buf = g_malloc(prom_size);
868
869 prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_filename);
870 if (initrd_size > 0) {
871 prom_set(prom_buf, prom_index++, "rd_start=0x%" PRIx64 " rd_size=%li %s",
872 xlate_to_kseg0(NULL, initrd_offset), initrd_size,
873 loaderparams.kernel_cmdline);
874 } else {
875 prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_cmdline);
876 }
877
878 prom_set(prom_buf, prom_index++, "memsize");
879 prom_set(prom_buf, prom_index++, "%u", loaderparams.ram_low_size);
880
881 prom_set(prom_buf, prom_index++, "ememsize");
882 prom_set(prom_buf, prom_index++, "%u", loaderparams.ram_size);
883
884 prom_set(prom_buf, prom_index++, "modetty0");
885 prom_set(prom_buf, prom_index++, "38400n8r");
886 prom_set(prom_buf, prom_index++, NULL);
887
888 rom_add_blob_fixed("prom", prom_buf, prom_size,
889 cpu_mips_kseg0_to_phys(NULL, ENVP_ADDR));
890
891 g_free(prom_buf);
892 return kernel_entry;
893}
894
895static void malta_mips_config(MIPSCPU *cpu)
896{
897 CPUMIPSState *env = &cpu->env;
898 CPUState *cs = CPU(cpu);
899
900 env->mvp->CP0_MVPConf0 |= ((smp_cpus - 1) << CP0MVPC0_PVPE) |
901 ((smp_cpus * cs->nr_threads - 1) << CP0MVPC0_PTC);
902}
903
904static void main_cpu_reset(void *opaque)
905{
906 MIPSCPU *cpu = opaque;
907 CPUMIPSState *env = &cpu->env;
908
909 cpu_reset(CPU(cpu));
910
911
912
913
914 if (loaderparams.kernel_filename) {
915 env->CP0_Status &= ~(1 << CP0St_ERL);
916 }
917
918 malta_mips_config(cpu);
919
920 if (kvm_enabled()) {
921
922 env->active_tc.PC = 0x40000000 + loaderparams.ram_low_size;
923 }
924}
925
926static void create_cpu_without_cps(const char *cpu_model,
927 qemu_irq *cbus_irq, qemu_irq *i8259_irq)
928{
929 CPUMIPSState *env;
930 MIPSCPU *cpu;
931 int i;
932
933 for (i = 0; i < smp_cpus; i++) {
934 cpu = cpu_mips_init(cpu_model);
935 if (cpu == NULL) {
936 fprintf(stderr, "Unable to find CPU definition\n");
937 exit(1);
938 }
939
940
941 cpu_mips_irq_init_cpu(cpu);
942 cpu_mips_clock_init(cpu);
943 qemu_register_reset(main_cpu_reset, cpu);
944 }
945
946 cpu = MIPS_CPU(first_cpu);
947 env = &cpu->env;
948 *i8259_irq = env->irq[2];
949 *cbus_irq = env->irq[4];
950}
951
952static void create_cps(MaltaState *s, const char *cpu_model,
953 qemu_irq *cbus_irq, qemu_irq *i8259_irq)
954{
955 Error *err = NULL;
956 s->cps = g_new0(MIPSCPSState, 1);
957
958 object_initialize(s->cps, sizeof(MIPSCPSState), TYPE_MIPS_CPS);
959 qdev_set_parent_bus(DEVICE(s->cps), sysbus_get_default());
960
961 object_property_set_str(OBJECT(s->cps), cpu_model, "cpu-model", &err);
962 object_property_set_int(OBJECT(s->cps), smp_cpus, "num-vp", &err);
963 object_property_set_bool(OBJECT(s->cps), true, "realized", &err);
964 if (err != NULL) {
965 error_report("%s", error_get_pretty(err));
966 exit(1);
967 }
968
969 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(s->cps), 0, 0, 1);
970
971 *i8259_irq = get_cps_irq(s->cps, 3);
972 *cbus_irq = NULL;
973}
974
975static void create_cpu(MaltaState *s, const char *cpu_model,
976 qemu_irq *cbus_irq, qemu_irq *i8259_irq)
977{
978 if (cpu_model == NULL) {
979#ifdef TARGET_MIPS64
980 cpu_model = "20Kc";
981#else
982 cpu_model = "24Kf";
983#endif
984 }
985
986 if ((smp_cpus > 1) && cpu_supports_cps_smp(cpu_model)) {
987 create_cps(s, cpu_model, cbus_irq, i8259_irq);
988 } else {
989 create_cpu_without_cps(cpu_model, cbus_irq, i8259_irq);
990 }
991}
992
993static
994void mips_malta_init(MachineState *machine)
995{
996 ram_addr_t ram_size = machine->ram_size;
997 ram_addr_t ram_low_size;
998 const char *kernel_filename = machine->kernel_filename;
999 const char *kernel_cmdline = machine->kernel_cmdline;
1000 const char *initrd_filename = machine->initrd_filename;
1001 char *filename;
1002 pflash_t *fl;
1003 MemoryRegion *system_memory = get_system_memory();
1004 MemoryRegion *ram_high = g_new(MemoryRegion, 1);
1005 MemoryRegion *ram_low_preio = g_new(MemoryRegion, 1);
1006 MemoryRegion *ram_low_postio;
1007 MemoryRegion *bios, *bios_copy = g_new(MemoryRegion, 1);
1008 target_long bios_size = FLASH_SIZE;
1009 const size_t smbus_eeprom_size = 8 * 256;
1010 uint8_t *smbus_eeprom_buf = g_malloc0(smbus_eeprom_size);
1011 int64_t kernel_entry, bootloader_run_addr;
1012 PCIBus *pci_bus;
1013 ISABus *isa_bus;
1014 qemu_irq *isa_irq;
1015 qemu_irq cbus_irq, i8259_irq;
1016 int piix4_devfn;
1017 I2CBus *smbus;
1018 int i;
1019 DriveInfo *dinfo;
1020 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
1021 DriveInfo *fd[MAX_FD];
1022 int fl_idx = 0;
1023 int fl_sectors = bios_size >> 16;
1024 int be;
1025
1026 DeviceState *dev = qdev_create(NULL, TYPE_MIPS_MALTA);
1027 MaltaState *s = MIPS_MALTA(dev);
1028
1029
1030
1031
1032 empty_slot_init(0, 0x20000000);
1033
1034 qdev_init_nofail(dev);
1035
1036
1037 for(i = 0; i < 3; i++) {
1038 if (!serial_hds[i]) {
1039 char label[32];
1040 snprintf(label, sizeof(label), "serial%d", i);
1041 serial_hds[i] = qemu_chr_new(label, "null");
1042 }
1043 }
1044
1045
1046 create_cpu(s, machine->cpu_model, &cbus_irq, &i8259_irq);
1047
1048
1049 if (ram_size > (2048u << 20)) {
1050 fprintf(stderr,
1051 "qemu: Too much memory for this machine: %d MB, maximum 2048 MB\n",
1052 ((unsigned int)ram_size / (1 << 20)));
1053 exit(1);
1054 }
1055
1056
1057 memory_region_allocate_system_memory(ram_high, NULL, "mips_malta.ram",
1058 ram_size);
1059 memory_region_add_subregion(system_memory, 0x80000000, ram_high);
1060
1061
1062 memory_region_init_alias(ram_low_preio, NULL, "mips_malta_low_preio.ram",
1063 ram_high, 0, MIN(ram_size, (256 << 20)));
1064 memory_region_add_subregion(system_memory, 0, ram_low_preio);
1065
1066
1067 if (ram_size > (512 << 20)) {
1068 ram_low_postio = g_new(MemoryRegion, 1);
1069 memory_region_init_alias(ram_low_postio, NULL,
1070 "mips_malta_low_postio.ram",
1071 ram_high, 512 << 20,
1072 ram_size - (512 << 20));
1073 memory_region_add_subregion(system_memory, 512 << 20, ram_low_postio);
1074 }
1075
1076
1077 generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size);
1078 generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]);
1079
1080#ifdef TARGET_WORDS_BIGENDIAN
1081 be = 1;
1082#else
1083 be = 0;
1084#endif
1085
1086
1087 malta_fpga_init(system_memory, FPGA_ADDRESS, cbus_irq, serial_hds[2]);
1088
1089
1090 dinfo = drive_get(IF_PFLASH, 0, fl_idx);
1091#ifdef DEBUG_BOARD_INIT
1092 if (dinfo) {
1093 printf("Register parallel flash %d size " TARGET_FMT_lx " at "
1094 "addr %08llx '%s' %x\n",
1095 fl_idx, bios_size, FLASH_ADDRESS,
1096 blk_name(dinfo->bdrv), fl_sectors);
1097 }
1098#endif
1099 fl = pflash_cfi01_register(FLASH_ADDRESS, NULL, "mips_malta.bios",
1100 BIOS_SIZE,
1101 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
1102 65536, fl_sectors,
1103 4, 0x0000, 0x0000, 0x0000, 0x0000, be);
1104 bios = pflash_cfi01_get_memory(fl);
1105 fl_idx++;
1106 if (kernel_filename) {
1107 ram_low_size = MIN(ram_size, 256 << 20);
1108
1109 if (kvm_enabled()) {
1110 ram_low_size -= 0x100000;
1111 bootloader_run_addr = 0x40000000 + ram_low_size;
1112 } else {
1113 bootloader_run_addr = 0xbfc00000;
1114 }
1115
1116
1117 loaderparams.ram_size = ram_size;
1118 loaderparams.ram_low_size = ram_low_size;
1119 loaderparams.kernel_filename = kernel_filename;
1120 loaderparams.kernel_cmdline = kernel_cmdline;
1121 loaderparams.initrd_filename = initrd_filename;
1122 kernel_entry = load_kernel();
1123
1124 write_bootloader(memory_region_get_ram_ptr(bios),
1125 bootloader_run_addr, kernel_entry);
1126 if (kvm_enabled()) {
1127
1128 write_bootloader(memory_region_get_ram_ptr(ram_low_preio) +
1129 ram_low_size,
1130 bootloader_run_addr, kernel_entry);
1131 }
1132 } else {
1133
1134 if (kvm_enabled()) {
1135 error_report("KVM enabled but no -kernel argument was specified. "
1136 "Booting from flash is not supported with KVM.");
1137 exit(1);
1138 }
1139
1140 if (!dinfo) {
1141
1142 if (bios_name == NULL) {
1143 bios_name = BIOS_FILENAME;
1144 }
1145 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1146 if (filename) {
1147 bios_size = load_image_targphys(filename, FLASH_ADDRESS,
1148 BIOS_SIZE);
1149 g_free(filename);
1150 } else {
1151 bios_size = -1;
1152 }
1153 if ((bios_size < 0 || bios_size > BIOS_SIZE) &&
1154 !kernel_filename && !qtest_enabled()) {
1155 error_report("Could not load MIPS bios '%s', and no "
1156 "-kernel argument was specified", bios_name);
1157 exit(1);
1158 }
1159 }
1160
1161
1162#ifndef TARGET_WORDS_BIGENDIAN
1163 {
1164 uint32_t *end, *addr = rom_ptr(FLASH_ADDRESS);
1165 if (!addr) {
1166 addr = memory_region_get_ram_ptr(bios);
1167 }
1168 end = (void *)addr + MIN(bios_size, 0x3e0000);
1169 while (addr < end) {
1170 bswap32s(addr);
1171 addr++;
1172 }
1173 }
1174#endif
1175 }
1176
1177
1178
1179
1180
1181
1182
1183 memory_region_init_ram_nomigrate(bios_copy, NULL, "bios.1fc", BIOS_SIZE,
1184 &error_fatal);
1185 if (!rom_copy(memory_region_get_ram_ptr(bios_copy),
1186 FLASH_ADDRESS, BIOS_SIZE)) {
1187 memcpy(memory_region_get_ram_ptr(bios_copy),
1188 memory_region_get_ram_ptr(bios), BIOS_SIZE);
1189 }
1190 memory_region_set_readonly(bios_copy, true);
1191 memory_region_add_subregion(system_memory, RESET_ADDRESS, bios_copy);
1192
1193
1194 stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
1195
1196
1197
1198
1199
1200
1201
1202
1203 isa_irq = qemu_irq_proxy(&s->i8259, 16);
1204
1205
1206 pci_bus = gt64120_register(isa_irq);
1207
1208
1209 ide_drive_get(hd, ARRAY_SIZE(hd));
1210
1211 piix4_devfn = piix4_init(pci_bus, &isa_bus, 80);
1212
1213
1214
1215 s->i8259 = i8259_init(isa_bus, i8259_irq);
1216
1217 isa_bus_irqs(isa_bus, s->i8259);
1218 pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
1219 pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
1220 smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
1221 isa_get_irq(NULL, 9), NULL, 0, NULL);
1222 smbus_eeprom_init(smbus, 8, smbus_eeprom_buf, smbus_eeprom_size);
1223 g_free(smbus_eeprom_buf);
1224 pit = pit_init(isa_bus, 0x40, 0, NULL);
1225 DMA_init(isa_bus, 0);
1226
1227
1228 isa_create_simple(isa_bus, "i8042");
1229
1230 rtc_init(isa_bus, 2000, NULL);
1231 serial_hds_isa_init(isa_bus, 0, 2);
1232 parallel_hds_isa_init(isa_bus, 1);
1233
1234 for(i = 0; i < MAX_FD; i++) {
1235 fd[i] = drive_get(IF_FLOPPY, 0, i);
1236 }
1237 fdctrl_init_isa(isa_bus, fd);
1238
1239
1240 network_init(pci_bus);
1241
1242
1243 pci_vga_init(pci_bus);
1244}
1245
1246static int mips_malta_sysbus_device_init(SysBusDevice *sysbusdev)
1247{
1248 return 0;
1249}
1250
1251static void mips_malta_class_init(ObjectClass *klass, void *data)
1252{
1253 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1254
1255 k->init = mips_malta_sysbus_device_init;
1256}
1257
1258static const TypeInfo mips_malta_device = {
1259 .name = TYPE_MIPS_MALTA,
1260 .parent = TYPE_SYS_BUS_DEVICE,
1261 .instance_size = sizeof(MaltaState),
1262 .class_init = mips_malta_class_init,
1263};
1264
1265static void mips_malta_machine_init(MachineClass *mc)
1266{
1267 mc->desc = "MIPS Malta Core LV";
1268 mc->init = mips_malta_init;
1269 mc->block_default_type = IF_IDE;
1270 mc->max_cpus = 16;
1271 mc->is_default = 1;
1272}
1273
1274DEFINE_MACHINE("malta", mips_malta_machine_init)
1275
1276static void mips_malta_register_types(void)
1277{
1278 type_register_static(&mips_malta_device);
1279}
1280
1281type_init(mips_malta_register_types)
1282