LXR qemu/hw/ppc/mac.h

   1/*
   2 * QEMU PowerMac emulation shared definitions and prototypes
   3 *
   4 * Copyright (c) 2004-2007 Fabrice Bellard
   5 * Copyright (c) 2007 Jocelyn Mayer
   6 *
   7 * Permission is hereby granted, free of charge, to any person obtaining a copy
   8 * of this software and associated documentation files (the "Software"), to deal
   9 * in the Software without restriction, including without limitation the rights
  10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11 * copies of the Software, and to permit persons to whom the Software is
  12 * furnished to do so, subject to the following conditions:
  13 *
  14 * The above copyright notice and this permission notice shall be included in
  15 * all copies or substantial portions of the Software.
  16 *
  17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23 * THE SOFTWARE.
  24 */
  25
  26#ifndef PPC_MAC_H
  27#define PPC_MAC_H
  28
  29#include "exec/memory.h"
  30#include "hw/sysbus.h"
  31#include "hw/ide/internal.h"
  32#include "hw/input/adb.h"
  33
  34/* SMP is not enabled, for now */
  35#define MAX_CPUS 1
  36
  37#define BIOS_SIZE     (1024 * 1024)
  38#define NVRAM_SIZE        0x2000
  39#define PROM_FILENAME    "openbios-ppc"
  40#define PROM_ADDR         0xfff00000
  41
  42#define KERNEL_LOAD_ADDR 0x01000000
  43#define KERNEL_GAP       0x00100000
  44
  45#define ESCC_CLOCK 3686400
  46
  47/* Cuda */
  48#define TYPE_CUDA "cuda"
  49#define CUDA(obj) OBJECT_CHECK(CUDAState, (obj), TYPE_CUDA)
  50
  51/**
  52 * CUDATimer:
  53 * @counter_value: counter value at load time
  54 */
  55typedef struct CUDATimer {
  56    int index;
  57    uint16_t latch;
  58    uint16_t counter_value;
  59    int64_t load_time;
  60    int64_t next_irq_time;
  61    uint64_t frequency;
  62    QEMUTimer *timer;
  63} CUDATimer;
  64
  65/**
  66 * CUDAState:
  67 * @b: B-side data
  68 * @a: A-side data
  69 * @dirb: B-side direction (1=output)
  70 * @dira: A-side direction (1=output)
  71 * @sr: Shift register
  72 * @acr: Auxiliary control register
  73 * @pcr: Peripheral control register
  74 * @ifr: Interrupt flag register
  75 * @ier: Interrupt enable register
  76 * @anh: A-side data, no handshake
  77 * @last_b: last value of B register
  78 * @last_acr: last value of ACR register
  79 */
  80typedef struct CUDAState {
  81    /*< private >*/
  82    SysBusDevice parent_obj;
  83    /*< public >*/
  84
  85    MemoryRegion mem;
  86    /* cuda registers */
  87    uint8_t b;
  88    uint8_t a;
  89    uint8_t dirb;
  90    uint8_t dira;
  91    uint8_t sr;
  92    uint8_t acr;
  93    uint8_t pcr;
  94    uint8_t ifr;
  95    uint8_t ier;
  96    uint8_t anh;
  97
  98    ADBBusState adb_bus;
  99    CUDATimer timers[2];
 100
 101    uint32_t tick_offset;
 102    uint64_t frequency;
 103
 104    uint8_t last_b;
 105    uint8_t last_acr;
 106
 107    /* MacOS 9 is racy and requires a delay upon setting the SR_INT bit */
 108    QEMUTimer *sr_delay_timer;
 109
 110    int data_in_size;
 111    int data_in_index;
 112    int data_out_index;
 113
 114    qemu_irq irq;
 115    uint16_t adb_poll_mask;
 116    uint8_t autopoll_rate_ms;
 117    uint8_t autopoll;
 118    uint8_t data_in[128];
 119    uint8_t data_out[16];
 120    QEMUTimer *adb_poll_timer;
 121} CUDAState;
 122
 123/* MacIO */
 124#define TYPE_OLDWORLD_MACIO "macio-oldworld"
 125#define TYPE_NEWWORLD_MACIO "macio-newworld"
 126
 127#define TYPE_MACIO_IDE "macio-ide"
 128#define MACIO_IDE(obj) OBJECT_CHECK(MACIOIDEState, (obj), TYPE_MACIO_IDE)
 129
 130typedef struct MACIOIDEState {
 131    /*< private >*/
 132    SysBusDevice parent_obj;
 133    /*< public >*/
 134
 135    qemu_irq irq;
 136    qemu_irq dma_irq;
 137
 138    MemoryRegion mem;
 139    IDEBus bus;
 140    IDEDMA dma;
 141    void *dbdma;
 142    bool dma_active;
 143} MACIOIDEState;
 144
 145void macio_ide_init_drives(MACIOIDEState *ide, DriveInfo **hd_table);
 146void macio_ide_register_dma(MACIOIDEState *ide, void *dbdma, int channel);
 147
 148void macio_init(PCIDevice *dev,
 149                MemoryRegion *pic_mem,
 150                MemoryRegion *escc_mem);
 151
 152/* Heathrow PIC */
 153qemu_irq *heathrow_pic_init(MemoryRegion **pmem,
 154                            int nb_cpus, qemu_irq **irqs);
 155
 156/* Grackle PCI */
 157#define TYPE_GRACKLE_PCI_HOST_BRIDGE "grackle-pcihost"
 158PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic,
 159                         MemoryRegion *address_space_mem,
 160                         MemoryRegion *address_space_io);
 161
 162/* UniNorth PCI */
 163PCIBus *pci_pmac_init(qemu_irq *pic,
 164                      MemoryRegion *address_space_mem,
 165                      MemoryRegion *address_space_io);
 166PCIBus *pci_pmac_u3_init(qemu_irq *pic,
 167                         MemoryRegion *address_space_mem,
 168                         MemoryRegion *address_space_io);
 169
 170/* Mac NVRAM */
 171#define TYPE_MACIO_NVRAM "macio-nvram"
 172#define MACIO_NVRAM(obj) \
 173    OBJECT_CHECK(MacIONVRAMState, (obj), TYPE_MACIO_NVRAM)
 174
 175typedef struct MacIONVRAMState {
 176    /*< private >*/
 177    SysBusDevice parent_obj;
 178    /*< public >*/
 179
 180    uint32_t size;
 181    uint32_t it_shift;
 182
 183    MemoryRegion mem;
 184    uint8_t *data;
 185} MacIONVRAMState;
 186
 187void pmac_format_nvram_partition (MacIONVRAMState *nvr, int len);
 188#endif /* PPC_MAC_H */
 189