qemu/hw/ppc/pnv_xscom.c
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   1/*
   2 * QEMU PowerPC PowerNV XSCOM bus
   3 *
   4 * Copyright (c) 2016, IBM Corporation.
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19#include "qemu/osdep.h"
  20#include "qapi/error.h"
  21#include "hw/hw.h"
  22#include "qemu/log.h"
  23#include "sysemu/hw_accel.h"
  24#include "target/ppc/cpu.h"
  25#include "hw/sysbus.h"
  26
  27#include "hw/ppc/fdt.h"
  28#include "hw/ppc/pnv.h"
  29#include "hw/ppc/pnv_xscom.h"
  30
  31#include <libfdt.h>
  32
  33static void xscom_complete(CPUState *cs, uint64_t hmer_bits)
  34{
  35    /*
  36     * TODO: When the read/write comes from the monitor, NULL is
  37     * passed for the cpu, and no CPU completion is generated.
  38     */
  39    if (cs) {
  40        PowerPCCPU *cpu = POWERPC_CPU(cs);
  41        CPUPPCState *env = &cpu->env;
  42
  43        /*
  44         * TODO: Need a CPU helper to set HMER, also handle generation
  45         * of HMIs
  46         */
  47        cpu_synchronize_state(cs);
  48        env->spr[SPR_HMER] |= hmer_bits;
  49    }
  50}
  51
  52static uint32_t pnv_xscom_pcba(PnvChip *chip, uint64_t addr)
  53{
  54    PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
  55
  56    addr &= (PNV_XSCOM_SIZE - 1);
  57    if (pcc->chip_type == PNV_CHIP_POWER9) {
  58        return addr >> 3;
  59    } else {
  60        return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf);
  61    }
  62}
  63
  64static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba)
  65{
  66    switch (pcba) {
  67    case 0xf000f:
  68        return PNV_CHIP_GET_CLASS(chip)->chip_cfam_id;
  69    case 0x1010c00:     /* PIBAM FIR */
  70    case 0x1010c03:     /* PIBAM FIR MASK */
  71    case 0x2020007:     /* ADU stuff */
  72    case 0x2020009:     /* ADU stuff */
  73    case 0x202000f:     /* ADU stuff */
  74        return 0;
  75    case 0x2013f00:     /* PBA stuff */
  76    case 0x2013f01:     /* PBA stuff */
  77    case 0x2013f02:     /* PBA stuff */
  78    case 0x2013f03:     /* PBA stuff */
  79    case 0x2013f04:     /* PBA stuff */
  80    case 0x2013f05:     /* PBA stuff */
  81    case 0x2013f06:     /* PBA stuff */
  82    case 0x2013f07:     /* PBA stuff */
  83        return 0;
  84    case 0x2013028:     /* CAPP stuff */
  85    case 0x201302a:     /* CAPP stuff */
  86    case 0x2013801:     /* CAPP stuff */
  87    case 0x2013802:     /* CAPP stuff */
  88        return 0;
  89    default:
  90        return -1;
  91    }
  92}
  93
  94static bool xscom_write_default(PnvChip *chip, uint32_t pcba, uint64_t val)
  95{
  96    /* We ignore writes to these */
  97    switch (pcba) {
  98    case 0xf000f:       /* chip id is RO */
  99    case 0x1010c00:     /* PIBAM FIR */
 100    case 0x1010c01:     /* PIBAM FIR */
 101    case 0x1010c02:     /* PIBAM FIR */
 102    case 0x1010c03:     /* PIBAM FIR MASK */
 103    case 0x1010c04:     /* PIBAM FIR MASK */
 104    case 0x1010c05:     /* PIBAM FIR MASK */
 105    case 0x2020007:     /* ADU stuff */
 106    case 0x2020009:     /* ADU stuff */
 107    case 0x202000f:     /* ADU stuff */
 108        return true;
 109    default:
 110        return false;
 111    }
 112}
 113
 114static uint64_t xscom_read(void *opaque, hwaddr addr, unsigned width)
 115{
 116    PnvChip *chip = opaque;
 117    uint32_t pcba = pnv_xscom_pcba(chip, addr);
 118    uint64_t val = 0;
 119    MemTxResult result;
 120
 121    /* Handle some SCOMs here before dispatch */
 122    val = xscom_read_default(chip, pcba);
 123    if (val != -1) {
 124        goto complete;
 125    }
 126
 127    val = address_space_ldq(&chip->xscom_as, (uint64_t) pcba << 3,
 128                            MEMTXATTRS_UNSPECIFIED, &result);
 129    if (result != MEMTX_OK) {
 130        qemu_log_mask(LOG_GUEST_ERROR, "XSCOM read failed at @0x%"
 131                      HWADDR_PRIx " pcba=0x%08x\n", addr, pcba);
 132        xscom_complete(current_cpu, HMER_XSCOM_FAIL | HMER_XSCOM_DONE);
 133        return 0;
 134    }
 135
 136complete:
 137    xscom_complete(current_cpu, HMER_XSCOM_DONE);
 138    return val;
 139}
 140
 141static void xscom_write(void *opaque, hwaddr addr, uint64_t val,
 142                        unsigned width)
 143{
 144    PnvChip *chip = opaque;
 145    uint32_t pcba = pnv_xscom_pcba(chip, addr);
 146    MemTxResult result;
 147
 148    /* Handle some SCOMs here before dispatch */
 149    if (xscom_write_default(chip, pcba, val)) {
 150        goto complete;
 151    }
 152
 153    address_space_stq(&chip->xscom_as, (uint64_t) pcba << 3, val,
 154                      MEMTXATTRS_UNSPECIFIED, &result);
 155    if (result != MEMTX_OK) {
 156        qemu_log_mask(LOG_GUEST_ERROR, "XSCOM write failed at @0x%"
 157                      HWADDR_PRIx " pcba=0x%08x data=0x%" PRIx64 "\n",
 158                      addr, pcba, val);
 159        xscom_complete(current_cpu, HMER_XSCOM_FAIL | HMER_XSCOM_DONE);
 160        return;
 161    }
 162
 163complete:
 164    xscom_complete(current_cpu, HMER_XSCOM_DONE);
 165}
 166
 167const MemoryRegionOps pnv_xscom_ops = {
 168    .read = xscom_read,
 169    .write = xscom_write,
 170    .valid.min_access_size = 8,
 171    .valid.max_access_size = 8,
 172    .impl.min_access_size = 8,
 173    .impl.max_access_size = 8,
 174    .endianness = DEVICE_BIG_ENDIAN,
 175};
 176
 177void pnv_xscom_realize(PnvChip *chip, Error **errp)
 178{
 179    SysBusDevice *sbd = SYS_BUS_DEVICE(chip);
 180    char *name;
 181
 182    name = g_strdup_printf("xscom-%x", chip->chip_id);
 183    memory_region_init_io(&chip->xscom_mmio, OBJECT(chip), &pnv_xscom_ops,
 184                          chip, name, PNV_XSCOM_SIZE);
 185    sysbus_init_mmio(sbd, &chip->xscom_mmio);
 186
 187    memory_region_init(&chip->xscom, OBJECT(chip), name, PNV_XSCOM_SIZE);
 188    address_space_init(&chip->xscom_as, &chip->xscom, name);
 189    g_free(name);
 190}
 191
 192static const TypeInfo pnv_xscom_interface_info = {
 193    .name = TYPE_PNV_XSCOM_INTERFACE,
 194    .parent = TYPE_INTERFACE,
 195    .class_size = sizeof(PnvXScomInterfaceClass),
 196};
 197
 198static void pnv_xscom_register_types(void)
 199{
 200    type_register_static(&pnv_xscom_interface_info);
 201}
 202
 203type_init(pnv_xscom_register_types)
 204
 205typedef struct ForeachPopulateArgs {
 206    void *fdt;
 207    int xscom_offset;
 208} ForeachPopulateArgs;
 209
 210static int xscom_populate_child(Object *child, void *opaque)
 211{
 212    if (object_dynamic_cast(child, TYPE_PNV_XSCOM_INTERFACE)) {
 213        ForeachPopulateArgs *args = opaque;
 214        PnvXScomInterface *xd = PNV_XSCOM_INTERFACE(child);
 215        PnvXScomInterfaceClass *xc = PNV_XSCOM_INTERFACE_GET_CLASS(xd);
 216
 217        if (xc->populate) {
 218            _FDT((xc->populate(xd, args->fdt, args->xscom_offset)));
 219        }
 220    }
 221    return 0;
 222}
 223
 224static const char compat_p8[] = "ibm,power8-xscom\0ibm,xscom";
 225static const char compat_p9[] = "ibm,power9-xscom\0ibm,xscom";
 226
 227int pnv_xscom_populate(PnvChip *chip, void *fdt, int root_offset)
 228{
 229    uint64_t reg[] = { cpu_to_be64(PNV_XSCOM_BASE(chip)),
 230                       cpu_to_be64(PNV_XSCOM_SIZE) };
 231    int xscom_offset;
 232    ForeachPopulateArgs args;
 233    char *name;
 234    PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
 235
 236    name = g_strdup_printf("xscom@%" PRIx64, be64_to_cpu(reg[0]));
 237    xscom_offset = fdt_add_subnode(fdt, root_offset, name);
 238    _FDT(xscom_offset);
 239    g_free(name);
 240    _FDT((fdt_setprop_cell(fdt, xscom_offset, "ibm,chip-id", chip->chip_id)));
 241    _FDT((fdt_setprop_cell(fdt, xscom_offset, "#address-cells", 1)));
 242    _FDT((fdt_setprop_cell(fdt, xscom_offset, "#size-cells", 1)));
 243    _FDT((fdt_setprop(fdt, xscom_offset, "reg", reg, sizeof(reg))));
 244
 245    if (pcc->chip_type == PNV_CHIP_POWER9) {
 246        _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p9,
 247                          sizeof(compat_p9))));
 248    } else {
 249        _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p8,
 250                          sizeof(compat_p8))));
 251    }
 252
 253    _FDT((fdt_setprop(fdt, xscom_offset, "scom-controller", NULL, 0)));
 254
 255    args.fdt = fdt;
 256    args.xscom_offset = xscom_offset;
 257
 258    object_child_foreach(OBJECT(chip), xscom_populate_child, &args);
 259    return 0;
 260}
 261
 262void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset, MemoryRegion *mr)
 263{
 264    memory_region_add_subregion(&chip->xscom, offset << 3, mr);
 265}
 266
 267void pnv_xscom_region_init(MemoryRegion *mr,
 268                           struct Object *owner,
 269                           const MemoryRegionOps *ops,
 270                           void *opaque,
 271                           const char *name,
 272                           uint64_t size)
 273{
 274    memory_region_init_io(mr, owner, ops, opaque, name, size << 3);
 275}
 276