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27#include "qemu/osdep.h"
28#include "qapi/error.h"
29#include "sysemu/sysemu.h"
30#include "sysemu/numa.h"
31#include "hw/hw.h"
32#include "qemu/log.h"
33#include "hw/fw-path-provider.h"
34#include "elf.h"
35#include "net/net.h"
36#include "sysemu/device_tree.h"
37#include "sysemu/block-backend.h"
38#include "sysemu/cpus.h"
39#include "sysemu/hw_accel.h"
40#include "kvm_ppc.h"
41#include "migration/misc.h"
42#include "migration/global_state.h"
43#include "migration/register.h"
44#include "mmu-hash64.h"
45#include "mmu-book3s-v3.h"
46#include "qom/cpu.h"
47
48#include "hw/boards.h"
49#include "hw/ppc/ppc.h"
50#include "hw/loader.h"
51
52#include "hw/ppc/fdt.h"
53#include "hw/ppc/spapr.h"
54#include "hw/ppc/spapr_vio.h"
55#include "hw/pci-host/spapr.h"
56#include "hw/ppc/xics.h"
57#include "hw/pci/msi.h"
58
59#include "hw/pci/pci.h"
60#include "hw/scsi/scsi.h"
61#include "hw/virtio/virtio-scsi.h"
62#include "hw/virtio/vhost-scsi-common.h"
63
64#include "exec/address-spaces.h"
65#include "hw/usb.h"
66#include "qemu/config-file.h"
67#include "qemu/error-report.h"
68#include "trace.h"
69#include "hw/nmi.h"
70#include "hw/intc/intc.h"
71
72#include "hw/compat.h"
73#include "qemu/cutils.h"
74#include "hw/ppc/spapr_cpu_core.h"
75#include "qmp-commands.h"
76
77#include <libfdt.h>
78
79
80
81
82
83
84
85
86
87
88
89#define FDT_MAX_SIZE 0x100000
90#define RTAS_MAX_SIZE 0x10000
91#define RTAS_MAX_ADDR 0x80000000
92#define FW_MAX_SIZE 0x400000
93#define FW_FILE_NAME "slof.bin"
94#define FW_OVERHEAD 0x2800000
95#define KERNEL_LOAD_ADDR FW_MAX_SIZE
96
97#define MIN_RMA_SLOF 128UL
98
99#define PHANDLE_XICP 0x00001111
100
101static ICSState *spapr_ics_create(sPAPRMachineState *spapr,
102 const char *type_ics,
103 int nr_irqs, Error **errp)
104{
105 Error *local_err = NULL;
106 Object *obj;
107
108 obj = object_new(type_ics);
109 object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort);
110 object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr),
111 &error_abort);
112 object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err);
113 if (local_err) {
114 goto error;
115 }
116 object_property_set_bool(obj, true, "realized", &local_err);
117 if (local_err) {
118 goto error;
119 }
120
121 return ICS_SIMPLE(obj);
122
123error:
124 error_propagate(errp, local_err);
125 return NULL;
126}
127
128static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque)
129{
130
131
132
133
134 return false;
135}
136
137static const VMStateDescription pre_2_10_vmstate_dummy_icp = {
138 .name = "icp/server",
139 .version_id = 1,
140 .minimum_version_id = 1,
141 .needed = pre_2_10_vmstate_dummy_icp_needed,
142 .fields = (VMStateField[]) {
143 VMSTATE_UNUSED(4),
144 VMSTATE_UNUSED(1),
145 VMSTATE_UNUSED(1),
146 VMSTATE_END_OF_LIST()
147 },
148};
149
150static void pre_2_10_vmstate_register_dummy_icp(int i)
151{
152 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp,
153 (void *)(uintptr_t) i);
154}
155
156static void pre_2_10_vmstate_unregister_dummy_icp(int i)
157{
158 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp,
159 (void *)(uintptr_t) i);
160}
161
162static inline int xics_max_server_number(void)
163{
164 return DIV_ROUND_UP(max_cpus * kvmppc_smt_threads(), smp_threads);
165}
166
167static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp)
168{
169 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
170 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
171
172 if (kvm_enabled()) {
173 if (machine_kernel_irqchip_allowed(machine) &&
174 !xics_kvm_init(spapr, errp)) {
175 spapr->icp_type = TYPE_KVM_ICP;
176 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs, errp);
177 }
178 if (machine_kernel_irqchip_required(machine) && !spapr->ics) {
179 error_prepend(errp, "kernel_irqchip requested but unavailable: ");
180 return;
181 }
182 }
183
184 if (!spapr->ics) {
185 xics_spapr_init(spapr);
186 spapr->icp_type = TYPE_ICP;
187 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs, errp);
188 if (!spapr->ics) {
189 return;
190 }
191 }
192
193 if (smc->pre_2_10_has_unused_icps) {
194 int i;
195
196 for (i = 0; i < xics_max_server_number(); i++) {
197
198
199
200 pre_2_10_vmstate_register_dummy_icp(i);
201 }
202 }
203}
204
205static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
206 int smt_threads)
207{
208 int i, ret = 0;
209 uint32_t servers_prop[smt_threads];
210 uint32_t gservers_prop[smt_threads * 2];
211 int index = ppc_get_vcpu_dt_id(cpu);
212
213 if (cpu->compat_pvr) {
214 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr);
215 if (ret < 0) {
216 return ret;
217 }
218 }
219
220
221 for (i = 0; i < smt_threads; i++) {
222 servers_prop[i] = cpu_to_be32(index + i);
223
224 gservers_prop[i*2] = cpu_to_be32(index + i);
225 gservers_prop[i*2 + 1] = 0;
226 }
227 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
228 servers_prop, sizeof(servers_prop));
229 if (ret < 0) {
230 return ret;
231 }
232 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
233 gservers_prop, sizeof(gservers_prop));
234
235 return ret;
236}
237
238static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu)
239{
240 int index = ppc_get_vcpu_dt_id(cpu);
241 uint32_t associativity[] = {cpu_to_be32(0x5),
242 cpu_to_be32(0x0),
243 cpu_to_be32(0x0),
244 cpu_to_be32(0x0),
245 cpu_to_be32(cpu->node_id),
246 cpu_to_be32(index)};
247
248
249 return fdt_setprop(fdt, offset, "ibm,associativity", associativity,
250 sizeof(associativity));
251}
252
253
254static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset,
255 bool legacy_guest)
256{
257 uint8_t pa_features_206[] = { 6, 0,
258 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
259 uint8_t pa_features_207[] = { 24, 0,
260 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
261 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
262 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
263 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
264 uint8_t pa_features_300[] = { 66, 0,
265
266
267 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
268
269 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
270
271 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
272
273 0x80, 0x00, 0x80, 0x00, 0x00, 0x00,
274
275 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
276
277 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00,
278
279 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
280
281 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
282
283 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
284
285 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
286
287 0x80, 0x00, 0x80, 0x00, 0x00, 0x00,
288 };
289 uint8_t *pa_features;
290 size_t pa_size;
291
292 switch (POWERPC_MMU_VER(env->mmu_model)) {
293 case POWERPC_MMU_VER_2_06:
294 pa_features = pa_features_206;
295 pa_size = sizeof(pa_features_206);
296 break;
297 case POWERPC_MMU_VER_2_07:
298 pa_features = pa_features_207;
299 pa_size = sizeof(pa_features_207);
300 break;
301 case POWERPC_MMU_VER_3_00:
302 pa_features = pa_features_300;
303 pa_size = sizeof(pa_features_300);
304 break;
305 default:
306 return;
307 }
308
309 if (env->ci_large_pages) {
310
311
312
313
314
315
316
317 pa_features[3] |= 0x20;
318 }
319 if (kvmppc_has_cap_htm() && pa_size > 24) {
320 pa_features[24] |= 0x80;
321 }
322 if (legacy_guest && pa_size > 40) {
323
324
325
326 pa_features[40 + 2] &= ~0x80;
327 }
328
329 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
330}
331
332static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
333{
334 int ret = 0, offset, cpus_offset;
335 CPUState *cs;
336 char cpu_model[32];
337 int smt = kvmppc_smt_threads();
338 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
339
340 CPU_FOREACH(cs) {
341 PowerPCCPU *cpu = POWERPC_CPU(cs);
342 CPUPPCState *env = &cpu->env;
343 DeviceClass *dc = DEVICE_GET_CLASS(cs);
344 int index = ppc_get_vcpu_dt_id(cpu);
345 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu));
346
347 if ((index % smt) != 0) {
348 continue;
349 }
350
351 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
352
353 cpus_offset = fdt_path_offset(fdt, "/cpus");
354 if (cpus_offset < 0) {
355 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
356 "cpus");
357 if (cpus_offset < 0) {
358 return cpus_offset;
359 }
360 }
361 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
362 if (offset < 0) {
363 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
364 if (offset < 0) {
365 return offset;
366 }
367 }
368
369 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
370 pft_size_prop, sizeof(pft_size_prop));
371 if (ret < 0) {
372 return ret;
373 }
374
375 if (nb_numa_nodes > 1) {
376 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu);
377 if (ret < 0) {
378 return ret;
379 }
380 }
381
382 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt);
383 if (ret < 0) {
384 return ret;
385 }
386
387 spapr_populate_pa_features(env, fdt, offset,
388 spapr->cas_legacy_guest_workaround);
389 }
390 return ret;
391}
392
393static hwaddr spapr_node0_size(void)
394{
395 MachineState *machine = MACHINE(qdev_get_machine());
396
397 if (nb_numa_nodes) {
398 int i;
399 for (i = 0; i < nb_numa_nodes; ++i) {
400 if (numa_info[i].node_mem) {
401 return MIN(pow2floor(numa_info[i].node_mem),
402 machine->ram_size);
403 }
404 }
405 }
406 return machine->ram_size;
407}
408
409static void add_str(GString *s, const gchar *s1)
410{
411 g_string_append_len(s, s1, strlen(s1) + 1);
412}
413
414static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
415 hwaddr size)
416{
417 uint32_t associativity[] = {
418 cpu_to_be32(0x4),
419 cpu_to_be32(0x0), cpu_to_be32(0x0),
420 cpu_to_be32(0x0), cpu_to_be32(nodeid)
421 };
422 char mem_name[32];
423 uint64_t mem_reg_property[2];
424 int off;
425
426 mem_reg_property[0] = cpu_to_be64(start);
427 mem_reg_property[1] = cpu_to_be64(size);
428
429 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
430 off = fdt_add_subnode(fdt, 0, mem_name);
431 _FDT(off);
432 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
433 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
434 sizeof(mem_reg_property))));
435 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
436 sizeof(associativity))));
437 return off;
438}
439
440static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
441{
442 MachineState *machine = MACHINE(spapr);
443 hwaddr mem_start, node_size;
444 int i, nb_nodes = nb_numa_nodes;
445 NodeInfo *nodes = numa_info;
446 NodeInfo ramnode;
447
448
449 if (!nb_numa_nodes) {
450 nb_nodes = 1;
451 ramnode.node_mem = machine->ram_size;
452 nodes = &ramnode;
453 }
454
455 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
456 if (!nodes[i].node_mem) {
457 continue;
458 }
459 if (mem_start >= machine->ram_size) {
460 node_size = 0;
461 } else {
462 node_size = nodes[i].node_mem;
463 if (node_size > machine->ram_size - mem_start) {
464 node_size = machine->ram_size - mem_start;
465 }
466 }
467 if (!mem_start) {
468
469 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
470 mem_start += spapr->rma_size;
471 node_size -= spapr->rma_size;
472 }
473 for ( ; node_size; ) {
474 hwaddr sizetmp = pow2floor(node_size);
475
476
477 if (ctzl(mem_start) < ctzl(sizetmp)) {
478 sizetmp = 1ULL << ctzl(mem_start);
479 }
480
481 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
482 node_size -= sizetmp;
483 mem_start += sizetmp;
484 }
485 }
486
487 return 0;
488}
489
490static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
491 sPAPRMachineState *spapr)
492{
493 PowerPCCPU *cpu = POWERPC_CPU(cs);
494 CPUPPCState *env = &cpu->env;
495 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
496 int index = ppc_get_vcpu_dt_id(cpu);
497 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
498 0xffffffff, 0xffffffff};
499 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
500 : SPAPR_TIMEBASE_FREQ;
501 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
502 uint32_t page_sizes_prop[64];
503 size_t page_sizes_prop_size;
504 uint32_t vcpus_per_socket = smp_threads * smp_cores;
505 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
506 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu));
507 sPAPRDRConnector *drc;
508 int drc_index;
509 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ];
510 int i;
511
512 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index);
513 if (drc) {
514 drc_index = spapr_drc_index(drc);
515 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
516 }
517
518 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
519 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
520
521 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
522 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
523 env->dcache_line_size)));
524 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
525 env->dcache_line_size)));
526 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
527 env->icache_line_size)));
528 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
529 env->icache_line_size)));
530
531 if (pcc->l1_dcache_size) {
532 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
533 pcc->l1_dcache_size)));
534 } else {
535 warn_report("Unknown L1 dcache size for cpu");
536 }
537 if (pcc->l1_icache_size) {
538 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
539 pcc->l1_icache_size)));
540 } else {
541 warn_report("Unknown L1 icache size for cpu");
542 }
543
544 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
545 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
546 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr)));
547 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
548 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
549 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
550
551 if (env->spr_cb[SPR_PURR].oea_read) {
552 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
553 }
554
555 if (env->mmu_model & POWERPC_MMU_1TSEG) {
556 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
557 segs, sizeof(segs))));
558 }
559
560
561
562
563
564 if (env->insns_flags & PPC_ALTIVEC) {
565 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
566
567 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
568 }
569
570
571
572
573 if (env->insns_flags2 & PPC2_DFP) {
574 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
575 }
576
577 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
578 sizeof(page_sizes_prop));
579 if (page_sizes_prop_size) {
580 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
581 page_sizes_prop, page_sizes_prop_size)));
582 }
583
584 spapr_populate_pa_features(env, fdt, offset, false);
585
586 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
587 cs->cpu_index / vcpus_per_socket)));
588
589 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
590 pft_size_prop, sizeof(pft_size_prop))));
591
592 if (nb_numa_nodes > 1) {
593 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu));
594 }
595
596 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt));
597
598 if (pcc->radix_page_info) {
599 for (i = 0; i < pcc->radix_page_info->count; i++) {
600 radix_AP_encodings[i] =
601 cpu_to_be32(pcc->radix_page_info->entries[i]);
602 }
603 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings",
604 radix_AP_encodings,
605 pcc->radix_page_info->count *
606 sizeof(radix_AP_encodings[0]))));
607 }
608}
609
610static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
611{
612 CPUState *cs;
613 int cpus_offset;
614 char *nodename;
615 int smt = kvmppc_smt_threads();
616
617 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
618 _FDT(cpus_offset);
619 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
620 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
621
622
623
624
625
626
627 CPU_FOREACH_REVERSE(cs) {
628 PowerPCCPU *cpu = POWERPC_CPU(cs);
629 int index = ppc_get_vcpu_dt_id(cpu);
630 DeviceClass *dc = DEVICE_GET_CLASS(cs);
631 int offset;
632
633 if ((index % smt) != 0) {
634 continue;
635 }
636
637 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
638 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
639 g_free(nodename);
640 _FDT(offset);
641 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
642 }
643
644}
645
646
647
648
649
650
651static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
652{
653 MachineState *machine = MACHINE(spapr);
654 int ret, i, offset;
655 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
656 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
657 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size;
658 uint32_t nr_lmbs = (spapr->hotplug_memory.base +
659 memory_region_size(&spapr->hotplug_memory.mr)) /
660 lmb_size;
661 uint32_t *int_buf, *cur_index, buf_len;
662 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
663
664
665
666
667 if (machine->ram_size == machine->maxram_size) {
668 return 0;
669 }
670
671
672
673
674
675 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2)
676 * sizeof(uint32_t);
677 cur_index = int_buf = g_malloc0(buf_len);
678
679 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
680
681 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
682 sizeof(prop_lmb_size));
683 if (ret < 0) {
684 goto out;
685 }
686
687 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
688 if (ret < 0) {
689 goto out;
690 }
691
692 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
693 if (ret < 0) {
694 goto out;
695 }
696
697
698 int_buf[0] = cpu_to_be32(nr_lmbs);
699 cur_index++;
700 for (i = 0; i < nr_lmbs; i++) {
701 uint64_t addr = i * lmb_size;
702 uint32_t *dynamic_memory = cur_index;
703
704 if (i >= hotplug_lmb_start) {
705 sPAPRDRConnector *drc;
706
707 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i);
708 g_assert(drc);
709
710 dynamic_memory[0] = cpu_to_be32(addr >> 32);
711 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
712 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc));
713 dynamic_memory[3] = cpu_to_be32(0);
714 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL));
715 if (memory_region_present(get_system_memory(), addr)) {
716 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
717 } else {
718 dynamic_memory[5] = cpu_to_be32(0);
719 }
720 } else {
721
722
723
724
725
726 dynamic_memory[0] = cpu_to_be32(addr >> 32);
727 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
728 dynamic_memory[2] = cpu_to_be32(0);
729 dynamic_memory[3] = cpu_to_be32(0);
730 dynamic_memory[4] = cpu_to_be32(-1);
731 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
732 SPAPR_LMB_FLAGS_DRC_INVALID);
733 }
734
735 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
736 }
737 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
738 if (ret < 0) {
739 goto out;
740 }
741
742
743 cur_index = int_buf;
744 int_buf[0] = cpu_to_be32(nr_nodes);
745 int_buf[1] = cpu_to_be32(4);
746 cur_index += 2;
747 for (i = 0; i < nr_nodes; i++) {
748 uint32_t associativity[] = {
749 cpu_to_be32(0x0),
750 cpu_to_be32(0x0),
751 cpu_to_be32(0x0),
752 cpu_to_be32(i)
753 };
754 memcpy(cur_index, associativity, sizeof(associativity));
755 cur_index += 4;
756 }
757 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
758 (cur_index - int_buf) * sizeof(uint32_t));
759out:
760 g_free(int_buf);
761 return ret;
762}
763
764static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt,
765 sPAPROptionVector *ov5_updates)
766{
767 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
768 int ret = 0, offset;
769
770
771 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) {
772 g_assert(smc->dr_lmb_enabled);
773 ret = spapr_populate_drconf_memory(spapr, fdt);
774 if (ret) {
775 goto out;
776 }
777 }
778
779 offset = fdt_path_offset(fdt, "/chosen");
780 if (offset < 0) {
781 offset = fdt_add_subnode(fdt, 0, "chosen");
782 if (offset < 0) {
783 return offset;
784 }
785 }
786 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas,
787 "ibm,architecture-vec-5");
788
789out:
790 return ret;
791}
792
793int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
794 target_ulong addr, target_ulong size,
795 sPAPROptionVector *ov5_updates)
796{
797 void *fdt, *fdt_skel;
798 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
799
800 size -= sizeof(hdr);
801
802
803 fdt_skel = g_malloc0(size);
804 _FDT((fdt_create(fdt_skel, size)));
805 _FDT((fdt_begin_node(fdt_skel, "")));
806 _FDT((fdt_end_node(fdt_skel)));
807 _FDT((fdt_finish(fdt_skel)));
808 fdt = g_malloc0(size);
809 _FDT((fdt_open_into(fdt_skel, fdt, size)));
810 g_free(fdt_skel);
811
812
813 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
814
815 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) {
816 return -1;
817 }
818
819
820 _FDT((fdt_pack(fdt)));
821
822 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
823 trace_spapr_cas_failed(size);
824 return -1;
825 }
826
827 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
828 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
829 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
830 g_free(fdt);
831
832 return 0;
833}
834
835static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt)
836{
837 int rtas;
838 GString *hypertas = g_string_sized_new(256);
839 GString *qemu_hypertas = g_string_sized_new(256);
840 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
841 uint64_t max_hotplug_addr = spapr->hotplug_memory.base +
842 memory_region_size(&spapr->hotplug_memory.mr);
843 uint32_t lrdr_capacity[] = {
844 cpu_to_be32(max_hotplug_addr >> 32),
845 cpu_to_be32(max_hotplug_addr & 0xffffffff),
846 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE),
847 cpu_to_be32(max_cpus / smp_threads),
848 };
849
850 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas"));
851
852
853 add_str(hypertas, "hcall-pft");
854 add_str(hypertas, "hcall-term");
855 add_str(hypertas, "hcall-dabr");
856 add_str(hypertas, "hcall-interrupt");
857 add_str(hypertas, "hcall-tce");
858 add_str(hypertas, "hcall-vio");
859 add_str(hypertas, "hcall-splpar");
860 add_str(hypertas, "hcall-bulk");
861 add_str(hypertas, "hcall-set-mode");
862 add_str(hypertas, "hcall-sprg0");
863 add_str(hypertas, "hcall-copy");
864 add_str(hypertas, "hcall-debug");
865 add_str(qemu_hypertas, "hcall-memop1");
866
867 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
868 add_str(hypertas, "hcall-multi-tce");
869 }
870
871 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
872 add_str(hypertas, "hcall-hpt-resize");
873 }
874
875 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions",
876 hypertas->str, hypertas->len));
877 g_string_free(hypertas, TRUE);
878 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions",
879 qemu_hypertas->str, qemu_hypertas->len));
880 g_string_free(qemu_hypertas, TRUE);
881
882 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points",
883 refpoints, sizeof(refpoints)));
884
885 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max",
886 RTAS_ERROR_LOG_MAX));
887 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate",
888 RTAS_EVENT_SCAN_RATE));
889
890 if (msi_nonbroken) {
891 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0));
892 }
893
894
895
896
897
898
899
900
901 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0));
902
903 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity",
904 lrdr_capacity, sizeof(lrdr_capacity)));
905
906 spapr_dt_rtas_tokens(fdt, rtas);
907}
908
909
910
911
912static void spapr_dt_ov5_platform_support(void *fdt, int chosen)
913{
914 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
915
916 char val[2 * 4] = {
917 23, 0x00,
918 24, 0x00,
919 25, 0x00,
920 26, 0x40,
921 };
922
923 if (kvm_enabled()) {
924 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
925 val[3] = 0x80;
926 } else if (kvmppc_has_cap_mmu_radix()) {
927 val[3] = 0x40;
928 } else {
929 val[3] = 0x00;
930 }
931 } else {
932 if (first_ppc_cpu->env.mmu_model & POWERPC_MMU_V3) {
933
934 val[3] = 0xC0;
935 } else {
936
937 val[3] = 0x00;
938 }
939 }
940 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support",
941 val, sizeof(val)));
942}
943
944static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt)
945{
946 MachineState *machine = MACHINE(spapr);
947 int chosen;
948 const char *boot_device = machine->boot_order;
949 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
950 size_t cb = 0;
951 char *bootlist = get_boot_devices_list(&cb, true);
952
953 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen"));
954
955 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline));
956 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start",
957 spapr->initrd_base));
958 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end",
959 spapr->initrd_base + spapr->initrd_size));
960
961 if (spapr->kernel_size) {
962 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
963 cpu_to_be64(spapr->kernel_size) };
964
965 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel",
966 &kprop, sizeof(kprop)));
967 if (spapr->kernel_le) {
968 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0));
969 }
970 }
971 if (boot_menu) {
972 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu)));
973 }
974 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width));
975 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height));
976 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth));
977
978 if (cb && bootlist) {
979 int i;
980
981 for (i = 0; i < cb; i++) {
982 if (bootlist[i] == '\n') {
983 bootlist[i] = ' ';
984 }
985 }
986 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist));
987 }
988
989 if (boot_device && strlen(boot_device)) {
990 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device));
991 }
992
993 if (!spapr->has_graphics && stdout_path) {
994 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path));
995 }
996
997 spapr_dt_ov5_platform_support(fdt, chosen);
998
999 g_free(stdout_path);
1000 g_free(bootlist);
1001}
1002
1003static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt)
1004{
1005
1006
1007 int hypervisor;
1008 uint8_t hypercall[16];
1009
1010 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor"));
1011
1012 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm"));
1013 if (kvmppc_has_cap_fixup_hcalls()) {
1014
1015
1016
1017
1018 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
1019 sizeof(hypercall))) {
1020 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions",
1021 hypercall, sizeof(hypercall)));
1022 }
1023 }
1024}
1025
1026static void *spapr_build_fdt(sPAPRMachineState *spapr,
1027 hwaddr rtas_addr,
1028 hwaddr rtas_size)
1029{
1030 MachineState *machine = MACHINE(qdev_get_machine());
1031 MachineClass *mc = MACHINE_GET_CLASS(machine);
1032 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1033 int ret;
1034 void *fdt;
1035 sPAPRPHBState *phb;
1036 char *buf;
1037
1038 fdt = g_malloc0(FDT_MAX_SIZE);
1039 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
1040
1041
1042 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp"));
1043 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)"));
1044 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries"));
1045
1046
1047
1048
1049
1050 if (kvmppc_get_host_model(&buf)) {
1051 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf));
1052 g_free(buf);
1053 }
1054 if (kvmppc_get_host_serial(&buf)) {
1055 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf));
1056 g_free(buf);
1057 }
1058
1059 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
1060
1061 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf));
1062 if (qemu_uuid_set) {
1063 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf));
1064 }
1065 g_free(buf);
1066
1067 if (qemu_get_vm_name()) {
1068 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name",
1069 qemu_get_vm_name()));
1070 }
1071
1072 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2));
1073 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2));
1074
1075
1076 spapr_dt_xics(xics_max_server_number(), fdt, PHANDLE_XICP);
1077
1078 ret = spapr_populate_memory(spapr, fdt);
1079 if (ret < 0) {
1080 error_report("couldn't setup memory nodes in fdt");
1081 exit(1);
1082 }
1083
1084
1085 spapr_dt_vdevice(spapr->vio_bus, fdt);
1086
1087 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
1088 ret = spapr_rng_populate_dt(fdt);
1089 if (ret < 0) {
1090 error_report("could not set up rng device in the fdt");
1091 exit(1);
1092 }
1093 }
1094
1095 QLIST_FOREACH(phb, &spapr->phbs, list) {
1096 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
1097 if (ret < 0) {
1098 error_report("couldn't setup PCI devices in fdt");
1099 exit(1);
1100 }
1101 }
1102
1103
1104 spapr_populate_cpus_dt_node(fdt, spapr);
1105
1106 if (smc->dr_lmb_enabled) {
1107 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
1108 }
1109
1110 if (mc->has_hotpluggable_cpus) {
1111 int offset = fdt_path_offset(fdt, "/cpus");
1112 ret = spapr_drc_populate_dt(fdt, offset, NULL,
1113 SPAPR_DR_CONNECTOR_TYPE_CPU);
1114 if (ret < 0) {
1115 error_report("Couldn't set up CPU DR device tree properties");
1116 exit(1);
1117 }
1118 }
1119
1120
1121 spapr_dt_events(spapr, fdt);
1122
1123
1124 spapr_dt_rtas(spapr, fdt);
1125
1126
1127 spapr_dt_chosen(spapr, fdt);
1128
1129
1130 if (kvm_enabled()) {
1131 spapr_dt_hypervisor(spapr, fdt);
1132 }
1133
1134
1135 if (spapr->kernel_size) {
1136 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size)));
1137 }
1138 if (spapr->initrd_size) {
1139 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size)));
1140 }
1141
1142
1143 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas);
1144 if (ret < 0) {
1145 error_report("couldn't setup CAS properties fdt");
1146 exit(1);
1147 }
1148
1149 return fdt;
1150}
1151
1152static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1153{
1154 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1155}
1156
1157static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,
1158 PowerPCCPU *cpu)
1159{
1160 CPUPPCState *env = &cpu->env;
1161
1162
1163 g_assert(qemu_mutex_iothread_locked());
1164
1165 if (msr_pr) {
1166 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1167 env->gpr[3] = H_PRIVILEGE;
1168 } else {
1169 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1170 }
1171}
1172
1173static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp)
1174{
1175 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1176
1177 return spapr->patb_entry;
1178}
1179
1180#define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1181#define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1182#define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1183#define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1184#define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1185
1186
1187
1188
1189static int get_htab_fd(sPAPRMachineState *spapr)
1190{
1191 if (spapr->htab_fd >= 0) {
1192 return spapr->htab_fd;
1193 }
1194
1195 spapr->htab_fd = kvmppc_get_htab_fd(false);
1196 if (spapr->htab_fd < 0) {
1197 error_report("Unable to open fd for reading hash table from KVM: %s",
1198 strerror(errno));
1199 }
1200
1201 return spapr->htab_fd;
1202}
1203
1204void close_htab_fd(sPAPRMachineState *spapr)
1205{
1206 if (spapr->htab_fd >= 0) {
1207 close(spapr->htab_fd);
1208 }
1209 spapr->htab_fd = -1;
1210}
1211
1212static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp)
1213{
1214 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1215
1216 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1;
1217}
1218
1219static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp,
1220 hwaddr ptex, int n)
1221{
1222 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1223 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
1224
1225 if (!spapr->htab) {
1226
1227
1228
1229 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64);
1230 kvmppc_read_hptes(hptes, ptex, n);
1231 return hptes;
1232 }
1233
1234
1235
1236
1237
1238 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset);
1239}
1240
1241static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp,
1242 const ppc_hash_pte64_t *hptes,
1243 hwaddr ptex, int n)
1244{
1245 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1246
1247 if (!spapr->htab) {
1248 g_free((void *)hptes);
1249 }
1250
1251
1252}
1253
1254static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1255 uint64_t pte0, uint64_t pte1)
1256{
1257 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1258 hwaddr offset = ptex * HASH_PTE_SIZE_64;
1259
1260 if (!spapr->htab) {
1261 kvmppc_write_hpte(ptex, pte0, pte1);
1262 } else {
1263 stq_p(spapr->htab + offset, pte0);
1264 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1265 }
1266}
1267
1268int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1269{
1270 int shift;
1271
1272
1273
1274
1275 shift = ctz64(pow2ceil(ramsize)) - 7;
1276 shift = MAX(shift, 18);
1277 shift = MIN(shift, 46);
1278 return shift;
1279}
1280
1281void spapr_free_hpt(sPAPRMachineState *spapr)
1282{
1283 g_free(spapr->htab);
1284 spapr->htab = NULL;
1285 spapr->htab_shift = 0;
1286 close_htab_fd(spapr);
1287}
1288
1289void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
1290 Error **errp)
1291{
1292 long rc;
1293
1294
1295 spapr_free_hpt(spapr);
1296
1297 rc = kvmppc_reset_htab(shift);
1298 if (rc < 0) {
1299
1300 error_setg_errno(errp, errno,
1301 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1302 shift);
1303
1304
1305 } else if (rc > 0) {
1306
1307 if (rc != shift) {
1308 error_setg(errp,
1309 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1310 shift, rc);
1311 }
1312
1313 spapr->htab_shift = shift;
1314 spapr->htab = NULL;
1315 } else {
1316
1317 size_t size = 1ULL << shift;
1318 int i;
1319
1320 spapr->htab = qemu_memalign(size, size);
1321 if (!spapr->htab) {
1322 error_setg_errno(errp, errno,
1323 "Could not allocate HPT of order %d", shift);
1324 return;
1325 }
1326
1327 memset(spapr->htab, 0, size);
1328 spapr->htab_shift = shift;
1329
1330 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1331 DIRTY_HPTE(HPTE(spapr->htab, i));
1332 }
1333 }
1334}
1335
1336void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr)
1337{
1338 int hpt_shift;
1339
1340 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED)
1341 || (spapr->cas_reboot
1342 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) {
1343 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size);
1344 } else {
1345 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->ram_size);
1346 }
1347 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal);
1348
1349 if (spapr->vrma_adjust) {
1350 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(),
1351 spapr->htab_shift);
1352 }
1353
1354 spapr->patb_entry = 0;
1355}
1356
1357static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque)
1358{
1359 bool matched = false;
1360
1361 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
1362 matched = true;
1363 }
1364
1365 if (!matched) {
1366 error_report("Device %s is not supported by this machine yet.",
1367 qdev_fw_name(DEVICE(sbdev)));
1368 exit(1);
1369 }
1370}
1371
1372static void ppc_spapr_reset(void)
1373{
1374 MachineState *machine = MACHINE(qdev_get_machine());
1375 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1376 PowerPCCPU *first_ppc_cpu;
1377 uint32_t rtas_limit;
1378 hwaddr rtas_addr, fdt_addr;
1379 void *fdt;
1380 int rc;
1381
1382
1383 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
1384
1385 if (kvm_enabled() && kvmppc_has_cap_mmu_radix()) {
1386
1387
1388
1389 spapr->patb_entry = PATBE1_GR;
1390 } else {
1391 spapr_setup_hpt_and_vrma(spapr);
1392 }
1393
1394 qemu_devices_reset();
1395
1396
1397
1398
1399
1400
1401 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1402 rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1403 fdt_addr = rtas_addr - FDT_MAX_SIZE;
1404
1405
1406
1407 if (!spapr->cas_reboot) {
1408 spapr_ovec_cleanup(spapr->ov5_cas);
1409 spapr->ov5_cas = spapr_ovec_new();
1410
1411 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal);
1412 }
1413
1414 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size);
1415
1416 spapr_load_rtas(spapr, fdt, rtas_addr);
1417
1418 rc = fdt_pack(fdt);
1419
1420
1421 assert(rc == 0);
1422
1423 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
1424 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1425 fdt_totalsize(fdt), FDT_MAX_SIZE);
1426 exit(1);
1427 }
1428
1429
1430 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
1431 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1432 g_free(fdt);
1433
1434
1435 first_ppc_cpu = POWERPC_CPU(first_cpu);
1436 first_ppc_cpu->env.gpr[3] = fdt_addr;
1437 first_ppc_cpu->env.gpr[5] = 0;
1438 first_cpu->halted = 0;
1439 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT;
1440
1441 spapr->cas_reboot = false;
1442}
1443
1444static void spapr_create_nvram(sPAPRMachineState *spapr)
1445{
1446 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
1447 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1448
1449 if (dinfo) {
1450 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1451 &error_fatal);
1452 }
1453
1454 qdev_init_nofail(dev);
1455
1456 spapr->nvram = (struct sPAPRNVRAM *)dev;
1457}
1458
1459static void spapr_rtc_create(sPAPRMachineState *spapr)
1460{
1461 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC);
1462 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc),
1463 &error_fatal);
1464 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized",
1465 &error_fatal);
1466 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc),
1467 "date", &error_fatal);
1468}
1469
1470
1471static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1472{
1473 switch (vga_interface_type) {
1474 case VGA_NONE:
1475 return false;
1476 case VGA_DEVICE:
1477 return true;
1478 case VGA_STD:
1479 case VGA_VIRTIO:
1480 return pci_vga_init(pci_bus) != NULL;
1481 default:
1482 error_setg(errp,
1483 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1484 return false;
1485 }
1486}
1487
1488static int spapr_post_load(void *opaque, int version_id)
1489{
1490 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1491 int err = 0;
1492
1493 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) {
1494 CPUState *cs;
1495 CPU_FOREACH(cs) {
1496 PowerPCCPU *cpu = POWERPC_CPU(cs);
1497 icp_resend(ICP(cpu->intc));
1498 }
1499 }
1500
1501
1502
1503
1504
1505 if (version_id < 3) {
1506 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset);
1507 }
1508
1509 if (spapr->patb_entry) {
1510 PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
1511 bool radix = !!(spapr->patb_entry & PATBE1_GR);
1512 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE);
1513
1514 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry);
1515 if (err) {
1516 error_report("Process table config unsupported by the host");
1517 return -EINVAL;
1518 }
1519 }
1520
1521 return err;
1522}
1523
1524static bool version_before_3(void *opaque, int version_id)
1525{
1526 return version_id < 3;
1527}
1528
1529static bool spapr_pending_events_needed(void *opaque)
1530{
1531 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1532 return !QTAILQ_EMPTY(&spapr->pending_events);
1533}
1534
1535static const VMStateDescription vmstate_spapr_event_entry = {
1536 .name = "spapr_event_log_entry",
1537 .version_id = 1,
1538 .minimum_version_id = 1,
1539 .fields = (VMStateField[]) {
1540 VMSTATE_UINT32(summary, sPAPREventLogEntry),
1541 VMSTATE_UINT32(extended_length, sPAPREventLogEntry),
1542 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, sPAPREventLogEntry, 0,
1543 NULL, extended_length),
1544 VMSTATE_END_OF_LIST()
1545 },
1546};
1547
1548static const VMStateDescription vmstate_spapr_pending_events = {
1549 .name = "spapr_pending_events",
1550 .version_id = 1,
1551 .minimum_version_id = 1,
1552 .needed = spapr_pending_events_needed,
1553 .fields = (VMStateField[]) {
1554 VMSTATE_QTAILQ_V(pending_events, sPAPRMachineState, 1,
1555 vmstate_spapr_event_entry, sPAPREventLogEntry, next),
1556 VMSTATE_END_OF_LIST()
1557 },
1558};
1559
1560static bool spapr_ov5_cas_needed(void *opaque)
1561{
1562 sPAPRMachineState *spapr = opaque;
1563 sPAPROptionVector *ov5_mask = spapr_ovec_new();
1564 sPAPROptionVector *ov5_legacy = spapr_ovec_new();
1565 sPAPROptionVector *ov5_removed = spapr_ovec_new();
1566 bool cas_needed;
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY);
1593 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY);
1594
1595
1596
1597
1598
1599
1600 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask);
1601 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy);
1602
1603 spapr_ovec_cleanup(ov5_mask);
1604 spapr_ovec_cleanup(ov5_legacy);
1605 spapr_ovec_cleanup(ov5_removed);
1606
1607 return cas_needed;
1608}
1609
1610static const VMStateDescription vmstate_spapr_ov5_cas = {
1611 .name = "spapr_option_vector_ov5_cas",
1612 .version_id = 1,
1613 .minimum_version_id = 1,
1614 .needed = spapr_ov5_cas_needed,
1615 .fields = (VMStateField[]) {
1616 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1,
1617 vmstate_spapr_ovec, sPAPROptionVector),
1618 VMSTATE_END_OF_LIST()
1619 },
1620};
1621
1622static bool spapr_patb_entry_needed(void *opaque)
1623{
1624 sPAPRMachineState *spapr = opaque;
1625
1626 return !!spapr->patb_entry;
1627}
1628
1629static const VMStateDescription vmstate_spapr_patb_entry = {
1630 .name = "spapr_patb_entry",
1631 .version_id = 1,
1632 .minimum_version_id = 1,
1633 .needed = spapr_patb_entry_needed,
1634 .fields = (VMStateField[]) {
1635 VMSTATE_UINT64(patb_entry, sPAPRMachineState),
1636 VMSTATE_END_OF_LIST()
1637 },
1638};
1639
1640static const VMStateDescription vmstate_spapr = {
1641 .name = "spapr",
1642 .version_id = 3,
1643 .minimum_version_id = 1,
1644 .post_load = spapr_post_load,
1645 .fields = (VMStateField[]) {
1646
1647 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
1648
1649
1650 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
1651
1652 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
1653 VMSTATE_END_OF_LIST()
1654 },
1655 .subsections = (const VMStateDescription*[]) {
1656 &vmstate_spapr_ov5_cas,
1657 &vmstate_spapr_patb_entry,
1658 &vmstate_spapr_pending_events,
1659 NULL
1660 }
1661};
1662
1663static int htab_save_setup(QEMUFile *f, void *opaque)
1664{
1665 sPAPRMachineState *spapr = opaque;
1666
1667
1668 if (!spapr->htab_shift) {
1669 qemu_put_be32(f, -1);
1670 } else {
1671 qemu_put_be32(f, spapr->htab_shift);
1672 }
1673
1674 if (spapr->htab) {
1675 spapr->htab_save_index = 0;
1676 spapr->htab_first_pass = true;
1677 } else {
1678 if (spapr->htab_shift) {
1679 assert(kvm_enabled());
1680 }
1681 }
1682
1683
1684 return 0;
1685}
1686
1687static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr,
1688 int64_t max_ns)
1689{
1690 bool has_timeout = max_ns != -1;
1691 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1692 int index = spapr->htab_save_index;
1693 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1694
1695 assert(spapr->htab_first_pass);
1696
1697 do {
1698 int chunkstart;
1699
1700
1701 while ((index < htabslots)
1702 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1703 CLEAN_HPTE(HPTE(spapr->htab, index));
1704 index++;
1705 }
1706
1707
1708 chunkstart = index;
1709 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1710 && HPTE_VALID(HPTE(spapr->htab, index))) {
1711 CLEAN_HPTE(HPTE(spapr->htab, index));
1712 index++;
1713 }
1714
1715 if (index > chunkstart) {
1716 int n_valid = index - chunkstart;
1717
1718 qemu_put_be32(f, chunkstart);
1719 qemu_put_be16(f, n_valid);
1720 qemu_put_be16(f, 0);
1721 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1722 HASH_PTE_SIZE_64 * n_valid);
1723
1724 if (has_timeout &&
1725 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1726 break;
1727 }
1728 }
1729 } while ((index < htabslots) && !qemu_file_rate_limit(f));
1730
1731 if (index >= htabslots) {
1732 assert(index == htabslots);
1733 index = 0;
1734 spapr->htab_first_pass = false;
1735 }
1736 spapr->htab_save_index = index;
1737}
1738
1739static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr,
1740 int64_t max_ns)
1741{
1742 bool final = max_ns < 0;
1743 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1744 int examined = 0, sent = 0;
1745 int index = spapr->htab_save_index;
1746 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1747
1748 assert(!spapr->htab_first_pass);
1749
1750 do {
1751 int chunkstart, invalidstart;
1752
1753
1754 while ((index < htabslots)
1755 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
1756 index++;
1757 examined++;
1758 }
1759
1760 chunkstart = index;
1761
1762 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1763 && HPTE_DIRTY(HPTE(spapr->htab, index))
1764 && HPTE_VALID(HPTE(spapr->htab, index))) {
1765 CLEAN_HPTE(HPTE(spapr->htab, index));
1766 index++;
1767 examined++;
1768 }
1769
1770 invalidstart = index;
1771
1772 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
1773 && HPTE_DIRTY(HPTE(spapr->htab, index))
1774 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1775 CLEAN_HPTE(HPTE(spapr->htab, index));
1776 index++;
1777 examined++;
1778 }
1779
1780 if (index > chunkstart) {
1781 int n_valid = invalidstart - chunkstart;
1782 int n_invalid = index - invalidstart;
1783
1784 qemu_put_be32(f, chunkstart);
1785 qemu_put_be16(f, n_valid);
1786 qemu_put_be16(f, n_invalid);
1787 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1788 HASH_PTE_SIZE_64 * n_valid);
1789 sent += index - chunkstart;
1790
1791 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1792 break;
1793 }
1794 }
1795
1796 if (examined >= htabslots) {
1797 break;
1798 }
1799
1800 if (index >= htabslots) {
1801 assert(index == htabslots);
1802 index = 0;
1803 }
1804 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
1805
1806 if (index >= htabslots) {
1807 assert(index == htabslots);
1808 index = 0;
1809 }
1810
1811 spapr->htab_save_index = index;
1812
1813 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
1814}
1815
1816#define MAX_ITERATION_NS 5000000
1817#define MAX_KVM_BUF_SIZE 2048
1818
1819static int htab_save_iterate(QEMUFile *f, void *opaque)
1820{
1821 sPAPRMachineState *spapr = opaque;
1822 int fd;
1823 int rc = 0;
1824
1825
1826 if (!spapr->htab_shift) {
1827 qemu_put_be32(f, -1);
1828 return 1;
1829 } else {
1830 qemu_put_be32(f, 0);
1831 }
1832
1833 if (!spapr->htab) {
1834 assert(kvm_enabled());
1835
1836 fd = get_htab_fd(spapr);
1837 if (fd < 0) {
1838 return fd;
1839 }
1840
1841 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
1842 if (rc < 0) {
1843 return rc;
1844 }
1845 } else if (spapr->htab_first_pass) {
1846 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
1847 } else {
1848 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
1849 }
1850
1851
1852 qemu_put_be32(f, 0);
1853 qemu_put_be16(f, 0);
1854 qemu_put_be16(f, 0);
1855
1856 return rc;
1857}
1858
1859static int htab_save_complete(QEMUFile *f, void *opaque)
1860{
1861 sPAPRMachineState *spapr = opaque;
1862 int fd;
1863
1864
1865 if (!spapr->htab_shift) {
1866 qemu_put_be32(f, -1);
1867 return 0;
1868 } else {
1869 qemu_put_be32(f, 0);
1870 }
1871
1872 if (!spapr->htab) {
1873 int rc;
1874
1875 assert(kvm_enabled());
1876
1877 fd = get_htab_fd(spapr);
1878 if (fd < 0) {
1879 return fd;
1880 }
1881
1882 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
1883 if (rc < 0) {
1884 return rc;
1885 }
1886 } else {
1887 if (spapr->htab_first_pass) {
1888 htab_save_first_pass(f, spapr, -1);
1889 }
1890 htab_save_later_pass(f, spapr, -1);
1891 }
1892
1893
1894 qemu_put_be32(f, 0);
1895 qemu_put_be16(f, 0);
1896 qemu_put_be16(f, 0);
1897
1898 return 0;
1899}
1900
1901static int htab_load(QEMUFile *f, void *opaque, int version_id)
1902{
1903 sPAPRMachineState *spapr = opaque;
1904 uint32_t section_hdr;
1905 int fd = -1;
1906
1907 if (version_id < 1 || version_id > 1) {
1908 error_report("htab_load() bad version");
1909 return -EINVAL;
1910 }
1911
1912 section_hdr = qemu_get_be32(f);
1913
1914 if (section_hdr == -1) {
1915 spapr_free_hpt(spapr);
1916 return 0;
1917 }
1918
1919 if (section_hdr) {
1920 Error *local_err = NULL;
1921
1922
1923 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
1924 if (local_err) {
1925 error_report_err(local_err);
1926 return -EINVAL;
1927 }
1928 return 0;
1929 }
1930
1931 if (!spapr->htab) {
1932 assert(kvm_enabled());
1933
1934 fd = kvmppc_get_htab_fd(true);
1935 if (fd < 0) {
1936 error_report("Unable to open fd to restore KVM hash table: %s",
1937 strerror(errno));
1938 }
1939 }
1940
1941 while (true) {
1942 uint32_t index;
1943 uint16_t n_valid, n_invalid;
1944
1945 index = qemu_get_be32(f);
1946 n_valid = qemu_get_be16(f);
1947 n_invalid = qemu_get_be16(f);
1948
1949 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
1950
1951 break;
1952 }
1953
1954 if ((index + n_valid + n_invalid) >
1955 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
1956
1957 error_report(
1958 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
1959 index, n_valid, n_invalid, spapr->htab_shift);
1960 return -EINVAL;
1961 }
1962
1963 if (spapr->htab) {
1964 if (n_valid) {
1965 qemu_get_buffer(f, HPTE(spapr->htab, index),
1966 HASH_PTE_SIZE_64 * n_valid);
1967 }
1968 if (n_invalid) {
1969 memset(HPTE(spapr->htab, index + n_valid), 0,
1970 HASH_PTE_SIZE_64 * n_invalid);
1971 }
1972 } else {
1973 int rc;
1974
1975 assert(fd >= 0);
1976
1977 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
1978 if (rc < 0) {
1979 return rc;
1980 }
1981 }
1982 }
1983
1984 if (!spapr->htab) {
1985 assert(fd >= 0);
1986 close(fd);
1987 }
1988
1989 return 0;
1990}
1991
1992static void htab_save_cleanup(void *opaque)
1993{
1994 sPAPRMachineState *spapr = opaque;
1995
1996 close_htab_fd(spapr);
1997}
1998
1999static SaveVMHandlers savevm_htab_handlers = {
2000 .save_setup = htab_save_setup,
2001 .save_live_iterate = htab_save_iterate,
2002 .save_live_complete_precopy = htab_save_complete,
2003 .save_cleanup = htab_save_cleanup,
2004 .load_state = htab_load,
2005};
2006
2007static void spapr_boot_set(void *opaque, const char *boot_device,
2008 Error **errp)
2009{
2010 MachineState *machine = MACHINE(qdev_get_machine());
2011 machine->boot_order = g_strdup(boot_device);
2012}
2013
2014static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
2015{
2016 MachineState *machine = MACHINE(spapr);
2017 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
2018 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
2019 int i;
2020
2021 for (i = 0; i < nr_lmbs; i++) {
2022 uint64_t addr;
2023
2024 addr = i * lmb_size + spapr->hotplug_memory.base;
2025 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB,
2026 addr / lmb_size);
2027 }
2028}
2029
2030
2031
2032
2033
2034
2035static void spapr_validate_node_memory(MachineState *machine, Error **errp)
2036{
2037 int i;
2038
2039 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2040 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
2041 " is not aligned to %llu MiB",
2042 machine->ram_size,
2043 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
2044 return;
2045 }
2046
2047 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2048 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
2049 " is not aligned to %llu MiB",
2050 machine->ram_size,
2051 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
2052 return;
2053 }
2054
2055 for (i = 0; i < nb_numa_nodes; i++) {
2056 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
2057 error_setg(errp,
2058 "Node %d memory size 0x%" PRIx64
2059 " is not aligned to %llu MiB",
2060 i, numa_info[i].node_mem,
2061 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
2062 return;
2063 }
2064 }
2065}
2066
2067
2068static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
2069{
2070 int index = id / smp_threads;
2071
2072 if (index >= ms->possible_cpus->len) {
2073 return NULL;
2074 }
2075 if (idx) {
2076 *idx = index;
2077 }
2078 return &ms->possible_cpus->cpus[index];
2079}
2080
2081static void spapr_init_cpus(sPAPRMachineState *spapr)
2082{
2083 MachineState *machine = MACHINE(spapr);
2084 MachineClass *mc = MACHINE_GET_CLASS(machine);
2085 char *type = spapr_get_cpu_core_type(machine->cpu_model);
2086 int smt = kvmppc_smt_threads();
2087 const CPUArchIdList *possible_cpus;
2088 int boot_cores_nr = smp_cpus / smp_threads;
2089 int i;
2090
2091 if (!type) {
2092 error_report("Unable to find sPAPR CPU Core definition");
2093 exit(1);
2094 }
2095
2096 possible_cpus = mc->possible_cpu_arch_ids(machine);
2097 if (mc->has_hotpluggable_cpus) {
2098 if (smp_cpus % smp_threads) {
2099 error_report("smp_cpus (%u) must be multiple of threads (%u)",
2100 smp_cpus, smp_threads);
2101 exit(1);
2102 }
2103 if (max_cpus % smp_threads) {
2104 error_report("max_cpus (%u) must be multiple of threads (%u)",
2105 max_cpus, smp_threads);
2106 exit(1);
2107 }
2108 } else {
2109 if (max_cpus != smp_cpus) {
2110 error_report("This machine version does not support CPU hotplug");
2111 exit(1);
2112 }
2113 boot_cores_nr = possible_cpus->len;
2114 }
2115
2116 for (i = 0; i < possible_cpus->len; i++) {
2117 int core_id = i * smp_threads;
2118
2119 if (mc->has_hotpluggable_cpus) {
2120 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU,
2121 (core_id / smp_threads) * smt);
2122 }
2123
2124 if (i < boot_cores_nr) {
2125 Object *core = object_new(type);
2126 int nr_threads = smp_threads;
2127
2128
2129 if ((i + 1) * smp_threads >= smp_cpus) {
2130 nr_threads = smp_cpus - i * smp_threads;
2131 }
2132
2133 object_property_set_int(core, nr_threads, "nr-threads",
2134 &error_fatal);
2135 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
2136 &error_fatal);
2137 object_property_set_bool(core, true, "realized", &error_fatal);
2138 }
2139 }
2140 g_free(type);
2141}
2142
2143
2144static void ppc_spapr_init(MachineState *machine)
2145{
2146 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
2147 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2148 const char *kernel_filename = machine->kernel_filename;
2149 const char *initrd_filename = machine->initrd_filename;
2150 PCIHostState *phb;
2151 int i;
2152 MemoryRegion *sysmem = get_system_memory();
2153 MemoryRegion *ram = g_new(MemoryRegion, 1);
2154 MemoryRegion *rma_region;
2155 void *rma = NULL;
2156 hwaddr rma_alloc_size;
2157 hwaddr node0_size = spapr_node0_size();
2158 long load_limit, fw_size;
2159 char *filename;
2160 Error *resize_hpt_err = NULL;
2161
2162 msi_nonbroken = true;
2163
2164 QLIST_INIT(&spapr->phbs);
2165 QTAILQ_INIT(&spapr->pending_dimm_unplugs);
2166
2167
2168 kvmppc_check_papr_resize_hpt(&resize_hpt_err);
2169 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) {
2170
2171
2172
2173
2174
2175
2176 if (resize_hpt_err) {
2177 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
2178 error_free(resize_hpt_err);
2179 resize_hpt_err = NULL;
2180 } else {
2181 spapr->resize_hpt = smc->resize_hpt_default;
2182 }
2183 }
2184
2185 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT);
2186
2187 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) {
2188
2189
2190
2191 error_report_err(resize_hpt_err);
2192 exit(1);
2193 }
2194
2195
2196 rma_alloc_size = kvmppc_alloc_rma(&rma);
2197
2198 if (rma_alloc_size == -1) {
2199 error_report("Unable to create RMA");
2200 exit(1);
2201 }
2202
2203 if (rma_alloc_size && (rma_alloc_size < node0_size)) {
2204 spapr->rma_size = rma_alloc_size;
2205 } else {
2206 spapr->rma_size = node0_size;
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217 if (kvm_enabled()) {
2218 spapr->vrma_adjust = 1;
2219 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
2220 }
2221
2222
2223
2224
2225
2226
2227 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull);
2228 }
2229
2230 if (spapr->rma_size > node0_size) {
2231 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
2232 spapr->rma_size);
2233 exit(1);
2234 }
2235
2236
2237 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
2238
2239
2240 xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal);
2241
2242
2243 spapr->ov5 = spapr_ovec_new();
2244 spapr->ov5_cas = spapr_ovec_new();
2245
2246 if (smc->dr_lmb_enabled) {
2247 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY);
2248 spapr_validate_node_memory(machine, &error_fatal);
2249 }
2250
2251 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY);
2252 if (!kvm_enabled() || kvmppc_has_cap_mmu_radix()) {
2253
2254 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE);
2255 }
2256
2257
2258
2259 if (spapr->use_hotplug_event_source) {
2260 spapr_ovec_set(spapr->ov5, OV5_HP_EVT);
2261 }
2262
2263
2264 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
2265 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE);
2266 }
2267
2268
2269 if (machine->cpu_model == NULL) {
2270 machine->cpu_model = kvm_enabled() ? "host" : smc->tcg_default_cpu;
2271 }
2272
2273 spapr_cpu_parse_features(spapr);
2274
2275 spapr_init_cpus(spapr);
2276
2277 if (kvm_enabled()) {
2278
2279 kvmppc_enable_logical_ci_hcalls();
2280 kvmppc_enable_set_mode_hcall();
2281
2282
2283 kvmppc_enable_clear_ref_mod_hcalls();
2284 }
2285
2286
2287 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
2288 machine->ram_size);
2289 memory_region_add_subregion(sysmem, 0, ram);
2290
2291 if (rma_alloc_size && rma) {
2292 rma_region = g_new(MemoryRegion, 1);
2293 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma",
2294 rma_alloc_size, rma);
2295 vmstate_register_ram_global(rma_region);
2296 memory_region_add_subregion(sysmem, 0, rma_region);
2297 }
2298
2299
2300 if (machine->ram_size < machine->maxram_size) {
2301 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size;
2302
2303
2304
2305
2306
2307 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
2308 SPAPR_MAX_RAM_SLOTS;
2309
2310 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
2311 max_memslots = SPAPR_MAX_RAM_SLOTS;
2312 }
2313 if (machine->ram_slots > max_memslots) {
2314 error_report("Specified number of memory slots %"
2315 PRIu64" exceeds max supported %d",
2316 machine->ram_slots, max_memslots);
2317 exit(1);
2318 }
2319
2320 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size,
2321 SPAPR_HOTPLUG_MEM_ALIGN);
2322 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr),
2323 "hotplug-memory", hotplug_mem_size);
2324 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base,
2325 &spapr->hotplug_memory.mr);
2326 }
2327
2328 if (smc->dr_lmb_enabled) {
2329 spapr_create_lmb_dr_connectors(spapr);
2330 }
2331
2332 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
2333 if (!filename) {
2334 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
2335 exit(1);
2336 }
2337 spapr->rtas_size = get_image_size(filename);
2338 if (spapr->rtas_size < 0) {
2339 error_report("Could not get size of LPAR rtas '%s'", filename);
2340 exit(1);
2341 }
2342 spapr->rtas_blob = g_malloc(spapr->rtas_size);
2343 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
2344 error_report("Could not load LPAR rtas '%s'", filename);
2345 exit(1);
2346 }
2347 if (spapr->rtas_size > RTAS_MAX_SIZE) {
2348 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
2349 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
2350 exit(1);
2351 }
2352 g_free(filename);
2353
2354
2355 spapr_events_init(spapr);
2356
2357
2358 spapr_rtc_create(spapr);
2359
2360
2361 spapr->vio_bus = spapr_vio_bus_init();
2362
2363 for (i = 0; i < MAX_SERIAL_PORTS; i++) {
2364 if (serial_hds[i]) {
2365 spapr_vty_create(spapr->vio_bus, serial_hds[i]);
2366 }
2367 }
2368
2369
2370 spapr_create_nvram(spapr);
2371
2372
2373 spapr_pci_rtas_init();
2374
2375 phb = spapr_create_phb(spapr, 0);
2376
2377 for (i = 0; i < nb_nics; i++) {
2378 NICInfo *nd = &nd_table[i];
2379
2380 if (!nd->model) {
2381 nd->model = g_strdup("ibmveth");
2382 }
2383
2384 if (strcmp(nd->model, "ibmveth") == 0) {
2385 spapr_vlan_create(spapr->vio_bus, nd);
2386 } else {
2387 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
2388 }
2389 }
2390
2391 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
2392 spapr_vscsi_create(spapr->vio_bus);
2393 }
2394
2395
2396 if (spapr_vga_init(phb->bus, &error_fatal)) {
2397 spapr->has_graphics = true;
2398 machine->usb |= defaults_enabled() && !machine->usb_disabled;
2399 }
2400
2401 if (machine->usb) {
2402 if (smc->use_ohci_by_default) {
2403 pci_create_simple(phb->bus, -1, "pci-ohci");
2404 } else {
2405 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
2406 }
2407
2408 if (spapr->has_graphics) {
2409 USBBus *usb_bus = usb_bus_find(-1);
2410
2411 usb_create_simple(usb_bus, "usb-kbd");
2412 usb_create_simple(usb_bus, "usb-mouse");
2413 }
2414 }
2415
2416 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
2417 error_report(
2418 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
2419 MIN_RMA_SLOF);
2420 exit(1);
2421 }
2422
2423 if (kernel_filename) {
2424 uint64_t lowaddr = 0;
2425
2426 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address,
2427 NULL, NULL, &lowaddr, NULL, 1,
2428 PPC_ELF_MACHINE, 0, 0);
2429 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) {
2430 spapr->kernel_size = load_elf(kernel_filename,
2431 translate_kernel_address, NULL, NULL,
2432 &lowaddr, NULL, 0, PPC_ELF_MACHINE,
2433 0, 0);
2434 spapr->kernel_le = spapr->kernel_size > 0;
2435 }
2436 if (spapr->kernel_size < 0) {
2437 error_report("error loading %s: %s", kernel_filename,
2438 load_elf_strerror(spapr->kernel_size));
2439 exit(1);
2440 }
2441
2442
2443 if (initrd_filename) {
2444
2445
2446
2447 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size
2448 + 0x1ffff) & ~0xffff;
2449 spapr->initrd_size = load_image_targphys(initrd_filename,
2450 spapr->initrd_base,
2451 load_limit
2452 - spapr->initrd_base);
2453 if (spapr->initrd_size < 0) {
2454 error_report("could not load initial ram disk '%s'",
2455 initrd_filename);
2456 exit(1);
2457 }
2458 }
2459 }
2460
2461 if (bios_name == NULL) {
2462 bios_name = FW_FILE_NAME;
2463 }
2464 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
2465 if (!filename) {
2466 error_report("Could not find LPAR firmware '%s'", bios_name);
2467 exit(1);
2468 }
2469 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
2470 if (fw_size <= 0) {
2471 error_report("Could not load LPAR firmware '%s'", filename);
2472 exit(1);
2473 }
2474 g_free(filename);
2475
2476
2477
2478
2479 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
2480 register_savevm_live(NULL, "spapr/htab", -1, 1,
2481 &savevm_htab_handlers, spapr);
2482
2483 qemu_register_boot_set(spapr_boot_set, spapr);
2484
2485 if (kvm_enabled()) {
2486
2487 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change,
2488 &spapr->tb);
2489
2490 kvmppc_spapr_enable_inkernel_multitce();
2491 }
2492}
2493
2494static int spapr_kvm_type(const char *vm_type)
2495{
2496 if (!vm_type) {
2497 return 0;
2498 }
2499
2500 if (!strcmp(vm_type, "HV")) {
2501 return 1;
2502 }
2503
2504 if (!strcmp(vm_type, "PR")) {
2505 return 2;
2506 }
2507
2508 error_report("Unknown kvm-type specified '%s'", vm_type);
2509 exit(1);
2510}
2511
2512
2513
2514
2515
2516static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
2517 DeviceState *dev)
2518{
2519#define CAST(type, obj, name) \
2520 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2521 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
2522 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
2523 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON);
2524
2525 if (d) {
2526 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
2527 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
2528 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
2529
2530 if (spapr) {
2531
2532
2533
2534
2535
2536 unsigned id = 0x8000 | (d->id << 8) | d->lun;
2537 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2538 (uint64_t)id << 48);
2539 } else if (virtio) {
2540
2541
2542
2543
2544
2545
2546
2547 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
2548 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2549 (uint64_t)id << 32);
2550 } else if (usb) {
2551
2552
2553
2554
2555 unsigned usb_port = atoi(usb->port->path);
2556 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
2557 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2558 (uint64_t)id << 32);
2559 }
2560 }
2561
2562
2563
2564
2565
2566
2567
2568 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) {
2569 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE);
2570 if (usb_host_dev_is_scsi_storage(usbdev)) {
2571 return g_strdup_printf("storage@%s/disk", usbdev->port->path);
2572 }
2573 }
2574
2575 if (phb) {
2576
2577 return g_strdup_printf("pci@%"PRIX64, phb->buid);
2578 }
2579
2580 if (vsc) {
2581
2582 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun;
2583 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32);
2584 }
2585
2586 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) {
2587
2588 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE);
2589 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn));
2590 }
2591
2592 return NULL;
2593}
2594
2595static char *spapr_get_kvm_type(Object *obj, Error **errp)
2596{
2597 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2598
2599 return g_strdup(spapr->kvm_type);
2600}
2601
2602static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
2603{
2604 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2605
2606 g_free(spapr->kvm_type);
2607 spapr->kvm_type = g_strdup(value);
2608}
2609
2610static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp)
2611{
2612 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2613
2614 return spapr->use_hotplug_event_source;
2615}
2616
2617static void spapr_set_modern_hotplug_events(Object *obj, bool value,
2618 Error **errp)
2619{
2620 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2621
2622 spapr->use_hotplug_event_source = value;
2623}
2624
2625static char *spapr_get_resize_hpt(Object *obj, Error **errp)
2626{
2627 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2628
2629 switch (spapr->resize_hpt) {
2630 case SPAPR_RESIZE_HPT_DEFAULT:
2631 return g_strdup("default");
2632 case SPAPR_RESIZE_HPT_DISABLED:
2633 return g_strdup("disabled");
2634 case SPAPR_RESIZE_HPT_ENABLED:
2635 return g_strdup("enabled");
2636 case SPAPR_RESIZE_HPT_REQUIRED:
2637 return g_strdup("required");
2638 }
2639 g_assert_not_reached();
2640}
2641
2642static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp)
2643{
2644 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2645
2646 if (strcmp(value, "default") == 0) {
2647 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT;
2648 } else if (strcmp(value, "disabled") == 0) {
2649 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
2650 } else if (strcmp(value, "enabled") == 0) {
2651 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED;
2652 } else if (strcmp(value, "required") == 0) {
2653 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED;
2654 } else {
2655 error_setg(errp, "Bad value for \"resize-hpt\" property");
2656 }
2657}
2658
2659static void spapr_machine_initfn(Object *obj)
2660{
2661 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2662
2663 spapr->htab_fd = -1;
2664 spapr->use_hotplug_event_source = true;
2665 object_property_add_str(obj, "kvm-type",
2666 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
2667 object_property_set_description(obj, "kvm-type",
2668 "Specifies the KVM virtualization mode (HV, PR)",
2669 NULL);
2670 object_property_add_bool(obj, "modern-hotplug-events",
2671 spapr_get_modern_hotplug_events,
2672 spapr_set_modern_hotplug_events,
2673 NULL);
2674 object_property_set_description(obj, "modern-hotplug-events",
2675 "Use dedicated hotplug event mechanism in"
2676 " place of standard EPOW events when possible"
2677 " (required for memory hot-unplug support)",
2678 NULL);
2679
2680 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr,
2681 "Maximum permitted CPU compatibility mode",
2682 &error_fatal);
2683
2684 object_property_add_str(obj, "resize-hpt",
2685 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL);
2686 object_property_set_description(obj, "resize-hpt",
2687 "Resizing of the Hash Page Table (enabled, disabled, required)",
2688 NULL);
2689}
2690
2691static void spapr_machine_finalizefn(Object *obj)
2692{
2693 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2694
2695 g_free(spapr->kvm_type);
2696}
2697
2698void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg)
2699{
2700 cpu_synchronize_state(cs);
2701 ppc_cpu_do_system_reset(cs);
2702}
2703
2704static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
2705{
2706 CPUState *cs;
2707
2708 CPU_FOREACH(cs) {
2709 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
2710 }
2711}
2712
2713static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size,
2714 uint32_t node, bool dedicated_hp_event_source,
2715 Error **errp)
2716{
2717 sPAPRDRConnector *drc;
2718 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
2719 int i, fdt_offset, fdt_size;
2720 void *fdt;
2721 uint64_t addr = addr_start;
2722 bool hotplugged = spapr_drc_hotplugged(dev);
2723 Error *local_err = NULL;
2724
2725 for (i = 0; i < nr_lmbs; i++) {
2726 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
2727 addr / SPAPR_MEMORY_BLOCK_SIZE);
2728 g_assert(drc);
2729
2730 fdt = create_device_tree(&fdt_size);
2731 fdt_offset = spapr_populate_memory_node(fdt, node, addr,
2732 SPAPR_MEMORY_BLOCK_SIZE);
2733
2734 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err);
2735 if (local_err) {
2736 while (addr > addr_start) {
2737 addr -= SPAPR_MEMORY_BLOCK_SIZE;
2738 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
2739 addr / SPAPR_MEMORY_BLOCK_SIZE);
2740 spapr_drc_detach(drc);
2741 }
2742 g_free(fdt);
2743 error_propagate(errp, local_err);
2744 return;
2745 }
2746 if (!hotplugged) {
2747 spapr_drc_reset(drc);
2748 }
2749 addr += SPAPR_MEMORY_BLOCK_SIZE;
2750 }
2751
2752
2753
2754 if (hotplugged) {
2755 if (dedicated_hp_event_source) {
2756 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
2757 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
2758 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
2759 nr_lmbs,
2760 spapr_drc_index(drc));
2761 } else {
2762 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB,
2763 nr_lmbs);
2764 }
2765 }
2766}
2767
2768static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2769 uint32_t node, Error **errp)
2770{
2771 Error *local_err = NULL;
2772 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
2773 PCDIMMDevice *dimm = PC_DIMM(dev);
2774 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2775 MemoryRegion *mr;
2776 uint64_t align, size, addr;
2777
2778 mr = ddc->get_memory_region(dimm, &local_err);
2779 if (local_err) {
2780 goto out;
2781 }
2782 align = memory_region_get_alignment(mr);
2783 size = memory_region_size(mr);
2784
2785 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err);
2786 if (local_err) {
2787 goto out;
2788 }
2789
2790 addr = object_property_get_uint(OBJECT(dimm),
2791 PC_DIMM_ADDR_PROP, &local_err);
2792 if (local_err) {
2793 goto out_unplug;
2794 }
2795
2796 spapr_add_lmbs(dev, addr, size, node,
2797 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT),
2798 &local_err);
2799 if (local_err) {
2800 goto out_unplug;
2801 }
2802
2803 return;
2804
2805out_unplug:
2806 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
2807out:
2808 error_propagate(errp, local_err);
2809}
2810
2811static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2812 Error **errp)
2813{
2814 PCDIMMDevice *dimm = PC_DIMM(dev);
2815 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2816 MemoryRegion *mr;
2817 uint64_t size;
2818 char *mem_dev;
2819
2820 mr = ddc->get_memory_region(dimm, errp);
2821 if (!mr) {
2822 return;
2823 }
2824 size = memory_region_size(mr);
2825
2826 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
2827 error_setg(errp, "Hotplugged memory size must be a multiple of "
2828 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
2829 return;
2830 }
2831
2832 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL);
2833 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) {
2834 error_setg(errp, "Memory backend has bad page size. "
2835 "Use 'memory-backend-file' with correct mem-path.");
2836 goto out;
2837 }
2838
2839out:
2840 g_free(mem_dev);
2841}
2842
2843struct sPAPRDIMMState {
2844 PCDIMMDevice *dimm;
2845 uint32_t nr_lmbs;
2846 QTAILQ_ENTRY(sPAPRDIMMState) next;
2847};
2848
2849static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s,
2850 PCDIMMDevice *dimm)
2851{
2852 sPAPRDIMMState *dimm_state = NULL;
2853
2854 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) {
2855 if (dimm_state->dimm == dimm) {
2856 break;
2857 }
2858 }
2859 return dimm_state;
2860}
2861
2862static sPAPRDIMMState *spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr,
2863 uint32_t nr_lmbs,
2864 PCDIMMDevice *dimm)
2865{
2866 sPAPRDIMMState *ds = NULL;
2867
2868
2869
2870
2871
2872
2873
2874 ds = spapr_pending_dimm_unplugs_find(spapr, dimm);
2875 if (!ds) {
2876 ds = g_malloc0(sizeof(sPAPRDIMMState));
2877 ds->nr_lmbs = nr_lmbs;
2878 ds->dimm = dimm;
2879 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next);
2880 }
2881 return ds;
2882}
2883
2884static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr,
2885 sPAPRDIMMState *dimm_state)
2886{
2887 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next);
2888 g_free(dimm_state);
2889}
2890
2891static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms,
2892 PCDIMMDevice *dimm)
2893{
2894 sPAPRDRConnector *drc;
2895 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2896 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort);
2897 uint64_t size = memory_region_size(mr);
2898 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
2899 uint32_t avail_lmbs = 0;
2900 uint64_t addr_start, addr;
2901 int i;
2902
2903 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP,
2904 &error_abort);
2905
2906 addr = addr_start;
2907 for (i = 0; i < nr_lmbs; i++) {
2908 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
2909 addr / SPAPR_MEMORY_BLOCK_SIZE);
2910 g_assert(drc);
2911 if (drc->dev) {
2912 avail_lmbs++;
2913 }
2914 addr += SPAPR_MEMORY_BLOCK_SIZE;
2915 }
2916
2917 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm);
2918}
2919
2920
2921void spapr_lmb_release(DeviceState *dev)
2922{
2923 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_hotplug_handler(dev));
2924 PCDIMMDevice *dimm = PC_DIMM(dev);
2925 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2926 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort);
2927 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev));
2928
2929
2930
2931 if (ds == NULL) {
2932 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev));
2933 g_assert(ds);
2934
2935 g_assert(ds->nr_lmbs);
2936 }
2937
2938 if (--ds->nr_lmbs) {
2939 return;
2940 }
2941
2942 spapr_pending_dimm_unplugs_remove(spapr, ds);
2943
2944
2945
2946
2947
2948 pc_dimm_memory_unplug(dev, &spapr->hotplug_memory, mr);
2949 object_unparent(OBJECT(dev));
2950}
2951
2952static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev,
2953 DeviceState *dev, Error **errp)
2954{
2955 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
2956 Error *local_err = NULL;
2957 PCDIMMDevice *dimm = PC_DIMM(dev);
2958 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2959 MemoryRegion *mr;
2960 uint32_t nr_lmbs;
2961 uint64_t size, addr_start, addr;
2962 int i;
2963 sPAPRDRConnector *drc;
2964
2965 mr = ddc->get_memory_region(dimm, &local_err);
2966 if (local_err) {
2967 goto out;
2968 }
2969 size = memory_region_size(mr);
2970 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
2971
2972 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP,
2973 &local_err);
2974 if (local_err) {
2975 goto out;
2976 }
2977
2978 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm);
2979
2980 addr = addr_start;
2981 for (i = 0; i < nr_lmbs; i++) {
2982 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
2983 addr / SPAPR_MEMORY_BLOCK_SIZE);
2984 g_assert(drc);
2985
2986 spapr_drc_detach(drc);
2987 addr += SPAPR_MEMORY_BLOCK_SIZE;
2988 }
2989
2990 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
2991 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
2992 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
2993 nr_lmbs, spapr_drc_index(drc));
2994out:
2995 error_propagate(errp, local_err);
2996}
2997
2998static void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
2999 sPAPRMachineState *spapr)
3000{
3001 PowerPCCPU *cpu = POWERPC_CPU(cs);
3002 DeviceClass *dc = DEVICE_GET_CLASS(cs);
3003 int id = ppc_get_vcpu_dt_id(cpu);
3004 void *fdt;
3005 int offset, fdt_size;
3006 char *nodename;
3007
3008 fdt = create_device_tree(&fdt_size);
3009 nodename = g_strdup_printf("%s@%x", dc->fw_name, id);
3010 offset = fdt_add_subnode(fdt, 0, nodename);
3011
3012 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
3013 g_free(nodename);
3014
3015 *fdt_offset = offset;
3016 return fdt;
3017}
3018
3019
3020void spapr_core_release(DeviceState *dev)
3021{
3022 MachineState *ms = MACHINE(qdev_get_hotplug_handler(dev));
3023 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms);
3024 CPUCore *cc = CPU_CORE(dev);
3025 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL);
3026
3027 if (smc->pre_2_10_has_unused_icps) {
3028 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
3029 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(cc));
3030 const char *typename = object_class_get_name(scc->cpu_class);
3031 size_t size = object_type_get_instance_size(typename);
3032 int i;
3033
3034 for (i = 0; i < cc->nr_threads; i++) {
3035 CPUState *cs = CPU(sc->threads + i * size);
3036
3037 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index);
3038 }
3039 }
3040
3041 assert(core_slot);
3042 core_slot->cpu = NULL;
3043 object_unparent(OBJECT(dev));
3044}
3045
3046static
3047void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev,
3048 Error **errp)
3049{
3050 int index;
3051 sPAPRDRConnector *drc;
3052 CPUCore *cc = CPU_CORE(dev);
3053 int smt = kvmppc_smt_threads();
3054
3055 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) {
3056 error_setg(errp, "Unable to find CPU core with core-id: %d",
3057 cc->core_id);
3058 return;
3059 }
3060 if (index == 0) {
3061 error_setg(errp, "Boot CPU core may not be unplugged");
3062 return;
3063 }
3064
3065 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index * smt);
3066 g_assert(drc);
3067
3068 spapr_drc_detach(drc);
3069
3070 spapr_hotplug_req_remove_by_index(drc);
3071}
3072
3073static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3074 Error **errp)
3075{
3076 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3077 MachineClass *mc = MACHINE_GET_CLASS(spapr);
3078 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3079 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev));
3080 CPUCore *cc = CPU_CORE(dev);
3081 CPUState *cs = CPU(core->threads);
3082 sPAPRDRConnector *drc;
3083 Error *local_err = NULL;
3084 int smt = kvmppc_smt_threads();
3085 CPUArchId *core_slot;
3086 int index;
3087 bool hotplugged = spapr_drc_hotplugged(dev);
3088
3089 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3090 if (!core_slot) {
3091 error_setg(errp, "Unable to find CPU core with core-id: %d",
3092 cc->core_id);
3093 return;
3094 }
3095 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index * smt);
3096
3097 g_assert(drc || !mc->has_hotpluggable_cpus);
3098
3099 if (drc) {
3100 void *fdt;
3101 int fdt_offset;
3102
3103 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr);
3104
3105 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err);
3106 if (local_err) {
3107 g_free(fdt);
3108 error_propagate(errp, local_err);
3109 return;
3110 }
3111
3112 if (hotplugged) {
3113
3114
3115
3116
3117 spapr_hotplug_req_add_by_index(drc);
3118 } else {
3119 spapr_drc_reset(drc);
3120 }
3121 }
3122
3123 core_slot->cpu = OBJECT(dev);
3124
3125 if (smc->pre_2_10_has_unused_icps) {
3126 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(cc));
3127 const char *typename = object_class_get_name(scc->cpu_class);
3128 size_t size = object_type_get_instance_size(typename);
3129 int i;
3130
3131 for (i = 0; i < cc->nr_threads; i++) {
3132 sPAPRCPUCore *sc = SPAPR_CPU_CORE(dev);
3133 void *obj = sc->threads + i * size;
3134
3135 cs = CPU(obj);
3136 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index);
3137 }
3138 }
3139}
3140
3141static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3142 Error **errp)
3143{
3144 MachineState *machine = MACHINE(OBJECT(hotplug_dev));
3145 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
3146 Error *local_err = NULL;
3147 CPUCore *cc = CPU_CORE(dev);
3148 char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model);
3149 const char *type = object_get_typename(OBJECT(dev));
3150 CPUArchId *core_slot;
3151 int index;
3152
3153 if (dev->hotplugged && !mc->has_hotpluggable_cpus) {
3154 error_setg(&local_err, "CPU hotplug not supported for this machine");
3155 goto out;
3156 }
3157
3158 if (strcmp(base_core_type, type)) {
3159 error_setg(&local_err, "CPU core type should be %s", base_core_type);
3160 goto out;
3161 }
3162
3163 if (cc->core_id % smp_threads) {
3164 error_setg(&local_err, "invalid core id %d", cc->core_id);
3165 goto out;
3166 }
3167
3168
3169
3170
3171
3172
3173
3174 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) {
3175 error_setg(&local_err, "invalid nr-threads %d, must be %d",
3176 cc->nr_threads, smp_threads);
3177 goto out;
3178 }
3179
3180 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3181 if (!core_slot) {
3182 error_setg(&local_err, "core id %d out of range", cc->core_id);
3183 goto out;
3184 }
3185
3186 if (core_slot->cpu) {
3187 error_setg(&local_err, "core %d already populated", cc->core_id);
3188 goto out;
3189 }
3190
3191 numa_cpu_pre_plug(core_slot, dev, &local_err);
3192
3193out:
3194 g_free(base_core_type);
3195 error_propagate(errp, local_err);
3196}
3197
3198static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
3199 DeviceState *dev, Error **errp)
3200{
3201 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
3202
3203 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3204 int node;
3205
3206 if (!smc->dr_lmb_enabled) {
3207 error_setg(errp, "Memory hotplug not supported for this machine");
3208 return;
3209 }
3210 node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP, errp);
3211 if (*errp) {
3212 return;
3213 }
3214 if (node < 0 || node >= MAX_NODES) {
3215 error_setg(errp, "Invaild node %d", node);
3216 return;
3217 }
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235 if (nb_numa_nodes && !numa_info[node].node_mem) {
3236 error_setg(errp, "Can't hotplug memory to memory-less node %d",
3237 node);
3238 return;
3239 }
3240
3241 spapr_memory_plug(hotplug_dev, dev, node, errp);
3242 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3243 spapr_core_plug(hotplug_dev, dev, errp);
3244 }
3245}
3246
3247static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev,
3248 DeviceState *dev, Error **errp)
3249{
3250 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine());
3251 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
3252
3253 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3254 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) {
3255 spapr_memory_unplug_request(hotplug_dev, dev, errp);
3256 } else {
3257
3258
3259
3260
3261
3262
3263 error_setg(errp, "Memory hot unplug not supported for this guest");
3264 }
3265 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3266 if (!mc->has_hotpluggable_cpus) {
3267 error_setg(errp, "CPU hot unplug not supported on this machine");
3268 return;
3269 }
3270 spapr_core_unplug_request(hotplug_dev, dev, errp);
3271 }
3272}
3273
3274static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev,
3275 DeviceState *dev, Error **errp)
3276{
3277 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3278 spapr_memory_pre_plug(hotplug_dev, dev, errp);
3279 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3280 spapr_core_pre_plug(hotplug_dev, dev, errp);
3281 }
3282}
3283
3284static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine,
3285 DeviceState *dev)
3286{
3287 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
3288 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3289 return HOTPLUG_HANDLER(machine);
3290 }
3291 return NULL;
3292}
3293
3294static CpuInstanceProperties
3295spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index)
3296{
3297 CPUArchId *core_slot;
3298 MachineClass *mc = MACHINE_GET_CLASS(machine);
3299
3300
3301 mc->possible_cpu_arch_ids(machine);
3302
3303 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL);
3304 assert(core_slot);
3305 return core_slot->props;
3306}
3307
3308static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine)
3309{
3310 int i;
3311 int spapr_max_cores = max_cpus / smp_threads;
3312 MachineClass *mc = MACHINE_GET_CLASS(machine);
3313
3314 if (!mc->has_hotpluggable_cpus) {
3315 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads;
3316 }
3317 if (machine->possible_cpus) {
3318 assert(machine->possible_cpus->len == spapr_max_cores);
3319 return machine->possible_cpus;
3320 }
3321
3322 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
3323 sizeof(CPUArchId) * spapr_max_cores);
3324 machine->possible_cpus->len = spapr_max_cores;
3325 for (i = 0; i < machine->possible_cpus->len; i++) {
3326 int core_id = i * smp_threads;
3327
3328 machine->possible_cpus->cpus[i].vcpus_count = smp_threads;
3329 machine->possible_cpus->cpus[i].arch_id = core_id;
3330 machine->possible_cpus->cpus[i].props.has_core_id = true;
3331 machine->possible_cpus->cpus[i].props.core_id = core_id;
3332
3333
3334 if (nb_numa_nodes) {
3335
3336
3337
3338 machine->possible_cpus->cpus[i].props.node_id =
3339 core_id / smp_threads / smp_cores % nb_numa_nodes;
3340 }
3341 }
3342 return machine->possible_cpus;
3343}
3344
3345static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index,
3346 uint64_t *buid, hwaddr *pio,
3347 hwaddr *mmio32, hwaddr *mmio64,
3348 unsigned n_dma, uint32_t *liobns, Error **errp)
3349{
3350
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365 const uint64_t base_buid = 0x800000020000000ULL;
3366#define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \
3367 SPAPR_PCI_MEM64_WIN_SIZE - 1)
3368 int i;
3369
3370
3371 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
3372 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
3373 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0);
3374 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0);
3375
3376 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) >
3377 SPAPR_PCI_MEM32_WIN_SIZE);
3378 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) >
3379 SPAPR_PCI_MEM64_WIN_SIZE);
3380
3381 if (index >= SPAPR_MAX_PHBS) {
3382 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)",
3383 SPAPR_MAX_PHBS - 1);
3384 return;
3385 }
3386
3387 *buid = base_buid + index;
3388 for (i = 0; i < n_dma; ++i) {
3389 liobns[i] = SPAPR_PCI_LIOBN(index, i);
3390 }
3391
3392 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE;
3393 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE;
3394 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE;
3395}
3396
3397static ICSState *spapr_ics_get(XICSFabric *dev, int irq)
3398{
3399 sPAPRMachineState *spapr = SPAPR_MACHINE(dev);
3400
3401 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL;
3402}
3403
3404static void spapr_ics_resend(XICSFabric *dev)
3405{
3406 sPAPRMachineState *spapr = SPAPR_MACHINE(dev);
3407
3408 ics_resend(spapr->ics);
3409}
3410
3411static ICPState *spapr_icp_get(XICSFabric *xi, int cpu_dt_id)
3412{
3413 PowerPCCPU *cpu = ppc_get_vcpu_by_dt_id(cpu_dt_id);
3414
3415 return cpu ? ICP(cpu->intc) : NULL;
3416}
3417
3418static void spapr_pic_print_info(InterruptStatsProvider *obj,
3419 Monitor *mon)
3420{
3421 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3422 CPUState *cs;
3423
3424 CPU_FOREACH(cs) {
3425 PowerPCCPU *cpu = POWERPC_CPU(cs);
3426
3427 icp_pic_print_info(ICP(cpu->intc), mon);
3428 }
3429
3430 ics_pic_print_info(spapr->ics, mon);
3431}
3432
3433static void spapr_machine_class_init(ObjectClass *oc, void *data)
3434{
3435 MachineClass *mc = MACHINE_CLASS(oc);
3436 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
3437 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
3438 NMIClass *nc = NMI_CLASS(oc);
3439 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
3440 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc);
3441 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
3442 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
3443
3444 mc->desc = "pSeries Logical Partition (PAPR compliant)";
3445
3446
3447
3448
3449
3450
3451 mc->init = ppc_spapr_init;
3452 mc->reset = ppc_spapr_reset;
3453 mc->block_default_type = IF_SCSI;
3454 mc->max_cpus = 1024;
3455 mc->no_parallel = 1;
3456 mc->default_boot_order = "";
3457 mc->default_ram_size = 512 * M_BYTE;
3458 mc->kvm_type = spapr_kvm_type;
3459 mc->has_dynamic_sysbus = true;
3460 mc->pci_allow_0_address = true;
3461 mc->get_hotplug_handler = spapr_get_hotplug_handler;
3462 hc->pre_plug = spapr_machine_device_pre_plug;
3463 hc->plug = spapr_machine_device_plug;
3464 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props;
3465 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids;
3466 hc->unplug_request = spapr_machine_device_unplug_request;
3467
3468 smc->dr_lmb_enabled = true;
3469 smc->tcg_default_cpu = "POWER8";
3470 mc->has_hotpluggable_cpus = true;
3471 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED;
3472 fwc->get_dev_path = spapr_get_fw_dev_path;
3473 nc->nmi_monitor_handler = spapr_nmi;
3474 smc->phb_placement = spapr_phb_placement;
3475 vhc->hypercall = emulate_spapr_hypercall;
3476 vhc->hpt_mask = spapr_hpt_mask;
3477 vhc->map_hptes = spapr_map_hptes;
3478 vhc->unmap_hptes = spapr_unmap_hptes;
3479 vhc->store_hpte = spapr_store_hpte;
3480 vhc->get_patbe = spapr_get_patbe;
3481 xic->ics_get = spapr_ics_get;
3482 xic->ics_resend = spapr_ics_resend;
3483 xic->icp_get = spapr_icp_get;
3484 ispc->print_info = spapr_pic_print_info;
3485
3486
3487
3488
3489 mc->numa_mem_align_shift = 28;
3490}
3491
3492static const TypeInfo spapr_machine_info = {
3493 .name = TYPE_SPAPR_MACHINE,
3494 .parent = TYPE_MACHINE,
3495 .abstract = true,
3496 .instance_size = sizeof(sPAPRMachineState),
3497 .instance_init = spapr_machine_initfn,
3498 .instance_finalize = spapr_machine_finalizefn,
3499 .class_size = sizeof(sPAPRMachineClass),
3500 .class_init = spapr_machine_class_init,
3501 .interfaces = (InterfaceInfo[]) {
3502 { TYPE_FW_PATH_PROVIDER },
3503 { TYPE_NMI },
3504 { TYPE_HOTPLUG_HANDLER },
3505 { TYPE_PPC_VIRTUAL_HYPERVISOR },
3506 { TYPE_XICS_FABRIC },
3507 { TYPE_INTERRUPT_STATS_PROVIDER },
3508 { }
3509 },
3510};
3511
3512#define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
3513 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
3514 void *data) \
3515 { \
3516 MachineClass *mc = MACHINE_CLASS(oc); \
3517 spapr_machine_##suffix##_class_options(mc); \
3518 if (latest) { \
3519 mc->alias = "pseries"; \
3520 mc->is_default = 1; \
3521 } \
3522 } \
3523 static void spapr_machine_##suffix##_instance_init(Object *obj) \
3524 { \
3525 MachineState *machine = MACHINE(obj); \
3526 spapr_machine_##suffix##_instance_options(machine); \
3527 } \
3528 static const TypeInfo spapr_machine_##suffix##_info = { \
3529 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
3530 .parent = TYPE_SPAPR_MACHINE, \
3531 .class_init = spapr_machine_##suffix##_class_init, \
3532 .instance_init = spapr_machine_##suffix##_instance_init, \
3533 }; \
3534 static void spapr_machine_register_##suffix(void) \
3535 { \
3536 type_register(&spapr_machine_##suffix##_info); \
3537 } \
3538 type_init(spapr_machine_register_##suffix)
3539
3540
3541
3542
3543static void spapr_machine_2_10_instance_options(MachineState *machine)
3544{
3545}
3546
3547static void spapr_machine_2_10_class_options(MachineClass *mc)
3548{
3549
3550}
3551
3552DEFINE_SPAPR_MACHINE(2_10, "2.10", true);
3553
3554
3555
3556
3557#define SPAPR_COMPAT_2_9 \
3558 HW_COMPAT_2_9 \
3559 { \
3560 .driver = TYPE_POWERPC_CPU, \
3561 .property = "pre-2.10-migration", \
3562 .value = "on", \
3563 }, \
3564
3565static void spapr_machine_2_9_instance_options(MachineState *machine)
3566{
3567 spapr_machine_2_10_instance_options(machine);
3568}
3569
3570static void spapr_machine_2_9_class_options(MachineClass *mc)
3571{
3572 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3573
3574 spapr_machine_2_10_class_options(mc);
3575 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9);
3576 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram;
3577 smc->pre_2_10_has_unused_icps = true;
3578 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED;
3579}
3580
3581DEFINE_SPAPR_MACHINE(2_9, "2.9", false);
3582
3583
3584
3585
3586#define SPAPR_COMPAT_2_8 \
3587 HW_COMPAT_2_8 \
3588 { \
3589 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3590 .property = "pcie-extended-configuration-space", \
3591 .value = "off", \
3592 },
3593
3594static void spapr_machine_2_8_instance_options(MachineState *machine)
3595{
3596 spapr_machine_2_9_instance_options(machine);
3597}
3598
3599static void spapr_machine_2_8_class_options(MachineClass *mc)
3600{
3601 spapr_machine_2_9_class_options(mc);
3602 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8);
3603 mc->numa_mem_align_shift = 23;
3604}
3605
3606DEFINE_SPAPR_MACHINE(2_8, "2.8", false);
3607
3608
3609
3610
3611#define SPAPR_COMPAT_2_7 \
3612 HW_COMPAT_2_7 \
3613 { \
3614 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3615 .property = "mem_win_size", \
3616 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\
3617 }, \
3618 { \
3619 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3620 .property = "mem64_win_size", \
3621 .value = "0", \
3622 }, \
3623 { \
3624 .driver = TYPE_POWERPC_CPU, \
3625 .property = "pre-2.8-migration", \
3626 .value = "on", \
3627 }, \
3628 { \
3629 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3630 .property = "pre-2.8-migration", \
3631 .value = "on", \
3632 },
3633
3634static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index,
3635 uint64_t *buid, hwaddr *pio,
3636 hwaddr *mmio32, hwaddr *mmio64,
3637 unsigned n_dma, uint32_t *liobns, Error **errp)
3638{
3639
3640 const uint64_t base_buid = 0x800000020000000ULL;
3641 const hwaddr phb_spacing = 0x1000000000ULL;
3642 const hwaddr mmio_offset = 0xa0000000;
3643 const hwaddr pio_offset = 0x80000000;
3644 const uint32_t max_index = 255;
3645 const hwaddr phb0_alignment = 0x10000000000ULL;
3646
3647 uint64_t ram_top = MACHINE(spapr)->ram_size;
3648 hwaddr phb0_base, phb_base;
3649 int i;
3650
3651
3652 if (MACHINE(spapr)->maxram_size > ram_top) {
3653
3654
3655
3656 ram_top = spapr->hotplug_memory.base +
3657 memory_region_size(&spapr->hotplug_memory.mr);
3658 }
3659
3660 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment);
3661
3662 if (index > max_index) {
3663 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)",
3664 max_index);
3665 return;
3666 }
3667
3668 *buid = base_buid + index;
3669 for (i = 0; i < n_dma; ++i) {
3670 liobns[i] = SPAPR_PCI_LIOBN(index, i);
3671 }
3672
3673 phb_base = phb0_base + index * phb_spacing;
3674 *pio = phb_base + pio_offset;
3675 *mmio32 = phb_base + mmio_offset;
3676
3677
3678
3679
3680
3681}
3682
3683static void spapr_machine_2_7_instance_options(MachineState *machine)
3684{
3685 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
3686
3687 spapr_machine_2_8_instance_options(machine);
3688 spapr->use_hotplug_event_source = false;
3689}
3690
3691static void spapr_machine_2_7_class_options(MachineClass *mc)
3692{
3693 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3694
3695 spapr_machine_2_8_class_options(mc);
3696 smc->tcg_default_cpu = "POWER7";
3697 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7);
3698 smc->phb_placement = phb_placement_2_7;
3699}
3700
3701DEFINE_SPAPR_MACHINE(2_7, "2.7", false);
3702
3703
3704
3705
3706#define SPAPR_COMPAT_2_6 \
3707 HW_COMPAT_2_6 \
3708 { \
3709 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
3710 .property = "ddw",\
3711 .value = stringify(off),\
3712 },
3713
3714static void spapr_machine_2_6_instance_options(MachineState *machine)
3715{
3716 spapr_machine_2_7_instance_options(machine);
3717}
3718
3719static void spapr_machine_2_6_class_options(MachineClass *mc)
3720{
3721 spapr_machine_2_7_class_options(mc);
3722 mc->has_hotpluggable_cpus = false;
3723 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6);
3724}
3725
3726DEFINE_SPAPR_MACHINE(2_6, "2.6", false);
3727
3728
3729
3730
3731#define SPAPR_COMPAT_2_5 \
3732 HW_COMPAT_2_5 \
3733 { \
3734 .driver = "spapr-vlan", \
3735 .property = "use-rx-buffer-pools", \
3736 .value = "off", \
3737 },
3738
3739static void spapr_machine_2_5_instance_options(MachineState *machine)
3740{
3741 spapr_machine_2_6_instance_options(machine);
3742}
3743
3744static void spapr_machine_2_5_class_options(MachineClass *mc)
3745{
3746 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3747
3748 spapr_machine_2_6_class_options(mc);
3749 smc->use_ohci_by_default = true;
3750 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5);
3751}
3752
3753DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
3754
3755
3756
3757
3758#define SPAPR_COMPAT_2_4 \
3759 HW_COMPAT_2_4
3760
3761static void spapr_machine_2_4_instance_options(MachineState *machine)
3762{
3763 spapr_machine_2_5_instance_options(machine);
3764}
3765
3766static void spapr_machine_2_4_class_options(MachineClass *mc)
3767{
3768 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3769
3770 spapr_machine_2_5_class_options(mc);
3771 smc->dr_lmb_enabled = false;
3772 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4);
3773}
3774
3775DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
3776
3777
3778
3779
3780#define SPAPR_COMPAT_2_3 \
3781 HW_COMPAT_2_3 \
3782 {\
3783 .driver = "spapr-pci-host-bridge",\
3784 .property = "dynamic-reconfiguration",\
3785 .value = "off",\
3786 },
3787
3788static void spapr_machine_2_3_instance_options(MachineState *machine)
3789{
3790 spapr_machine_2_4_instance_options(machine);
3791}
3792
3793static void spapr_machine_2_3_class_options(MachineClass *mc)
3794{
3795 spapr_machine_2_4_class_options(mc);
3796 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3);
3797}
3798DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
3799
3800
3801
3802
3803
3804#define SPAPR_COMPAT_2_2 \
3805 HW_COMPAT_2_2 \
3806 {\
3807 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
3808 .property = "mem_win_size",\
3809 .value = "0x20000000",\
3810 },
3811
3812static void spapr_machine_2_2_instance_options(MachineState *machine)
3813{
3814 spapr_machine_2_3_instance_options(machine);
3815 machine->suppress_vmdesc = true;
3816}
3817
3818static void spapr_machine_2_2_class_options(MachineClass *mc)
3819{
3820 spapr_machine_2_3_class_options(mc);
3821 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2);
3822}
3823DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
3824
3825
3826
3827
3828#define SPAPR_COMPAT_2_1 \
3829 HW_COMPAT_2_1
3830
3831static void spapr_machine_2_1_instance_options(MachineState *machine)
3832{
3833 spapr_machine_2_2_instance_options(machine);
3834}
3835
3836static void spapr_machine_2_1_class_options(MachineClass *mc)
3837{
3838 spapr_machine_2_2_class_options(mc);
3839 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1);
3840}
3841DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
3842
3843static void spapr_machine_register_types(void)
3844{
3845 type_register_static(&spapr_machine_info);
3846}
3847
3848type_init(spapr_machine_register_types)
3849