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14#include "qemu/osdep.h"
15#include "qemu-common.h"
16#include "cpu.h"
17#include "s390-pci-inst.h"
18#include "s390-pci-bus.h"
19#include "exec/memory-internal.h"
20#include "qemu/error-report.h"
21#include "sysemu/hw_accel.h"
22
23#ifndef DEBUG_S390PCI_INST
24#define DEBUG_S390PCI_INST 0
25#endif
26
27#define DPRINTF(fmt, ...) \
28 do { \
29 if (DEBUG_S390PCI_INST) { \
30 fprintf(stderr, "s390pci-inst: " fmt, ## __VA_ARGS__); \
31 } \
32 } while (0)
33
34static void s390_set_status_code(CPUS390XState *env,
35 uint8_t r, uint64_t status_code)
36{
37 env->regs[r] &= ~0xff000000ULL;
38 env->regs[r] |= (status_code & 0xff) << 24;
39}
40
41static int list_pci(ClpReqRspListPci *rrb, uint8_t *cc)
42{
43 S390PCIBusDevice *pbdev = NULL;
44 S390pciState *s = s390_get_phb();
45 uint32_t res_code, initial_l2, g_l2;
46 int rc, i;
47 uint64_t resume_token;
48
49 rc = 0;
50 if (lduw_p(&rrb->request.hdr.len) != 32) {
51 res_code = CLP_RC_LEN;
52 rc = -EINVAL;
53 goto out;
54 }
55
56 if ((ldl_p(&rrb->request.fmt) & CLP_MASK_FMT) != 0) {
57 res_code = CLP_RC_FMT;
58 rc = -EINVAL;
59 goto out;
60 }
61
62 if ((ldl_p(&rrb->request.fmt) & ~CLP_MASK_FMT) != 0 ||
63 ldq_p(&rrb->request.reserved1) != 0) {
64 res_code = CLP_RC_RESNOT0;
65 rc = -EINVAL;
66 goto out;
67 }
68
69 resume_token = ldq_p(&rrb->request.resume_token);
70
71 if (resume_token) {
72 pbdev = s390_pci_find_dev_by_idx(s, resume_token);
73 if (!pbdev) {
74 res_code = CLP_RC_LISTPCI_BADRT;
75 rc = -EINVAL;
76 goto out;
77 }
78 } else {
79 pbdev = s390_pci_find_next_avail_dev(s, NULL);
80 }
81
82 if (lduw_p(&rrb->response.hdr.len) < 48) {
83 res_code = CLP_RC_8K;
84 rc = -EINVAL;
85 goto out;
86 }
87
88 initial_l2 = lduw_p(&rrb->response.hdr.len);
89 if ((initial_l2 - LIST_PCI_HDR_LEN) % sizeof(ClpFhListEntry)
90 != 0) {
91 res_code = CLP_RC_LEN;
92 rc = -EINVAL;
93 *cc = 3;
94 goto out;
95 }
96
97 stl_p(&rrb->response.fmt, 0);
98 stq_p(&rrb->response.reserved1, 0);
99 stl_p(&rrb->response.mdd, FH_MASK_SHM);
100 stw_p(&rrb->response.max_fn, PCI_MAX_FUNCTIONS);
101 rrb->response.flags = UID_CHECKING_ENABLED;
102 rrb->response.entry_size = sizeof(ClpFhListEntry);
103
104 i = 0;
105 g_l2 = LIST_PCI_HDR_LEN;
106 while (g_l2 < initial_l2 && pbdev) {
107 stw_p(&rrb->response.fh_list[i].device_id,
108 pci_get_word(pbdev->pdev->config + PCI_DEVICE_ID));
109 stw_p(&rrb->response.fh_list[i].vendor_id,
110 pci_get_word(pbdev->pdev->config + PCI_VENDOR_ID));
111
112 stl_p(&rrb->response.fh_list[i].config,
113 pbdev->state == ZPCI_FS_STANDBY ? 0 : 1 << 31);
114 stl_p(&rrb->response.fh_list[i].fid, pbdev->fid);
115 stl_p(&rrb->response.fh_list[i].fh, pbdev->fh);
116
117 g_l2 += sizeof(ClpFhListEntry);
118
119 DPRINTF("g_l2 %d vendor id 0x%x device id 0x%x fid 0x%x fh 0x%x\n",
120 g_l2,
121 lduw_p(&rrb->response.fh_list[i].vendor_id),
122 lduw_p(&rrb->response.fh_list[i].device_id),
123 ldl_p(&rrb->response.fh_list[i].fid),
124 ldl_p(&rrb->response.fh_list[i].fh));
125 pbdev = s390_pci_find_next_avail_dev(s, pbdev);
126 i++;
127 }
128
129 if (!pbdev) {
130 resume_token = 0;
131 } else {
132 resume_token = pbdev->fh & FH_MASK_INDEX;
133 }
134 stq_p(&rrb->response.resume_token, resume_token);
135 stw_p(&rrb->response.hdr.len, g_l2);
136 stw_p(&rrb->response.hdr.rsp, CLP_RC_OK);
137out:
138 if (rc) {
139 DPRINTF("list pci failed rc 0x%x\n", rc);
140 stw_p(&rrb->response.hdr.rsp, res_code);
141 }
142 return rc;
143}
144
145int clp_service_call(S390CPU *cpu, uint8_t r2)
146{
147 ClpReqHdr *reqh;
148 ClpRspHdr *resh;
149 S390PCIBusDevice *pbdev;
150 uint32_t req_len;
151 uint32_t res_len;
152 uint8_t buffer[4096 * 2];
153 uint8_t cc = 0;
154 CPUS390XState *env = &cpu->env;
155 S390pciState *s = s390_get_phb();
156 int i;
157
158 cpu_synchronize_state(CPU(cpu));
159
160 if (env->psw.mask & PSW_MASK_PSTATE) {
161 program_interrupt(env, PGM_PRIVILEGED, 4);
162 return 0;
163 }
164
165 if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer, sizeof(*reqh))) {
166 return 0;
167 }
168 reqh = (ClpReqHdr *)buffer;
169 req_len = lduw_p(&reqh->len);
170 if (req_len < 16 || req_len > 8184 || (req_len % 8 != 0)) {
171 program_interrupt(env, PGM_OPERAND, 4);
172 return 0;
173 }
174
175 if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer,
176 req_len + sizeof(*resh))) {
177 return 0;
178 }
179 resh = (ClpRspHdr *)(buffer + req_len);
180 res_len = lduw_p(&resh->len);
181 if (res_len < 8 || res_len > 8176 || (res_len % 8 != 0)) {
182 program_interrupt(env, PGM_OPERAND, 4);
183 return 0;
184 }
185 if ((req_len + res_len) > 8192) {
186 program_interrupt(env, PGM_OPERAND, 4);
187 return 0;
188 }
189
190 if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer,
191 req_len + res_len)) {
192 return 0;
193 }
194
195 if (req_len != 32) {
196 stw_p(&resh->rsp, CLP_RC_LEN);
197 goto out;
198 }
199
200 switch (lduw_p(&reqh->cmd)) {
201 case CLP_LIST_PCI: {
202 ClpReqRspListPci *rrb = (ClpReqRspListPci *)buffer;
203 list_pci(rrb, &cc);
204 break;
205 }
206 case CLP_SET_PCI_FN: {
207 ClpReqSetPci *reqsetpci = (ClpReqSetPci *)reqh;
208 ClpRspSetPci *ressetpci = (ClpRspSetPci *)resh;
209
210 pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqsetpci->fh));
211 if (!pbdev) {
212 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FH);
213 goto out;
214 }
215
216 switch (reqsetpci->oc) {
217 case CLP_SET_ENABLE_PCI_FN:
218 switch (reqsetpci->ndas) {
219 case 0:
220 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_DMAAS);
221 goto out;
222 case 1:
223 break;
224 default:
225 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_RES);
226 goto out;
227 }
228
229 if (pbdev->fh & FH_MASK_ENABLE) {
230 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);
231 goto out;
232 }
233
234 pbdev->fh |= FH_MASK_ENABLE;
235 pbdev->state = ZPCI_FS_ENABLED;
236 stl_p(&ressetpci->fh, pbdev->fh);
237 stw_p(&ressetpci->hdr.rsp, CLP_RC_OK);
238 break;
239 case CLP_SET_DISABLE_PCI_FN:
240 if (!(pbdev->fh & FH_MASK_ENABLE)) {
241 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);
242 goto out;
243 }
244 device_reset(DEVICE(pbdev));
245 pbdev->fh &= ~FH_MASK_ENABLE;
246 pbdev->state = ZPCI_FS_DISABLED;
247 stl_p(&ressetpci->fh, pbdev->fh);
248 stw_p(&ressetpci->hdr.rsp, CLP_RC_OK);
249 break;
250 default:
251 DPRINTF("unknown set pci command\n");
252 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);
253 break;
254 }
255 break;
256 }
257 case CLP_QUERY_PCI_FN: {
258 ClpReqQueryPci *reqquery = (ClpReqQueryPci *)reqh;
259 ClpRspQueryPci *resquery = (ClpRspQueryPci *)resh;
260
261 pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqquery->fh));
262 if (!pbdev) {
263 DPRINTF("query pci no pci dev\n");
264 stw_p(&resquery->hdr.rsp, CLP_RC_SETPCIFN_FH);
265 goto out;
266 }
267
268 for (i = 0; i < PCI_BAR_COUNT; i++) {
269 uint32_t data = pci_get_long(pbdev->pdev->config +
270 PCI_BASE_ADDRESS_0 + (i * 4));
271
272 stl_p(&resquery->bar[i], data);
273 resquery->bar_size[i] = pbdev->pdev->io_regions[i].size ?
274 ctz64(pbdev->pdev->io_regions[i].size) : 0;
275 DPRINTF("bar %d addr 0x%x size 0x%" PRIx64 "barsize 0x%x\n", i,
276 ldl_p(&resquery->bar[i]),
277 pbdev->pdev->io_regions[i].size,
278 resquery->bar_size[i]);
279 }
280
281 stq_p(&resquery->sdma, ZPCI_SDMA_ADDR);
282 stq_p(&resquery->edma, ZPCI_EDMA_ADDR);
283 stl_p(&resquery->fid, pbdev->fid);
284 stw_p(&resquery->pchid, 0);
285 stw_p(&resquery->ug, 1);
286 stl_p(&resquery->uid, pbdev->uid);
287 stw_p(&resquery->hdr.rsp, CLP_RC_OK);
288 break;
289 }
290 case CLP_QUERY_PCI_FNGRP: {
291 ClpRspQueryPciGrp *resgrp = (ClpRspQueryPciGrp *)resh;
292 resgrp->fr = 1;
293 stq_p(&resgrp->dasm, 0);
294 stq_p(&resgrp->msia, ZPCI_MSI_ADDR);
295 stw_p(&resgrp->mui, 0);
296 stw_p(&resgrp->i, 128);
297 resgrp->version = 0;
298
299 stw_p(&resgrp->hdr.rsp, CLP_RC_OK);
300 break;
301 }
302 default:
303 DPRINTF("unknown clp command\n");
304 stw_p(&resh->rsp, CLP_RC_CMD);
305 break;
306 }
307
308out:
309 if (s390_cpu_virt_mem_write(cpu, env->regs[r2], r2, buffer,
310 req_len + res_len)) {
311 return 0;
312 }
313 setcc(cpu, cc);
314 return 0;
315}
316
317int pcilg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2)
318{
319 CPUS390XState *env = &cpu->env;
320 S390PCIBusDevice *pbdev;
321 uint64_t offset;
322 uint64_t data;
323 MemoryRegion *mr;
324 MemTxResult result;
325 uint8_t len;
326 uint32_t fh;
327 uint8_t pcias;
328
329 cpu_synchronize_state(CPU(cpu));
330
331 if (env->psw.mask & PSW_MASK_PSTATE) {
332 program_interrupt(env, PGM_PRIVILEGED, 4);
333 return 0;
334 }
335
336 if (r2 & 0x1) {
337 program_interrupt(env, PGM_SPECIFICATION, 4);
338 return 0;
339 }
340
341 fh = env->regs[r2] >> 32;
342 pcias = (env->regs[r2] >> 16) & 0xf;
343 len = env->regs[r2] & 0xf;
344 offset = env->regs[r2 + 1];
345
346 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
347 if (!pbdev) {
348 DPRINTF("pcilg no pci dev\n");
349 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
350 return 0;
351 }
352
353 switch (pbdev->state) {
354 case ZPCI_FS_RESERVED:
355 case ZPCI_FS_STANDBY:
356 case ZPCI_FS_DISABLED:
357 case ZPCI_FS_PERMANENT_ERROR:
358 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
359 return 0;
360 case ZPCI_FS_ERROR:
361 setcc(cpu, ZPCI_PCI_LS_ERR);
362 s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED);
363 return 0;
364 default:
365 break;
366 }
367
368 if (pcias < 6) {
369 if ((8 - (offset & 0x7)) < len) {
370 program_interrupt(env, PGM_OPERAND, 4);
371 return 0;
372 }
373 mr = pbdev->pdev->io_regions[pcias].memory;
374 result = memory_region_dispatch_read(mr, offset, &data, len,
375 MEMTXATTRS_UNSPECIFIED);
376 if (result != MEMTX_OK) {
377 program_interrupt(env, PGM_OPERAND, 4);
378 return 0;
379 }
380 } else if (pcias == 15) {
381 if ((4 - (offset & 0x3)) < len) {
382 program_interrupt(env, PGM_OPERAND, 4);
383 return 0;
384 }
385 data = pci_host_config_read_common(
386 pbdev->pdev, offset, pci_config_size(pbdev->pdev), len);
387
388 switch (len) {
389 case 1:
390 break;
391 case 2:
392 data = bswap16(data);
393 break;
394 case 4:
395 data = bswap32(data);
396 break;
397 case 8:
398 data = bswap64(data);
399 break;
400 default:
401 program_interrupt(env, PGM_OPERAND, 4);
402 return 0;
403 }
404 } else {
405 DPRINTF("invalid space\n");
406 setcc(cpu, ZPCI_PCI_LS_ERR);
407 s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS);
408 return 0;
409 }
410
411 env->regs[r1] = data;
412 setcc(cpu, ZPCI_PCI_LS_OK);
413 return 0;
414}
415
416static void update_msix_table_msg_data(S390PCIBusDevice *pbdev, uint64_t offset,
417 uint64_t *data, uint8_t len)
418{
419 uint32_t val;
420 uint8_t *msg_data;
421
422 if (offset % PCI_MSIX_ENTRY_SIZE != 8) {
423 return;
424 }
425
426 if (len != 4) {
427 DPRINTF("access msix table msg data but len is %d\n", len);
428 return;
429 }
430
431 msg_data = (uint8_t *)data - offset % PCI_MSIX_ENTRY_SIZE +
432 PCI_MSIX_ENTRY_VECTOR_CTRL;
433 val = pci_get_long(msg_data) |
434 ((pbdev->fh & FH_MASK_INDEX) << ZPCI_MSI_VEC_BITS);
435 pci_set_long(msg_data, val);
436 DPRINTF("update msix msg_data to 0x%" PRIx64 "\n", *data);
437}
438
439static int trap_msix(S390PCIBusDevice *pbdev, uint64_t offset, uint8_t pcias)
440{
441 if (pbdev->msix.available && pbdev->msix.table_bar == pcias &&
442 offset >= pbdev->msix.table_offset &&
443 offset <= pbdev->msix.table_offset +
444 (pbdev->msix.entries - 1) * PCI_MSIX_ENTRY_SIZE) {
445 return 1;
446 } else {
447 return 0;
448 }
449}
450
451int pcistg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2)
452{
453 CPUS390XState *env = &cpu->env;
454 uint64_t offset, data;
455 S390PCIBusDevice *pbdev;
456 MemoryRegion *mr;
457 MemTxResult result;
458 uint8_t len;
459 uint32_t fh;
460 uint8_t pcias;
461
462 cpu_synchronize_state(CPU(cpu));
463
464 if (env->psw.mask & PSW_MASK_PSTATE) {
465 program_interrupt(env, PGM_PRIVILEGED, 4);
466 return 0;
467 }
468
469 if (r2 & 0x1) {
470 program_interrupt(env, PGM_SPECIFICATION, 4);
471 return 0;
472 }
473
474 fh = env->regs[r2] >> 32;
475 pcias = (env->regs[r2] >> 16) & 0xf;
476 len = env->regs[r2] & 0xf;
477 offset = env->regs[r2 + 1];
478
479 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
480 if (!pbdev) {
481 DPRINTF("pcistg no pci dev\n");
482 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
483 return 0;
484 }
485
486 switch (pbdev->state) {
487 case ZPCI_FS_RESERVED:
488 case ZPCI_FS_STANDBY:
489 case ZPCI_FS_DISABLED:
490 case ZPCI_FS_PERMANENT_ERROR:
491 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
492 return 0;
493 case ZPCI_FS_ERROR:
494 setcc(cpu, ZPCI_PCI_LS_ERR);
495 s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED);
496 return 0;
497 default:
498 break;
499 }
500
501 data = env->regs[r1];
502 if (pcias < 6) {
503 if ((8 - (offset & 0x7)) < len) {
504 program_interrupt(env, PGM_OPERAND, 4);
505 return 0;
506 }
507
508 if (trap_msix(pbdev, offset, pcias)) {
509 offset = offset - pbdev->msix.table_offset;
510 mr = &pbdev->pdev->msix_table_mmio;
511 update_msix_table_msg_data(pbdev, offset, &data, len);
512 } else {
513 mr = pbdev->pdev->io_regions[pcias].memory;
514 }
515
516 result = memory_region_dispatch_write(mr, offset, data, len,
517 MEMTXATTRS_UNSPECIFIED);
518 if (result != MEMTX_OK) {
519 program_interrupt(env, PGM_OPERAND, 4);
520 return 0;
521 }
522 } else if (pcias == 15) {
523 if ((4 - (offset & 0x3)) < len) {
524 program_interrupt(env, PGM_OPERAND, 4);
525 return 0;
526 }
527 switch (len) {
528 case 1:
529 break;
530 case 2:
531 data = bswap16(data);
532 break;
533 case 4:
534 data = bswap32(data);
535 break;
536 case 8:
537 data = bswap64(data);
538 break;
539 default:
540 program_interrupt(env, PGM_OPERAND, 4);
541 return 0;
542 }
543
544 pci_host_config_write_common(pbdev->pdev, offset,
545 pci_config_size(pbdev->pdev),
546 data, len);
547 } else {
548 DPRINTF("pcistg invalid space\n");
549 setcc(cpu, ZPCI_PCI_LS_ERR);
550 s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS);
551 return 0;
552 }
553
554 setcc(cpu, ZPCI_PCI_LS_OK);
555 return 0;
556}
557
558int rpcit_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2)
559{
560 CPUS390XState *env = &cpu->env;
561 uint32_t fh;
562 S390PCIBusDevice *pbdev;
563 S390PCIIOMMU *iommu;
564 hwaddr start, end;
565 IOMMUTLBEntry entry;
566 IOMMUMemoryRegion *iommu_mr;
567 IOMMUMemoryRegionClass *imrc;
568
569 cpu_synchronize_state(CPU(cpu));
570
571 if (env->psw.mask & PSW_MASK_PSTATE) {
572 program_interrupt(env, PGM_PRIVILEGED, 4);
573 goto out;
574 }
575
576 if (r2 & 0x1) {
577 program_interrupt(env, PGM_SPECIFICATION, 4);
578 goto out;
579 }
580
581 fh = env->regs[r1] >> 32;
582 start = env->regs[r2];
583 end = start + env->regs[r2 + 1];
584
585 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
586 if (!pbdev) {
587 DPRINTF("rpcit no pci dev\n");
588 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
589 goto out;
590 }
591
592 switch (pbdev->state) {
593 case ZPCI_FS_RESERVED:
594 case ZPCI_FS_STANDBY:
595 case ZPCI_FS_DISABLED:
596 case ZPCI_FS_PERMANENT_ERROR:
597 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
598 return 0;
599 case ZPCI_FS_ERROR:
600 setcc(cpu, ZPCI_PCI_LS_ERR);
601 s390_set_status_code(env, r1, ZPCI_MOD_ST_ERROR_RECOVER);
602 return 0;
603 default:
604 break;
605 }
606
607 iommu = pbdev->iommu;
608 if (!iommu->g_iota) {
609 pbdev->state = ZPCI_FS_ERROR;
610 setcc(cpu, ZPCI_PCI_LS_ERR);
611 s390_set_status_code(env, r1, ZPCI_PCI_ST_INSUF_RES);
612 s390_pci_generate_error_event(ERR_EVENT_INVALAS, pbdev->fh, pbdev->fid,
613 start, 0);
614 goto out;
615 }
616
617 if (end < iommu->pba || start > iommu->pal) {
618 pbdev->state = ZPCI_FS_ERROR;
619 setcc(cpu, ZPCI_PCI_LS_ERR);
620 s390_set_status_code(env, r1, ZPCI_PCI_ST_INSUF_RES);
621 s390_pci_generate_error_event(ERR_EVENT_OORANGE, pbdev->fh, pbdev->fid,
622 start, 0);
623 goto out;
624 }
625
626 iommu_mr = &iommu->iommu_mr;
627 imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
628
629 while (start < end) {
630 entry = imrc->translate(iommu_mr, start, IOMMU_NONE);
631
632 if (!entry.translated_addr) {
633 pbdev->state = ZPCI_FS_ERROR;
634 setcc(cpu, ZPCI_PCI_LS_ERR);
635 s390_set_status_code(env, r1, ZPCI_PCI_ST_INSUF_RES);
636 s390_pci_generate_error_event(ERR_EVENT_SERR, pbdev->fh, pbdev->fid,
637 start, ERR_EVENT_Q_BIT);
638 goto out;
639 }
640
641 memory_region_notify_iommu(iommu_mr, entry);
642 start += entry.addr_mask + 1;
643 }
644
645 setcc(cpu, ZPCI_PCI_LS_OK);
646out:
647 return 0;
648}
649
650int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr,
651 uint8_t ar)
652{
653 CPUS390XState *env = &cpu->env;
654 S390PCIBusDevice *pbdev;
655 MemoryRegion *mr;
656 MemTxResult result;
657 int i;
658 uint32_t fh;
659 uint8_t pcias;
660 uint8_t len;
661 uint8_t buffer[128];
662
663 if (env->psw.mask & PSW_MASK_PSTATE) {
664 program_interrupt(env, PGM_PRIVILEGED, 6);
665 return 0;
666 }
667
668 fh = env->regs[r1] >> 32;
669 pcias = (env->regs[r1] >> 16) & 0xf;
670 len = env->regs[r1] & 0xff;
671
672 if (pcias > 5) {
673 DPRINTF("pcistb invalid space\n");
674 setcc(cpu, ZPCI_PCI_LS_ERR);
675 s390_set_status_code(env, r1, ZPCI_PCI_ST_INVAL_AS);
676 return 0;
677 }
678
679 switch (len) {
680 case 16:
681 case 32:
682 case 64:
683 case 128:
684 break;
685 default:
686 program_interrupt(env, PGM_SPECIFICATION, 6);
687 return 0;
688 }
689
690 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
691 if (!pbdev) {
692 DPRINTF("pcistb no pci dev fh 0x%x\n", fh);
693 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
694 return 0;
695 }
696
697 switch (pbdev->state) {
698 case ZPCI_FS_RESERVED:
699 case ZPCI_FS_STANDBY:
700 case ZPCI_FS_DISABLED:
701 case ZPCI_FS_PERMANENT_ERROR:
702 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
703 return 0;
704 case ZPCI_FS_ERROR:
705 setcc(cpu, ZPCI_PCI_LS_ERR);
706 s390_set_status_code(env, r1, ZPCI_PCI_ST_BLOCKED);
707 return 0;
708 default:
709 break;
710 }
711
712 mr = pbdev->pdev->io_regions[pcias].memory;
713 if (!memory_region_access_valid(mr, env->regs[r3], len, true)) {
714 program_interrupt(env, PGM_OPERAND, 6);
715 return 0;
716 }
717
718 if (s390_cpu_virt_mem_read(cpu, gaddr, ar, buffer, len)) {
719 return 0;
720 }
721
722 for (i = 0; i < len / 8; i++) {
723 result = memory_region_dispatch_write(mr, env->regs[r3] + i * 8,
724 ldq_p(buffer + i * 8), 8,
725 MEMTXATTRS_UNSPECIFIED);
726 if (result != MEMTX_OK) {
727 program_interrupt(env, PGM_OPERAND, 6);
728 return 0;
729 }
730 }
731
732 setcc(cpu, ZPCI_PCI_LS_OK);
733 return 0;
734}
735
736static int reg_irqs(CPUS390XState *env, S390PCIBusDevice *pbdev, ZpciFib fib)
737{
738 int ret, len;
739 uint8_t isc = FIB_DATA_ISC(ldl_p(&fib.data));
740
741 pbdev->routes.adapter.adapter_id = css_get_adapter_id(
742 CSS_IO_ADAPTER_PCI, isc);
743 pbdev->summary_ind = get_indicator(ldq_p(&fib.aisb), sizeof(uint64_t));
744 len = BITS_TO_LONGS(FIB_DATA_NOI(ldl_p(&fib.data))) * sizeof(unsigned long);
745 pbdev->indicator = get_indicator(ldq_p(&fib.aibv), len);
746
747 ret = map_indicator(&pbdev->routes.adapter, pbdev->summary_ind);
748 if (ret) {
749 goto out;
750 }
751
752 ret = map_indicator(&pbdev->routes.adapter, pbdev->indicator);
753 if (ret) {
754 goto out;
755 }
756
757 pbdev->routes.adapter.summary_addr = ldq_p(&fib.aisb);
758 pbdev->routes.adapter.summary_offset = FIB_DATA_AISBO(ldl_p(&fib.data));
759 pbdev->routes.adapter.ind_addr = ldq_p(&fib.aibv);
760 pbdev->routes.adapter.ind_offset = FIB_DATA_AIBVO(ldl_p(&fib.data));
761 pbdev->isc = isc;
762 pbdev->noi = FIB_DATA_NOI(ldl_p(&fib.data));
763 pbdev->sum = FIB_DATA_SUM(ldl_p(&fib.data));
764
765 DPRINTF("reg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id);
766 return 0;
767out:
768 release_indicator(&pbdev->routes.adapter, pbdev->summary_ind);
769 release_indicator(&pbdev->routes.adapter, pbdev->indicator);
770 pbdev->summary_ind = NULL;
771 pbdev->indicator = NULL;
772 return ret;
773}
774
775int pci_dereg_irqs(S390PCIBusDevice *pbdev)
776{
777 release_indicator(&pbdev->routes.adapter, pbdev->summary_ind);
778 release_indicator(&pbdev->routes.adapter, pbdev->indicator);
779
780 pbdev->summary_ind = NULL;
781 pbdev->indicator = NULL;
782 pbdev->routes.adapter.summary_addr = 0;
783 pbdev->routes.adapter.summary_offset = 0;
784 pbdev->routes.adapter.ind_addr = 0;
785 pbdev->routes.adapter.ind_offset = 0;
786 pbdev->isc = 0;
787 pbdev->noi = 0;
788 pbdev->sum = 0;
789
790 DPRINTF("dereg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id);
791 return 0;
792}
793
794static int reg_ioat(CPUS390XState *env, S390PCIIOMMU *iommu, ZpciFib fib)
795{
796 uint64_t pba = ldq_p(&fib.pba);
797 uint64_t pal = ldq_p(&fib.pal);
798 uint64_t g_iota = ldq_p(&fib.iota);
799 uint8_t dt = (g_iota >> 2) & 0x7;
800 uint8_t t = (g_iota >> 11) & 0x1;
801
802 if (pba > pal || pba < ZPCI_SDMA_ADDR || pal > ZPCI_EDMA_ADDR) {
803 program_interrupt(env, PGM_OPERAND, 6);
804 return -EINVAL;
805 }
806
807
808 if (!(dt == ZPCI_IOTA_RTTO && t)) {
809 error_report("unsupported ioat dt %d t %d", dt, t);
810 program_interrupt(env, PGM_OPERAND, 6);
811 return -EINVAL;
812 }
813
814 iommu->pba = pba;
815 iommu->pal = pal;
816 iommu->g_iota = g_iota;
817
818 s390_pci_iommu_enable(iommu);
819
820 return 0;
821}
822
823void pci_dereg_ioat(S390PCIIOMMU *iommu)
824{
825 s390_pci_iommu_disable(iommu);
826 iommu->pba = 0;
827 iommu->pal = 0;
828 iommu->g_iota = 0;
829}
830
831int mpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar)
832{
833 CPUS390XState *env = &cpu->env;
834 uint8_t oc, dmaas;
835 uint32_t fh;
836 ZpciFib fib;
837 S390PCIBusDevice *pbdev;
838 uint64_t cc = ZPCI_PCI_LS_OK;
839
840 if (env->psw.mask & PSW_MASK_PSTATE) {
841 program_interrupt(env, PGM_PRIVILEGED, 6);
842 return 0;
843 }
844
845 oc = env->regs[r1] & 0xff;
846 dmaas = (env->regs[r1] >> 16) & 0xff;
847 fh = env->regs[r1] >> 32;
848
849 if (fiba & 0x7) {
850 program_interrupt(env, PGM_SPECIFICATION, 6);
851 return 0;
852 }
853
854 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
855 if (!pbdev) {
856 DPRINTF("mpcifc no pci dev fh 0x%x\n", fh);
857 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
858 return 0;
859 }
860
861 switch (pbdev->state) {
862 case ZPCI_FS_RESERVED:
863 case ZPCI_FS_STANDBY:
864 case ZPCI_FS_DISABLED:
865 case ZPCI_FS_PERMANENT_ERROR:
866 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
867 return 0;
868 default:
869 break;
870 }
871
872 if (s390_cpu_virt_mem_read(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) {
873 return 0;
874 }
875
876 if (fib.fmt != 0) {
877 program_interrupt(env, PGM_OPERAND, 6);
878 return 0;
879 }
880
881 switch (oc) {
882 case ZPCI_MOD_FC_REG_INT:
883 if (pbdev->summary_ind) {
884 cc = ZPCI_PCI_LS_ERR;
885 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
886 } else if (reg_irqs(env, pbdev, fib)) {
887 cc = ZPCI_PCI_LS_ERR;
888 s390_set_status_code(env, r1, ZPCI_MOD_ST_RES_NOT_AVAIL);
889 }
890 break;
891 case ZPCI_MOD_FC_DEREG_INT:
892 if (!pbdev->summary_ind) {
893 cc = ZPCI_PCI_LS_ERR;
894 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
895 } else {
896 pci_dereg_irqs(pbdev);
897 }
898 break;
899 case ZPCI_MOD_FC_REG_IOAT:
900 if (dmaas != 0) {
901 cc = ZPCI_PCI_LS_ERR;
902 s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL);
903 } else if (pbdev->iommu->enabled) {
904 cc = ZPCI_PCI_LS_ERR;
905 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
906 } else if (reg_ioat(env, pbdev->iommu, fib)) {
907 cc = ZPCI_PCI_LS_ERR;
908 s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES);
909 }
910 break;
911 case ZPCI_MOD_FC_DEREG_IOAT:
912 if (dmaas != 0) {
913 cc = ZPCI_PCI_LS_ERR;
914 s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL);
915 } else if (!pbdev->iommu->enabled) {
916 cc = ZPCI_PCI_LS_ERR;
917 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
918 } else {
919 pci_dereg_ioat(pbdev->iommu);
920 }
921 break;
922 case ZPCI_MOD_FC_REREG_IOAT:
923 if (dmaas != 0) {
924 cc = ZPCI_PCI_LS_ERR;
925 s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL);
926 } else if (!pbdev->iommu->enabled) {
927 cc = ZPCI_PCI_LS_ERR;
928 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
929 } else {
930 pci_dereg_ioat(pbdev->iommu);
931 if (reg_ioat(env, pbdev->iommu, fib)) {
932 cc = ZPCI_PCI_LS_ERR;
933 s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES);
934 }
935 }
936 break;
937 case ZPCI_MOD_FC_RESET_ERROR:
938 switch (pbdev->state) {
939 case ZPCI_FS_BLOCKED:
940 case ZPCI_FS_ERROR:
941 pbdev->state = ZPCI_FS_ENABLED;
942 break;
943 default:
944 cc = ZPCI_PCI_LS_ERR;
945 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
946 }
947 break;
948 case ZPCI_MOD_FC_RESET_BLOCK:
949 switch (pbdev->state) {
950 case ZPCI_FS_ERROR:
951 pbdev->state = ZPCI_FS_BLOCKED;
952 break;
953 default:
954 cc = ZPCI_PCI_LS_ERR;
955 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
956 }
957 break;
958 case ZPCI_MOD_FC_SET_MEASURE:
959 pbdev->fmb_addr = ldq_p(&fib.fmb_addr);
960 break;
961 default:
962 program_interrupt(&cpu->env, PGM_OPERAND, 6);
963 cc = ZPCI_PCI_LS_ERR;
964 }
965
966 setcc(cpu, cc);
967 return 0;
968}
969
970int stpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar)
971{
972 CPUS390XState *env = &cpu->env;
973 uint8_t dmaas;
974 uint32_t fh;
975 ZpciFib fib;
976 S390PCIBusDevice *pbdev;
977 uint32_t data;
978 uint64_t cc = ZPCI_PCI_LS_OK;
979
980 if (env->psw.mask & PSW_MASK_PSTATE) {
981 program_interrupt(env, PGM_PRIVILEGED, 6);
982 return 0;
983 }
984
985 fh = env->regs[r1] >> 32;
986 dmaas = (env->regs[r1] >> 16) & 0xff;
987
988 if (dmaas) {
989 setcc(cpu, ZPCI_PCI_LS_ERR);
990 s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_INVAL_DMAAS);
991 return 0;
992 }
993
994 if (fiba & 0x7) {
995 program_interrupt(env, PGM_SPECIFICATION, 6);
996 return 0;
997 }
998
999 pbdev = s390_pci_find_dev_by_idx(s390_get_phb(), fh & FH_MASK_INDEX);
1000 if (!pbdev) {
1001 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
1002 return 0;
1003 }
1004
1005 memset(&fib, 0, sizeof(fib));
1006
1007 switch (pbdev->state) {
1008 case ZPCI_FS_RESERVED:
1009 case ZPCI_FS_STANDBY:
1010 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
1011 return 0;
1012 case ZPCI_FS_DISABLED:
1013 if (fh & FH_MASK_ENABLE) {
1014 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
1015 return 0;
1016 }
1017 goto out;
1018
1019
1020 case ZPCI_FS_ERROR:
1021 fib.fc |= 0x20;
1022 case ZPCI_FS_BLOCKED:
1023 fib.fc |= 0x40;
1024 case ZPCI_FS_ENABLED:
1025 fib.fc |= 0x80;
1026 if (pbdev->iommu->enabled) {
1027 fib.fc |= 0x10;
1028 }
1029 if (!(fh & FH_MASK_ENABLE)) {
1030 env->regs[r1] |= 1ULL << 63;
1031 }
1032 break;
1033 case ZPCI_FS_PERMANENT_ERROR:
1034 setcc(cpu, ZPCI_PCI_LS_ERR);
1035 s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_PERM_ERROR);
1036 return 0;
1037 }
1038
1039 stq_p(&fib.pba, pbdev->iommu->pba);
1040 stq_p(&fib.pal, pbdev->iommu->pal);
1041 stq_p(&fib.iota, pbdev->iommu->g_iota);
1042 stq_p(&fib.aibv, pbdev->routes.adapter.ind_addr);
1043 stq_p(&fib.aisb, pbdev->routes.adapter.summary_addr);
1044 stq_p(&fib.fmb_addr, pbdev->fmb_addr);
1045
1046 data = ((uint32_t)pbdev->isc << 28) | ((uint32_t)pbdev->noi << 16) |
1047 ((uint32_t)pbdev->routes.adapter.ind_offset << 8) |
1048 ((uint32_t)pbdev->sum << 7) | pbdev->routes.adapter.summary_offset;
1049 stl_p(&fib.data, data);
1050
1051out:
1052 if (s390_cpu_virt_mem_write(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) {
1053 return 0;
1054 }
1055
1056 setcc(cpu, cc);
1057 return 0;
1058}
1059
