LXR qemu/include/hw/arm/armv7m.h

   1/*
   2 * ARMv7M CPU object
   3 *
   4 * Copyright (c) 2017 Linaro Ltd
   5 * Written by Peter Maydell <peter.maydell@linaro.org>
   6 *
   7 * This code is licensed under the GPL version 2 or later.
   8 */
   9
  10#ifndef HW_ARM_ARMV7M_H
  11#define HW_ARM_ARMV7M_H
  12
  13#include "hw/sysbus.h"
  14#include "hw/arm/armv7m_nvic.h"
  15
  16#define TYPE_BITBAND "ARM,bitband-memory"
  17#define BITBAND(obj) OBJECT_CHECK(BitBandState, (obj), TYPE_BITBAND)
  18
  19typedef struct {
  20    /*< private >*/
  21    SysBusDevice parent_obj;
  22    /*< public >*/
  23
  24    AddressSpace *source_as;
  25    MemoryRegion iomem;
  26    uint32_t base;
  27    MemoryRegion *source_memory;
  28} BitBandState;
  29
  30#define TYPE_ARMV7M "armv7m"
  31#define ARMV7M(obj) OBJECT_CHECK(ARMv7MState, (obj), TYPE_ARMV7M)
  32
  33#define ARMV7M_NUM_BITBANDS 2
  34
  35/* ARMv7M container object.
  36 * + Unnamed GPIO input lines: external IRQ lines for the NVIC
  37 * + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ
  38 * + Property "cpu-model": CPU model to instantiate
  39 * + Property "num-irq": number of external IRQ lines
  40 * + Property "memory": MemoryRegion defining the physical address space
  41 *   that CPU accesses see. (The NVIC, bitbanding and other CPU-internal
  42 *   devices will be automatically layered on top of this view.)
  43 */
  44typedef struct ARMv7MState {
  45    /*< private >*/
  46    SysBusDevice parent_obj;
  47    /*< public >*/
  48    NVICState nvic;
  49    BitBandState bitband[ARMV7M_NUM_BITBANDS];
  50    ARMCPU *cpu;
  51
  52    /* MemoryRegion we pass to the CPU, with our devices layered on
  53     * top of the ones the board provides in board_memory.
  54     */
  55    MemoryRegion container;
  56
  57    /* Properties */
  58    char *cpu_model;
  59    /* MemoryRegion the board provides to us (with its devices, RAM, etc) */
  60    MemoryRegion *board_memory;
  61} ARMv7MState;
  62
  63#endif
  64