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21#ifndef CRIS_CPU_H
22#define CRIS_CPU_H
23
24#include "qemu-common.h"
25#include "cpu-qom.h"
26
27#define TARGET_LONG_BITS 32
28
29#define CPUArchState struct CPUCRISState
30
31#include "exec/cpu-defs.h"
32
33#define EXCP_NMI 1
34#define EXCP_GURU 2
35#define EXCP_BUSFAULT 3
36#define EXCP_IRQ 4
37#define EXCP_BREAK 5
38
39
40#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
41
42
43#define CRIS_CPU_IRQ 0
44#define CRIS_CPU_NMI 1
45
46
47#define R_FP 8
48#define R_SP 14
49#define R_ACR 15
50
51
52#define PR_BZ 0
53#define PR_VR 1
54#define PR_PID 2
55#define PR_SRS 3
56#define PR_WZ 4
57#define PR_EXS 5
58#define PR_EDA 6
59#define PR_PREFIX 6
60#define PR_MOF 7
61#define PR_DZ 8
62#define PR_EBP 9
63#define PR_ERP 10
64#define PR_SRP 11
65#define PR_NRP 12
66#define PR_CCS 13
67#define PR_USP 14
68#define PRV10_BRP 14
69#define PR_SPC 15
70
71
72#define Q_FLAG 0x80000000
73#define M_FLAG_V32 0x40000000
74#define PFIX_FLAG 0x800
75#define F_FLAG_V10 0x400
76#define P_FLAG_V10 0x200
77#define S_FLAG 0x200
78#define R_FLAG 0x100
79#define P_FLAG 0x80
80#define M_FLAG_V10 0x80
81#define U_FLAG 0x40
82#define I_FLAG 0x20
83#define X_FLAG 0x10
84#define N_FLAG 0x08
85#define Z_FLAG 0x04
86#define V_FLAG 0x02
87#define C_FLAG 0x01
88#define ALU_FLAGS 0x1F
89
90
91#define CC_CC 0
92#define CC_CS 1
93#define CC_NE 2
94#define CC_EQ 3
95#define CC_VC 4
96#define CC_VS 5
97#define CC_PL 6
98#define CC_MI 7
99#define CC_LS 8
100#define CC_HI 9
101#define CC_GE 10
102#define CC_LT 11
103#define CC_GT 12
104#define CC_LE 13
105#define CC_A 14
106#define CC_P 15
107
108#define NB_MMU_MODES 2
109
110typedef struct {
111 uint32_t hi;
112 uint32_t lo;
113} TLBSet;
114
115typedef struct CPUCRISState {
116 uint32_t regs[16];
117
118 uint32_t pregs[16];
119
120
121 uint32_t pc;
122
123
124 uint32_t ksp;
125
126
127 int dslot;
128 int btaken;
129 uint32_t btarget;
130
131
132 uint32_t cc_op;
133 uint32_t cc_mask;
134 uint32_t cc_dest;
135 uint32_t cc_src;
136 uint32_t cc_result;
137
138 int cc_size;
139
140 int cc_x;
141
142
143 int locked_irq;
144 int interrupt_vector;
145 int fault_vector;
146 int trap_vector;
147
148
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152
153
154
155 uint32_t sregs[4][16];
156
157
158
159
160 uint32_t mmu_rand_lfsr;
161
162
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166
167
168 TLBSet tlbsets[2][4][16];
169
170
171 struct {} end_reset_fields;
172
173 CPU_COMMON
174
175
176 void *load_info;
177} CPUCRISState;
178
179
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181
182
183
184
185struct CRISCPU {
186
187 CPUState parent_obj;
188
189
190 CPUCRISState env;
191};
192
193static inline CRISCPU *cris_env_get_cpu(CPUCRISState *env)
194{
195 return container_of(env, CRISCPU, env);
196}
197
198#define ENV_GET_CPU(e) CPU(cris_env_get_cpu(e))
199
200#define ENV_OFFSET offsetof(CRISCPU, env)
201
202#ifndef CONFIG_USER_ONLY
203extern const struct VMStateDescription vmstate_cris_cpu;
204#endif
205
206void cris_cpu_do_interrupt(CPUState *cpu);
207void crisv10_cpu_do_interrupt(CPUState *cpu);
208bool cris_cpu_exec_interrupt(CPUState *cpu, int int_req);
209
210void cris_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
211 int flags);
212
213hwaddr cris_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
214
215int crisv10_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
216int cris_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
217int cris_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
218
219CRISCPU *cpu_cris_init(const char *cpu_model);
220
221
222
223int cpu_cris_signal_handler(int host_signum, void *pinfo,
224 void *puc);
225
226void cris_initialize_tcg(void);
227void cris_initialize_crisv10_tcg(void);
228
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234
235
236enum {
237 CC_OP_DYNAMIC,
238 CC_OP_FLAGS,
239 CC_OP_CMP,
240 CC_OP_MOVE,
241 CC_OP_ADD,
242 CC_OP_ADDC,
243 CC_OP_MCP,
244 CC_OP_ADDU,
245 CC_OP_SUB,
246 CC_OP_SUBU,
247 CC_OP_NEG,
248 CC_OP_BTST,
249 CC_OP_MULS,
250 CC_OP_MULU,
251 CC_OP_DSTEP,
252 CC_OP_MSTEP,
253 CC_OP_BOUND,
254
255 CC_OP_OR,
256 CC_OP_AND,
257 CC_OP_XOR,
258 CC_OP_LSL,
259 CC_OP_LSR,
260 CC_OP_ASR,
261 CC_OP_LZ
262};
263
264
265#define TARGET_PAGE_BITS 13
266#define MMAP_SHIFT TARGET_PAGE_BITS
267
268#define TARGET_PHYS_ADDR_SPACE_BITS 32
269#define TARGET_VIRT_ADDR_SPACE_BITS 32
270
271#define cpu_init(cpu_model) CPU(cpu_cris_init(cpu_model))
272
273#define cpu_signal_handler cpu_cris_signal_handler
274
275
276#define MMU_MODE0_SUFFIX _kernel
277#define MMU_MODE1_SUFFIX _user
278#define MMU_USER_IDX 1
279static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch)
280{
281 return !!(env->pregs[PR_CCS] & U_FLAG);
282}
283
284int cris_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
285 int mmu_idx);
286
287
288#define SFR_RW_GC_CFG 0][0
289#define SFR_RW_MM_CFG env->pregs[PR_SRS]][0
290#define SFR_RW_MM_KBASE_LO env->pregs[PR_SRS]][1
291#define SFR_RW_MM_KBASE_HI env->pregs[PR_SRS]][2
292#define SFR_R_MM_CAUSE env->pregs[PR_SRS]][3
293#define SFR_RW_MM_TLB_SEL env->pregs[PR_SRS]][4
294#define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5
295#define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6
296
297#include "exec/cpu-all.h"
298
299static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *pc,
300 target_ulong *cs_base, uint32_t *flags)
301{
302 *pc = env->pc;
303 *cs_base = 0;
304 *flags = env->dslot |
305 (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG
306 | X_FLAG | PFIX_FLAG));
307}
308
309#define cpu_list cris_cpu_list
310void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf);
311
312#endif
313