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20#ifndef I386_CPU_H
21#define I386_CPU_H
22
23#include "qemu-common.h"
24#include "cpu-qom.h"
25#include "standard-headers/asm-x86/hyperv.h"
26
27#ifdef TARGET_X86_64
28#define TARGET_LONG_BITS 64
29#else
30#define TARGET_LONG_BITS 32
31#endif
32
33
34#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
35
36
37#define TARGET_MAX_INSN_SIZE 16
38
39
40
41#define TARGET_HAS_PRECISE_SMC
42
43#ifdef TARGET_X86_64
44#define I386_ELF_MACHINE EM_X86_64
45#define ELF_MACHINE_UNAME "x86_64"
46#else
47#define I386_ELF_MACHINE EM_386
48#define ELF_MACHINE_UNAME "i686"
49#endif
50
51#define CPUArchState struct CPUX86State
52
53#include "exec/cpu-defs.h"
54
55#ifdef CONFIG_TCG
56#include "fpu/softfloat.h"
57#endif
58
59#define R_EAX 0
60#define R_ECX 1
61#define R_EDX 2
62#define R_EBX 3
63#define R_ESP 4
64#define R_EBP 5
65#define R_ESI 6
66#define R_EDI 7
67
68#define R_AL 0
69#define R_CL 1
70#define R_DL 2
71#define R_BL 3
72#define R_AH 4
73#define R_CH 5
74#define R_DH 6
75#define R_BH 7
76
77#define R_ES 0
78#define R_CS 1
79#define R_SS 2
80#define R_DS 3
81#define R_FS 4
82#define R_GS 5
83
84
85#define DESC_G_MASK (1 << 23)
86#define DESC_B_SHIFT 22
87#define DESC_B_MASK (1 << DESC_B_SHIFT)
88#define DESC_L_SHIFT 21
89#define DESC_L_MASK (1 << DESC_L_SHIFT)
90#define DESC_AVL_MASK (1 << 20)
91#define DESC_P_MASK (1 << 15)
92#define DESC_DPL_SHIFT 13
93#define DESC_DPL_MASK (3 << DESC_DPL_SHIFT)
94#define DESC_S_MASK (1 << 12)
95#define DESC_TYPE_SHIFT 8
96#define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT)
97#define DESC_A_MASK (1 << 8)
98
99#define DESC_CS_MASK (1 << 11)
100#define DESC_C_MASK (1 << 10)
101#define DESC_R_MASK (1 << 9)
102
103#define DESC_E_MASK (1 << 10)
104#define DESC_W_MASK (1 << 9)
105
106#define DESC_TSS_BUSY_MASK (1 << 9)
107
108
109#define CC_C 0x0001
110#define CC_P 0x0004
111#define CC_A 0x0010
112#define CC_Z 0x0040
113#define CC_S 0x0080
114#define CC_O 0x0800
115
116#define TF_SHIFT 8
117#define IOPL_SHIFT 12
118#define VM_SHIFT 17
119
120#define TF_MASK 0x00000100
121#define IF_MASK 0x00000200
122#define DF_MASK 0x00000400
123#define IOPL_MASK 0x00003000
124#define NT_MASK 0x00004000
125#define RF_MASK 0x00010000
126#define VM_MASK 0x00020000
127#define AC_MASK 0x00040000
128#define VIF_MASK 0x00080000
129#define VIP_MASK 0x00100000
130#define ID_MASK 0x00200000
131
132
133
134
135
136
137#define HF_CPL_SHIFT 0
138
139#define HF_INHIBIT_IRQ_SHIFT 3
140
141#define HF_CS32_SHIFT 4
142#define HF_SS32_SHIFT 5
143
144#define HF_ADDSEG_SHIFT 6
145
146#define HF_PE_SHIFT 7
147#define HF_TF_SHIFT 8
148#define HF_MP_SHIFT 9
149#define HF_EM_SHIFT 10
150#define HF_TS_SHIFT 11
151#define HF_IOPL_SHIFT 12
152#define HF_LMA_SHIFT 14
153#define HF_CS64_SHIFT 15
154#define HF_RF_SHIFT 16
155#define HF_VM_SHIFT 17
156#define HF_AC_SHIFT 18
157#define HF_SMM_SHIFT 19
158#define HF_SVME_SHIFT 20
159#define HF_SVMI_SHIFT 21
160#define HF_OSFXSR_SHIFT 22
161#define HF_SMAP_SHIFT 23
162#define HF_IOBPT_SHIFT 24
163#define HF_MPX_EN_SHIFT 25
164#define HF_MPX_IU_SHIFT 26
165
166#define HF_CPL_MASK (3 << HF_CPL_SHIFT)
167#define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
168#define HF_CS32_MASK (1 << HF_CS32_SHIFT)
169#define HF_SS32_MASK (1 << HF_SS32_SHIFT)
170#define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
171#define HF_PE_MASK (1 << HF_PE_SHIFT)
172#define HF_TF_MASK (1 << HF_TF_SHIFT)
173#define HF_MP_MASK (1 << HF_MP_SHIFT)
174#define HF_EM_MASK (1 << HF_EM_SHIFT)
175#define HF_TS_MASK (1 << HF_TS_SHIFT)
176#define HF_IOPL_MASK (3 << HF_IOPL_SHIFT)
177#define HF_LMA_MASK (1 << HF_LMA_SHIFT)
178#define HF_CS64_MASK (1 << HF_CS64_SHIFT)
179#define HF_RF_MASK (1 << HF_RF_SHIFT)
180#define HF_VM_MASK (1 << HF_VM_SHIFT)
181#define HF_AC_MASK (1 << HF_AC_SHIFT)
182#define HF_SMM_MASK (1 << HF_SMM_SHIFT)
183#define HF_SVME_MASK (1 << HF_SVME_SHIFT)
184#define HF_SVMI_MASK (1 << HF_SVMI_SHIFT)
185#define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
186#define HF_SMAP_MASK (1 << HF_SMAP_SHIFT)
187#define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT)
188#define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT)
189#define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT)
190
191
192
193#define HF2_GIF_SHIFT 0
194#define HF2_HIF_SHIFT 1
195#define HF2_NMI_SHIFT 2
196#define HF2_VINTR_SHIFT 3
197#define HF2_SMM_INSIDE_NMI_SHIFT 4
198#define HF2_MPX_PR_SHIFT 5
199
200#define HF2_GIF_MASK (1 << HF2_GIF_SHIFT)
201#define HF2_HIF_MASK (1 << HF2_HIF_SHIFT)
202#define HF2_NMI_MASK (1 << HF2_NMI_SHIFT)
203#define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT)
204#define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT)
205#define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT)
206
207#define CR0_PE_SHIFT 0
208#define CR0_MP_SHIFT 1
209
210#define CR0_PE_MASK (1U << 0)
211#define CR0_MP_MASK (1U << 1)
212#define CR0_EM_MASK (1U << 2)
213#define CR0_TS_MASK (1U << 3)
214#define CR0_ET_MASK (1U << 4)
215#define CR0_NE_MASK (1U << 5)
216#define CR0_WP_MASK (1U << 16)
217#define CR0_AM_MASK (1U << 18)
218#define CR0_PG_MASK (1U << 31)
219
220#define CR4_VME_MASK (1U << 0)
221#define CR4_PVI_MASK (1U << 1)
222#define CR4_TSD_MASK (1U << 2)
223#define CR4_DE_MASK (1U << 3)
224#define CR4_PSE_MASK (1U << 4)
225#define CR4_PAE_MASK (1U << 5)
226#define CR4_MCE_MASK (1U << 6)
227#define CR4_PGE_MASK (1U << 7)
228#define CR4_PCE_MASK (1U << 8)
229#define CR4_OSFXSR_SHIFT 9
230#define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT)
231#define CR4_OSXMMEXCPT_MASK (1U << 10)
232#define CR4_LA57_MASK (1U << 12)
233#define CR4_VMXE_MASK (1U << 13)
234#define CR4_SMXE_MASK (1U << 14)
235#define CR4_FSGSBASE_MASK (1U << 16)
236#define CR4_PCIDE_MASK (1U << 17)
237#define CR4_OSXSAVE_MASK (1U << 18)
238#define CR4_SMEP_MASK (1U << 20)
239#define CR4_SMAP_MASK (1U << 21)
240#define CR4_PKE_MASK (1U << 22)
241
242#define DR6_BD (1 << 13)
243#define DR6_BS (1 << 14)
244#define DR6_BT (1 << 15)
245#define DR6_FIXED_1 0xffff0ff0
246
247#define DR7_GD (1 << 13)
248#define DR7_TYPE_SHIFT 16
249#define DR7_LEN_SHIFT 18
250#define DR7_FIXED_1 0x00000400
251#define DR7_GLOBAL_BP_MASK 0xaa
252#define DR7_LOCAL_BP_MASK 0x55
253#define DR7_MAX_BP 4
254#define DR7_TYPE_BP_INST 0x0
255#define DR7_TYPE_DATA_WR 0x1
256#define DR7_TYPE_IO_RW 0x2
257#define DR7_TYPE_DATA_RW 0x3
258
259#define PG_PRESENT_BIT 0
260#define PG_RW_BIT 1
261#define PG_USER_BIT 2
262#define PG_PWT_BIT 3
263#define PG_PCD_BIT 4
264#define PG_ACCESSED_BIT 5
265#define PG_DIRTY_BIT 6
266#define PG_PSE_BIT 7
267#define PG_GLOBAL_BIT 8
268#define PG_PSE_PAT_BIT 12
269#define PG_PKRU_BIT 59
270#define PG_NX_BIT 63
271
272#define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
273#define PG_RW_MASK (1 << PG_RW_BIT)
274#define PG_USER_MASK (1 << PG_USER_BIT)
275#define PG_PWT_MASK (1 << PG_PWT_BIT)
276#define PG_PCD_MASK (1 << PG_PCD_BIT)
277#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
278#define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
279#define PG_PSE_MASK (1 << PG_PSE_BIT)
280#define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
281#define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT)
282#define PG_ADDRESS_MASK 0x000ffffffffff000LL
283#define PG_HI_RSVD_MASK (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK)
284#define PG_HI_USER_MASK 0x7ff0000000000000LL
285#define PG_PKRU_MASK (15ULL << PG_PKRU_BIT)
286#define PG_NX_MASK (1ULL << PG_NX_BIT)
287
288#define PG_ERROR_W_BIT 1
289
290#define PG_ERROR_P_MASK 0x01
291#define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
292#define PG_ERROR_U_MASK 0x04
293#define PG_ERROR_RSVD_MASK 0x08
294#define PG_ERROR_I_D_MASK 0x10
295#define PG_ERROR_PK_MASK 0x20
296
297#define MCG_CTL_P (1ULL<<8)
298#define MCG_SER_P (1ULL<<24)
299#define MCG_LMCE_P (1ULL<<27)
300
301#define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P)
302#define MCE_BANKS_DEF 10
303
304#define MCG_CAP_BANKS_MASK 0xff
305
306#define MCG_STATUS_RIPV (1ULL<<0)
307#define MCG_STATUS_EIPV (1ULL<<1)
308#define MCG_STATUS_MCIP (1ULL<<2)
309#define MCG_STATUS_LMCE (1ULL<<3)
310
311#define MCG_EXT_CTL_LMCE_EN (1ULL<<0)
312
313#define MCI_STATUS_VAL (1ULL<<63)
314#define MCI_STATUS_OVER (1ULL<<62)
315#define MCI_STATUS_UC (1ULL<<61)
316#define MCI_STATUS_EN (1ULL<<60)
317#define MCI_STATUS_MISCV (1ULL<<59)
318#define MCI_STATUS_ADDRV (1ULL<<58)
319#define MCI_STATUS_PCC (1ULL<<57)
320#define MCI_STATUS_S (1ULL<<56)
321#define MCI_STATUS_AR (1ULL<<55)
322
323
324#define MCM_ADDR_SEGOFF 0
325#define MCM_ADDR_LINEAR 1
326#define MCM_ADDR_PHYS 2
327#define MCM_ADDR_MEM 3
328#define MCM_ADDR_GENERIC 7
329
330#define MSR_IA32_TSC 0x10
331#define MSR_IA32_APICBASE 0x1b
332#define MSR_IA32_APICBASE_BSP (1<<8)
333#define MSR_IA32_APICBASE_ENABLE (1<<11)
334#define MSR_IA32_APICBASE_EXTD (1 << 10)
335#define MSR_IA32_APICBASE_BASE (0xfffffU<<12)
336#define MSR_IA32_FEATURE_CONTROL 0x0000003a
337#define MSR_TSC_ADJUST 0x0000003b
338#define MSR_IA32_TSCDEADLINE 0x6e0
339
340#define FEATURE_CONTROL_LOCKED (1<<0)
341#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
342#define FEATURE_CONTROL_LMCE (1<<20)
343
344#define MSR_P6_PERFCTR0 0xc1
345
346#define MSR_IA32_SMBASE 0x9e
347#define MSR_MTRRcap 0xfe
348#define MSR_MTRRcap_VCNT 8
349#define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8)
350#define MSR_MTRRcap_WC_SUPPORTED (1 << 10)
351
352#define MSR_IA32_SYSENTER_CS 0x174
353#define MSR_IA32_SYSENTER_ESP 0x175
354#define MSR_IA32_SYSENTER_EIP 0x176
355
356#define MSR_MCG_CAP 0x179
357#define MSR_MCG_STATUS 0x17a
358#define MSR_MCG_CTL 0x17b
359#define MSR_MCG_EXT_CTL 0x4d0
360
361#define MSR_P6_EVNTSEL0 0x186
362
363#define MSR_IA32_PERF_STATUS 0x198
364
365#define MSR_IA32_MISC_ENABLE 0x1a0
366
367#define MSR_IA32_MISC_ENABLE_DEFAULT 1
368
369#define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
370#define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
371
372#define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2)
373
374#define MSR_MTRRfix64K_00000 0x250
375#define MSR_MTRRfix16K_80000 0x258
376#define MSR_MTRRfix16K_A0000 0x259
377#define MSR_MTRRfix4K_C0000 0x268
378#define MSR_MTRRfix4K_C8000 0x269
379#define MSR_MTRRfix4K_D0000 0x26a
380#define MSR_MTRRfix4K_D8000 0x26b
381#define MSR_MTRRfix4K_E0000 0x26c
382#define MSR_MTRRfix4K_E8000 0x26d
383#define MSR_MTRRfix4K_F0000 0x26e
384#define MSR_MTRRfix4K_F8000 0x26f
385
386#define MSR_PAT 0x277
387
388#define MSR_MTRRdefType 0x2ff
389
390#define MSR_CORE_PERF_FIXED_CTR0 0x309
391#define MSR_CORE_PERF_FIXED_CTR1 0x30a
392#define MSR_CORE_PERF_FIXED_CTR2 0x30b
393#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d
394#define MSR_CORE_PERF_GLOBAL_STATUS 0x38e
395#define MSR_CORE_PERF_GLOBAL_CTRL 0x38f
396#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390
397
398#define MSR_MC0_CTL 0x400
399#define MSR_MC0_STATUS 0x401
400#define MSR_MC0_ADDR 0x402
401#define MSR_MC0_MISC 0x403
402
403#define MSR_EFER 0xc0000080
404
405#define MSR_EFER_SCE (1 << 0)
406#define MSR_EFER_LME (1 << 8)
407#define MSR_EFER_LMA (1 << 10)
408#define MSR_EFER_NXE (1 << 11)
409#define MSR_EFER_SVME (1 << 12)
410#define MSR_EFER_FFXSR (1 << 14)
411
412#define MSR_STAR 0xc0000081
413#define MSR_LSTAR 0xc0000082
414#define MSR_CSTAR 0xc0000083
415#define MSR_FMASK 0xc0000084
416#define MSR_FSBASE 0xc0000100
417#define MSR_GSBASE 0xc0000101
418#define MSR_KERNELGSBASE 0xc0000102
419#define MSR_TSC_AUX 0xc0000103
420
421#define MSR_VM_HSAVE_PA 0xc0010117
422
423#define MSR_IA32_BNDCFGS 0x00000d90
424#define MSR_IA32_XSS 0x00000da0
425
426#define XSTATE_FP_BIT 0
427#define XSTATE_SSE_BIT 1
428#define XSTATE_YMM_BIT 2
429#define XSTATE_BNDREGS_BIT 3
430#define XSTATE_BNDCSR_BIT 4
431#define XSTATE_OPMASK_BIT 5
432#define XSTATE_ZMM_Hi256_BIT 6
433#define XSTATE_Hi16_ZMM_BIT 7
434#define XSTATE_PKRU_BIT 9
435
436#define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT)
437#define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT)
438#define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT)
439#define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT)
440#define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT)
441#define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT)
442#define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT)
443#define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT)
444#define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT)
445
446
447typedef enum FeatureWord {
448 FEAT_1_EDX,
449 FEAT_1_ECX,
450 FEAT_7_0_EBX,
451 FEAT_7_0_ECX,
452 FEAT_7_0_EDX,
453 FEAT_8000_0001_EDX,
454 FEAT_8000_0001_ECX,
455 FEAT_8000_0007_EDX,
456 FEAT_C000_0001_EDX,
457 FEAT_KVM,
458 FEAT_HYPERV_EAX,
459 FEAT_HYPERV_EBX,
460 FEAT_HYPERV_EDX,
461 FEAT_SVM,
462 FEAT_XSAVE,
463 FEAT_6_EAX,
464 FEAT_XSAVE_COMP_LO,
465 FEAT_XSAVE_COMP_HI,
466 FEATURE_WORDS,
467} FeatureWord;
468
469typedef uint32_t FeatureWordArray[FEATURE_WORDS];
470
471
472#define CPUID_FP87 (1U << 0)
473#define CPUID_VME (1U << 1)
474#define CPUID_DE (1U << 2)
475#define CPUID_PSE (1U << 3)
476#define CPUID_TSC (1U << 4)
477#define CPUID_MSR (1U << 5)
478#define CPUID_PAE (1U << 6)
479#define CPUID_MCE (1U << 7)
480#define CPUID_CX8 (1U << 8)
481#define CPUID_APIC (1U << 9)
482#define CPUID_SEP (1U << 11)
483#define CPUID_MTRR (1U << 12)
484#define CPUID_PGE (1U << 13)
485#define CPUID_MCA (1U << 14)
486#define CPUID_CMOV (1U << 15)
487#define CPUID_PAT (1U << 16)
488#define CPUID_PSE36 (1U << 17)
489#define CPUID_PN (1U << 18)
490#define CPUID_CLFLUSH (1U << 19)
491#define CPUID_DTS (1U << 21)
492#define CPUID_ACPI (1U << 22)
493#define CPUID_MMX (1U << 23)
494#define CPUID_FXSR (1U << 24)
495#define CPUID_SSE (1U << 25)
496#define CPUID_SSE2 (1U << 26)
497#define CPUID_SS (1U << 27)
498#define CPUID_HT (1U << 28)
499#define CPUID_TM (1U << 29)
500#define CPUID_IA64 (1U << 30)
501#define CPUID_PBE (1U << 31)
502
503#define CPUID_EXT_SSE3 (1U << 0)
504#define CPUID_EXT_PCLMULQDQ (1U << 1)
505#define CPUID_EXT_DTES64 (1U << 2)
506#define CPUID_EXT_MONITOR (1U << 3)
507#define CPUID_EXT_DSCPL (1U << 4)
508#define CPUID_EXT_VMX (1U << 5)
509#define CPUID_EXT_SMX (1U << 6)
510#define CPUID_EXT_EST (1U << 7)
511#define CPUID_EXT_TM2 (1U << 8)
512#define CPUID_EXT_SSSE3 (1U << 9)
513#define CPUID_EXT_CID (1U << 10)
514#define CPUID_EXT_FMA (1U << 12)
515#define CPUID_EXT_CX16 (1U << 13)
516#define CPUID_EXT_XTPR (1U << 14)
517#define CPUID_EXT_PDCM (1U << 15)
518#define CPUID_EXT_PCID (1U << 17)
519#define CPUID_EXT_DCA (1U << 18)
520#define CPUID_EXT_SSE41 (1U << 19)
521#define CPUID_EXT_SSE42 (1U << 20)
522#define CPUID_EXT_X2APIC (1U << 21)
523#define CPUID_EXT_MOVBE (1U << 22)
524#define CPUID_EXT_POPCNT (1U << 23)
525#define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24)
526#define CPUID_EXT_AES (1U << 25)
527#define CPUID_EXT_XSAVE (1U << 26)
528#define CPUID_EXT_OSXSAVE (1U << 27)
529#define CPUID_EXT_AVX (1U << 28)
530#define CPUID_EXT_F16C (1U << 29)
531#define CPUID_EXT_RDRAND (1U << 30)
532#define CPUID_EXT_HYPERVISOR (1U << 31)
533
534#define CPUID_EXT2_FPU (1U << 0)
535#define CPUID_EXT2_VME (1U << 1)
536#define CPUID_EXT2_DE (1U << 2)
537#define CPUID_EXT2_PSE (1U << 3)
538#define CPUID_EXT2_TSC (1U << 4)
539#define CPUID_EXT2_MSR (1U << 5)
540#define CPUID_EXT2_PAE (1U << 6)
541#define CPUID_EXT2_MCE (1U << 7)
542#define CPUID_EXT2_CX8 (1U << 8)
543#define CPUID_EXT2_APIC (1U << 9)
544#define CPUID_EXT2_SYSCALL (1U << 11)
545#define CPUID_EXT2_MTRR (1U << 12)
546#define CPUID_EXT2_PGE (1U << 13)
547#define CPUID_EXT2_MCA (1U << 14)
548#define CPUID_EXT2_CMOV (1U << 15)
549#define CPUID_EXT2_PAT (1U << 16)
550#define CPUID_EXT2_PSE36 (1U << 17)
551#define CPUID_EXT2_MP (1U << 19)
552#define CPUID_EXT2_NX (1U << 20)
553#define CPUID_EXT2_MMXEXT (1U << 22)
554#define CPUID_EXT2_MMX (1U << 23)
555#define CPUID_EXT2_FXSR (1U << 24)
556#define CPUID_EXT2_FFXSR (1U << 25)
557#define CPUID_EXT2_PDPE1GB (1U << 26)
558#define CPUID_EXT2_RDTSCP (1U << 27)
559#define CPUID_EXT2_LM (1U << 29)
560#define CPUID_EXT2_3DNOWEXT (1U << 30)
561#define CPUID_EXT2_3DNOW (1U << 31)
562
563
564#define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
565 CPUID_EXT2_DE | CPUID_EXT2_PSE | \
566 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \
567 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \
568 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \
569 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \
570 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \
571 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \
572 CPUID_EXT2_MMX | CPUID_EXT2_FXSR)
573
574#define CPUID_EXT3_LAHF_LM (1U << 0)
575#define CPUID_EXT3_CMP_LEG (1U << 1)
576#define CPUID_EXT3_SVM (1U << 2)
577#define CPUID_EXT3_EXTAPIC (1U << 3)
578#define CPUID_EXT3_CR8LEG (1U << 4)
579#define CPUID_EXT3_ABM (1U << 5)
580#define CPUID_EXT3_SSE4A (1U << 6)
581#define CPUID_EXT3_MISALIGNSSE (1U << 7)
582#define CPUID_EXT3_3DNOWPREFETCH (1U << 8)
583#define CPUID_EXT3_OSVW (1U << 9)
584#define CPUID_EXT3_IBS (1U << 10)
585#define CPUID_EXT3_XOP (1U << 11)
586#define CPUID_EXT3_SKINIT (1U << 12)
587#define CPUID_EXT3_WDT (1U << 13)
588#define CPUID_EXT3_LWP (1U << 15)
589#define CPUID_EXT3_FMA4 (1U << 16)
590#define CPUID_EXT3_TCE (1U << 17)
591#define CPUID_EXT3_NODEID (1U << 19)
592#define CPUID_EXT3_TBM (1U << 21)
593#define CPUID_EXT3_TOPOEXT (1U << 22)
594#define CPUID_EXT3_PERFCORE (1U << 23)
595#define CPUID_EXT3_PERFNB (1U << 24)
596
597#define CPUID_SVM_NPT (1U << 0)
598#define CPUID_SVM_LBRV (1U << 1)
599#define CPUID_SVM_SVMLOCK (1U << 2)
600#define CPUID_SVM_NRIPSAVE (1U << 3)
601#define CPUID_SVM_TSCSCALE (1U << 4)
602#define CPUID_SVM_VMCBCLEAN (1U << 5)
603#define CPUID_SVM_FLUSHASID (1U << 6)
604#define CPUID_SVM_DECODEASSIST (1U << 7)
605#define CPUID_SVM_PAUSEFILTER (1U << 10)
606#define CPUID_SVM_PFTHRESHOLD (1U << 12)
607
608#define CPUID_7_0_EBX_FSGSBASE (1U << 0)
609#define CPUID_7_0_EBX_BMI1 (1U << 3)
610#define CPUID_7_0_EBX_HLE (1U << 4)
611#define CPUID_7_0_EBX_AVX2 (1U << 5)
612#define CPUID_7_0_EBX_SMEP (1U << 7)
613#define CPUID_7_0_EBX_BMI2 (1U << 8)
614#define CPUID_7_0_EBX_ERMS (1U << 9)
615#define CPUID_7_0_EBX_INVPCID (1U << 10)
616#define CPUID_7_0_EBX_RTM (1U << 11)
617#define CPUID_7_0_EBX_MPX (1U << 14)
618#define CPUID_7_0_EBX_AVX512F (1U << 16)
619#define CPUID_7_0_EBX_AVX512DQ (1U << 17)
620#define CPUID_7_0_EBX_RDSEED (1U << 18)
621#define CPUID_7_0_EBX_ADX (1U << 19)
622#define CPUID_7_0_EBX_SMAP (1U << 20)
623#define CPUID_7_0_EBX_AVX512IFMA (1U << 21)
624#define CPUID_7_0_EBX_PCOMMIT (1U << 22)
625#define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23)
626#define CPUID_7_0_EBX_CLWB (1U << 24)
627#define CPUID_7_0_EBX_AVX512PF (1U << 26)
628#define CPUID_7_0_EBX_AVX512ER (1U << 27)
629#define CPUID_7_0_EBX_AVX512CD (1U << 28)
630#define CPUID_7_0_EBX_SHA_NI (1U << 29)
631#define CPUID_7_0_EBX_AVX512BW (1U << 30)
632#define CPUID_7_0_EBX_AVX512VL (1U << 31)
633
634#define CPUID_7_0_ECX_VBMI (1U << 1)
635#define CPUID_7_0_ECX_UMIP (1U << 2)
636#define CPUID_7_0_ECX_PKU (1U << 3)
637#define CPUID_7_0_ECX_OSPKE (1U << 4)
638#define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14)
639#define CPUID_7_0_ECX_LA57 (1U << 16)
640#define CPUID_7_0_ECX_RDPID (1U << 22)
641
642#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2)
643#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3)
644
645#define CPUID_XSAVE_XSAVEOPT (1U << 0)
646#define CPUID_XSAVE_XSAVEC (1U << 1)
647#define CPUID_XSAVE_XGETBV1 (1U << 2)
648#define CPUID_XSAVE_XSAVES (1U << 3)
649
650#define CPUID_6_EAX_ARAT (1U << 2)
651
652
653#define CPUID_APM_INVTSC (1U << 8)
654
655#define CPUID_VENDOR_SZ 12
656
657#define CPUID_VENDOR_INTEL_1 0x756e6547
658#define CPUID_VENDOR_INTEL_2 0x49656e69
659#define CPUID_VENDOR_INTEL_3 0x6c65746e
660#define CPUID_VENDOR_INTEL "GenuineIntel"
661
662#define CPUID_VENDOR_AMD_1 0x68747541
663#define CPUID_VENDOR_AMD_2 0x69746e65
664#define CPUID_VENDOR_AMD_3 0x444d4163
665#define CPUID_VENDOR_AMD "AuthenticAMD"
666
667#define CPUID_VENDOR_VIA "CentaurHauls"
668
669#define CPUID_MWAIT_IBE (1U << 1)
670#define CPUID_MWAIT_EMX (1U << 0)
671
672
673#define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8)
674#define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8)
675#define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8)
676
677#ifndef HYPERV_SPINLOCK_NEVER_RETRY
678#define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF
679#endif
680
681#define EXCP00_DIVZ 0
682#define EXCP01_DB 1
683#define EXCP02_NMI 2
684#define EXCP03_INT3 3
685#define EXCP04_INTO 4
686#define EXCP05_BOUND 5
687#define EXCP06_ILLOP 6
688#define EXCP07_PREX 7
689#define EXCP08_DBLE 8
690#define EXCP09_XERR 9
691#define EXCP0A_TSS 10
692#define EXCP0B_NOSEG 11
693#define EXCP0C_STACK 12
694#define EXCP0D_GPF 13
695#define EXCP0E_PAGE 14
696#define EXCP10_COPR 16
697#define EXCP11_ALGN 17
698#define EXCP12_MCHK 18
699
700#define EXCP_SYSCALL 0x100
701
702#define EXCP_VMEXIT 0x100
703
704
705#define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1
706#define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2
707#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
708#define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4
709#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0
710#define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1
711#define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2
712
713
714#define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET
715
716
717
718
719
720
721
722
723typedef enum {
724 CC_OP_DYNAMIC,
725 CC_OP_EFLAGS,
726
727 CC_OP_MULB,
728 CC_OP_MULW,
729 CC_OP_MULL,
730 CC_OP_MULQ,
731
732 CC_OP_ADDB,
733 CC_OP_ADDW,
734 CC_OP_ADDL,
735 CC_OP_ADDQ,
736
737 CC_OP_ADCB,
738 CC_OP_ADCW,
739 CC_OP_ADCL,
740 CC_OP_ADCQ,
741
742 CC_OP_SUBB,
743 CC_OP_SUBW,
744 CC_OP_SUBL,
745 CC_OP_SUBQ,
746
747 CC_OP_SBBB,
748 CC_OP_SBBW,
749 CC_OP_SBBL,
750 CC_OP_SBBQ,
751
752 CC_OP_LOGICB,
753 CC_OP_LOGICW,
754 CC_OP_LOGICL,
755 CC_OP_LOGICQ,
756
757 CC_OP_INCB,
758 CC_OP_INCW,
759 CC_OP_INCL,
760 CC_OP_INCQ,
761
762 CC_OP_DECB,
763 CC_OP_DECW,
764 CC_OP_DECL,
765 CC_OP_DECQ,
766
767 CC_OP_SHLB,
768 CC_OP_SHLW,
769 CC_OP_SHLL,
770 CC_OP_SHLQ,
771
772 CC_OP_SARB,
773 CC_OP_SARW,
774 CC_OP_SARL,
775 CC_OP_SARQ,
776
777 CC_OP_BMILGB,
778 CC_OP_BMILGW,
779 CC_OP_BMILGL,
780 CC_OP_BMILGQ,
781
782 CC_OP_ADCX,
783 CC_OP_ADOX,
784 CC_OP_ADCOX,
785
786 CC_OP_CLR,
787 CC_OP_POPCNT,
788
789 CC_OP_NB,
790} CCOp;
791
792typedef struct SegmentCache {
793 uint32_t selector;
794 target_ulong base;
795 uint32_t limit;
796 uint32_t flags;
797} SegmentCache;
798
799#define MMREG_UNION(n, bits) \
800 union n { \
801 uint8_t _b_##n[(bits)/8]; \
802 uint16_t _w_##n[(bits)/16]; \
803 uint32_t _l_##n[(bits)/32]; \
804 uint64_t _q_##n[(bits)/64]; \
805 float32 _s_##n[(bits)/32]; \
806 float64 _d_##n[(bits)/64]; \
807 }
808
809typedef MMREG_UNION(ZMMReg, 512) ZMMReg;
810typedef MMREG_UNION(MMXReg, 64) MMXReg;
811
812typedef struct BNDReg {
813 uint64_t lb;
814 uint64_t ub;
815} BNDReg;
816
817typedef struct BNDCSReg {
818 uint64_t cfgu;
819 uint64_t sts;
820} BNDCSReg;
821
822#define BNDCFG_ENABLE 1ULL
823#define BNDCFG_BNDPRESERVE 2ULL
824#define BNDCFG_BDIR_MASK TARGET_PAGE_MASK
825
826#ifdef HOST_WORDS_BIGENDIAN
827#define ZMM_B(n) _b_ZMMReg[63 - (n)]
828#define ZMM_W(n) _w_ZMMReg[31 - (n)]
829#define ZMM_L(n) _l_ZMMReg[15 - (n)]
830#define ZMM_S(n) _s_ZMMReg[15 - (n)]
831#define ZMM_Q(n) _q_ZMMReg[7 - (n)]
832#define ZMM_D(n) _d_ZMMReg[7 - (n)]
833
834#define MMX_B(n) _b_MMXReg[7 - (n)]
835#define MMX_W(n) _w_MMXReg[3 - (n)]
836#define MMX_L(n) _l_MMXReg[1 - (n)]
837#define MMX_S(n) _s_MMXReg[1 - (n)]
838#else
839#define ZMM_B(n) _b_ZMMReg[n]
840#define ZMM_W(n) _w_ZMMReg[n]
841#define ZMM_L(n) _l_ZMMReg[n]
842#define ZMM_S(n) _s_ZMMReg[n]
843#define ZMM_Q(n) _q_ZMMReg[n]
844#define ZMM_D(n) _d_ZMMReg[n]
845
846#define MMX_B(n) _b_MMXReg[n]
847#define MMX_W(n) _w_MMXReg[n]
848#define MMX_L(n) _l_MMXReg[n]
849#define MMX_S(n) _s_MMXReg[n]
850#endif
851#define MMX_Q(n) _q_MMXReg[n]
852
853typedef union {
854 floatx80 d __attribute__((aligned(16)));
855 MMXReg mmx;
856} FPReg;
857
858typedef struct {
859 uint64_t base;
860 uint64_t mask;
861} MTRRVar;
862
863#define CPU_NB_REGS64 16
864#define CPU_NB_REGS32 8
865
866#ifdef TARGET_X86_64
867#define CPU_NB_REGS CPU_NB_REGS64
868#else
869#define CPU_NB_REGS CPU_NB_REGS32
870#endif
871
872#define MAX_FIXED_COUNTERS 3
873#define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)
874
875#define NB_MMU_MODES 3
876#define TARGET_INSN_START_EXTRA_WORDS 1
877
878#define NB_OPMASK_REGS 8
879
880
881
882
883#define UNASSIGNED_APIC_ID 0xFFFFFFFF
884
885typedef union X86LegacyXSaveArea {
886 struct {
887 uint16_t fcw;
888 uint16_t fsw;
889 uint8_t ftw;
890 uint8_t reserved;
891 uint16_t fpop;
892 uint64_t fpip;
893 uint64_t fpdp;
894 uint32_t mxcsr;
895 uint32_t mxcsr_mask;
896 FPReg fpregs[8];
897 uint8_t xmm_regs[16][16];
898 };
899 uint8_t data[512];
900} X86LegacyXSaveArea;
901
902typedef struct X86XSaveHeader {
903 uint64_t xstate_bv;
904 uint64_t xcomp_bv;
905 uint64_t reserve0;
906 uint8_t reserved[40];
907} X86XSaveHeader;
908
909
910typedef struct XSaveAVX {
911 uint8_t ymmh[16][16];
912} XSaveAVX;
913
914
915typedef struct XSaveBNDREG {
916 BNDReg bnd_regs[4];
917} XSaveBNDREG;
918
919
920typedef union XSaveBNDCSR {
921 BNDCSReg bndcsr;
922 uint8_t data[64];
923} XSaveBNDCSR;
924
925
926typedef struct XSaveOpmask {
927 uint64_t opmask_regs[NB_OPMASK_REGS];
928} XSaveOpmask;
929
930
931typedef struct XSaveZMM_Hi256 {
932 uint8_t zmm_hi256[16][32];
933} XSaveZMM_Hi256;
934
935
936typedef struct XSaveHi16_ZMM {
937 uint8_t hi16_zmm[16][64];
938} XSaveHi16_ZMM;
939
940
941typedef struct XSavePKRU {
942 uint32_t pkru;
943 uint32_t padding;
944} XSavePKRU;
945
946typedef struct X86XSaveArea {
947 X86LegacyXSaveArea legacy;
948 X86XSaveHeader header;
949
950
951
952
953 XSaveAVX avx_state;
954 uint8_t padding[960 - 576 - sizeof(XSaveAVX)];
955
956 XSaveBNDREG bndreg_state;
957 XSaveBNDCSR bndcsr_state;
958
959 XSaveOpmask opmask_state;
960 XSaveZMM_Hi256 zmm_hi256_state;
961 XSaveHi16_ZMM hi16_zmm_state;
962
963 XSavePKRU pkru_state;
964} X86XSaveArea;
965
966QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != 0x240);
967QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100);
968QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != 0x3c0);
969QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40);
970QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != 0x400);
971QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40);
972QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != 0x440);
973QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40);
974QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != 0x480);
975QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200);
976QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != 0x680);
977QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400);
978QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != 0xA80);
979QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8);
980
981typedef enum TPRAccess {
982 TPR_ACCESS_READ,
983 TPR_ACCESS_WRITE,
984} TPRAccess;
985
986typedef struct CPUX86State {
987
988 target_ulong regs[CPU_NB_REGS];
989 target_ulong eip;
990 target_ulong eflags;
991
992
993
994
995 target_ulong cc_dst;
996 target_ulong cc_src;
997 target_ulong cc_src2;
998 uint32_t cc_op;
999 int32_t df;
1000 uint32_t hflags;
1001
1002 uint32_t hflags2;
1003
1004
1005 SegmentCache segs[6];
1006 SegmentCache ldt;
1007 SegmentCache tr;
1008 SegmentCache gdt;
1009 SegmentCache idt;
1010
1011 target_ulong cr[5];
1012 int32_t a20_mask;
1013
1014 BNDReg bnd_regs[4];
1015 BNDCSReg bndcs_regs;
1016 uint64_t msr_bndcfgs;
1017 uint64_t efer;
1018
1019
1020 struct {} start_init_save;
1021
1022
1023 unsigned int fpstt;
1024 uint16_t fpus;
1025 uint16_t fpuc;
1026 uint8_t fptags[8];
1027 FPReg fpregs[8];
1028
1029 uint16_t fpop;
1030 uint64_t fpip;
1031 uint64_t fpdp;
1032
1033
1034 float_status fp_status;
1035 floatx80 ft0;
1036
1037 float_status mmx_status;
1038 float_status sse_status;
1039 uint32_t mxcsr;
1040 ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32];
1041 ZMMReg xmm_t0;
1042 MMXReg mmx_t0;
1043
1044 uint64_t opmask_regs[NB_OPMASK_REGS];
1045
1046
1047 uint32_t sysenter_cs;
1048 target_ulong sysenter_esp;
1049 target_ulong sysenter_eip;
1050 uint64_t star;
1051
1052 uint64_t vm_hsave;
1053
1054#ifdef TARGET_X86_64
1055 target_ulong lstar;
1056 target_ulong cstar;
1057 target_ulong fmask;
1058 target_ulong kernelgsbase;
1059#endif
1060
1061 uint64_t tsc;
1062 uint64_t tsc_adjust;
1063 uint64_t tsc_deadline;
1064 uint64_t tsc_aux;
1065
1066 uint64_t xcr0;
1067
1068 uint64_t mcg_status;
1069 uint64_t msr_ia32_misc_enable;
1070 uint64_t msr_ia32_feature_control;
1071
1072 uint64_t msr_fixed_ctr_ctrl;
1073 uint64_t msr_global_ctrl;
1074 uint64_t msr_global_status;
1075 uint64_t msr_global_ovf_ctrl;
1076 uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS];
1077 uint64_t msr_gp_counters[MAX_GP_COUNTERS];
1078 uint64_t msr_gp_evtsel[MAX_GP_COUNTERS];
1079
1080 uint64_t pat;
1081 uint32_t smbase;
1082
1083 uint32_t pkru;
1084
1085
1086 struct {} end_init_save;
1087
1088 uint64_t system_time_msr;
1089 uint64_t wall_clock_msr;
1090 uint64_t steal_time_msr;
1091 uint64_t async_pf_en_msr;
1092 uint64_t pv_eoi_en_msr;
1093
1094 uint64_t msr_hv_hypercall;
1095 uint64_t msr_hv_guest_os_id;
1096 uint64_t msr_hv_vapic;
1097 uint64_t msr_hv_tsc;
1098 uint64_t msr_hv_crash_params[HV_X64_MSR_CRASH_PARAMS];
1099 uint64_t msr_hv_runtime;
1100 uint64_t msr_hv_synic_control;
1101 uint64_t msr_hv_synic_version;
1102 uint64_t msr_hv_synic_evt_page;
1103 uint64_t msr_hv_synic_msg_page;
1104 uint64_t msr_hv_synic_sint[HV_SYNIC_SINT_COUNT];
1105 uint64_t msr_hv_stimer_config[HV_SYNIC_STIMER_COUNT];
1106 uint64_t msr_hv_stimer_count[HV_SYNIC_STIMER_COUNT];
1107
1108
1109 int error_code;
1110 int exception_is_int;
1111 target_ulong exception_next_eip;
1112 target_ulong dr[8];
1113 union {
1114 struct CPUBreakpoint *cpu_breakpoint[4];
1115 struct CPUWatchpoint *cpu_watchpoint[4];
1116 };
1117 int old_exception;
1118
1119 uint64_t vm_vmcb;
1120 uint64_t tsc_offset;
1121 uint64_t intercept;
1122 uint16_t intercept_cr_read;
1123 uint16_t intercept_cr_write;
1124 uint16_t intercept_dr_read;
1125 uint16_t intercept_dr_write;
1126 uint32_t intercept_exceptions;
1127 uint8_t v_tpr;
1128
1129
1130 uint8_t nmi_injected;
1131 uint8_t nmi_pending;
1132
1133
1134 struct {} end_reset_fields;
1135
1136 CPU_COMMON
1137
1138
1139
1140
1141
1142 uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2;
1143
1144 uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2;
1145
1146 uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2;
1147 uint32_t cpuid_vendor1;
1148 uint32_t cpuid_vendor2;
1149 uint32_t cpuid_vendor3;
1150 uint32_t cpuid_version;
1151 FeatureWordArray features;
1152
1153 FeatureWordArray user_features;
1154 uint32_t cpuid_model[12];
1155
1156
1157 uint64_t mtrr_fixed[11];
1158 uint64_t mtrr_deftype;
1159 MTRRVar mtrr_var[MSR_MTRRcap_VCNT];
1160
1161
1162 uint32_t mp_state;
1163 int32_t exception_injected;
1164 int32_t interrupt_injected;
1165 uint8_t soft_interrupt;
1166 uint8_t has_error_code;
1167 uint32_t sipi_vector;
1168 bool tsc_valid;
1169 int64_t tsc_khz;
1170 int64_t user_tsc_khz;
1171 void *kvm_xsave_buf;
1172
1173 uint64_t mcg_cap;
1174 uint64_t mcg_ctl;
1175 uint64_t mcg_ext_ctl;
1176 uint64_t mce_banks[MCE_BANKS_DEF*4];
1177 uint64_t xstate_bv;
1178
1179
1180 uint16_t fpus_vmstate;
1181 uint16_t fptag_vmstate;
1182 uint16_t fpregs_format_vmstate;
1183
1184 uint64_t xss;
1185
1186 TPRAccess tpr_access_type;
1187} CPUX86State;
1188
1189struct kvm_msrs;
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200struct X86CPU {
1201
1202 CPUState parent_obj;
1203
1204
1205 CPUX86State env;
1206
1207 bool hyperv_vapic;
1208 bool hyperv_relaxed_timing;
1209 int hyperv_spinlock_attempts;
1210 char *hyperv_vendor_id;
1211 bool hyperv_time;
1212 bool hyperv_crash;
1213 bool hyperv_reset;
1214 bool hyperv_vpindex;
1215 bool hyperv_runtime;
1216 bool hyperv_synic;
1217 bool hyperv_stimer;
1218 bool check_cpuid;
1219 bool enforce_cpuid;
1220 bool expose_kvm;
1221 bool expose_tcg;
1222 bool migratable;
1223 bool max_features;
1224 uint32_t apic_id;
1225
1226
1227
1228 bool vmware_cpuid_freq;
1229
1230
1231 bool cache_info_passthrough;
1232
1233
1234 uint32_t filtered_features[FEATURE_WORDS];
1235
1236
1237
1238
1239
1240
1241 bool enable_pmu;
1242
1243
1244
1245
1246
1247 bool enable_lmce;
1248
1249
1250
1251
1252
1253 bool enable_l3_cache;
1254
1255
1256 bool enable_cpuid_0xb;
1257
1258
1259 bool full_cpuid_auto_level;
1260
1261
1262 bool fill_mtrr_mask;
1263
1264
1265 bool host_phys_bits;
1266
1267
1268 bool kvm_no_smi_migration;
1269
1270
1271 uint32_t phys_bits;
1272
1273
1274
1275 struct DeviceState *apic_state;
1276 struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram;
1277 Notifier machine_done;
1278
1279 struct kvm_msrs *kvm_msr_buf;
1280
1281 int32_t node_id;
1282 int32_t socket_id;
1283 int32_t core_id;
1284 int32_t thread_id;
1285};
1286
1287static inline X86CPU *x86_env_get_cpu(CPUX86State *env)
1288{
1289 return container_of(env, X86CPU, env);
1290}
1291
1292#define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e))
1293
1294#define ENV_OFFSET offsetof(X86CPU, env)
1295
1296#ifndef CONFIG_USER_ONLY
1297extern struct VMStateDescription vmstate_x86_cpu;
1298#endif
1299
1300
1301
1302
1303
1304void x86_cpu_do_interrupt(CPUState *cpu);
1305bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);
1306
1307int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
1308 int cpuid, void *opaque);
1309int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
1310 int cpuid, void *opaque);
1311int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
1312 void *opaque);
1313int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
1314 void *opaque);
1315
1316void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
1317 Error **errp);
1318
1319void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
1320 int flags);
1321
1322hwaddr x86_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
1323
1324int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
1325int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1326
1327void x86_cpu_exec_enter(CPUState *cpu);
1328void x86_cpu_exec_exit(CPUState *cpu);
1329
1330X86CPU *cpu_x86_init(const char *cpu_model);
1331void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf);
1332int cpu_x86_support_mca_broadcast(CPUX86State *env);
1333
1334int cpu_get_pic_interrupt(CPUX86State *s);
1335
1336void cpu_set_ferr(CPUX86State *s);
1337
1338
1339
1340static inline void cpu_x86_load_seg_cache(CPUX86State *env,
1341 int seg_reg, unsigned int selector,
1342 target_ulong base,
1343 unsigned int limit,
1344 unsigned int flags)
1345{
1346 SegmentCache *sc;
1347 unsigned int new_hflags;
1348
1349 sc = &env->segs[seg_reg];
1350 sc->selector = selector;
1351 sc->base = base;
1352 sc->limit = limit;
1353 sc->flags = flags;
1354
1355
1356 {
1357 if (seg_reg == R_CS) {
1358#ifdef TARGET_X86_64
1359 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
1360
1361 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1362 env->hflags &= ~(HF_ADDSEG_MASK);
1363 } else
1364#endif
1365 {
1366
1367 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
1368 >> (DESC_B_SHIFT - HF_CS32_SHIFT);
1369 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
1370 new_hflags;
1371 }
1372 }
1373 if (seg_reg == R_SS) {
1374 int cpl = (flags >> DESC_DPL_SHIFT) & 3;
1375#if HF_CPL_MASK != 3
1376#error HF_CPL_MASK is hardcoded
1377#endif
1378 env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl;
1379 }
1380 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
1381 >> (DESC_B_SHIFT - HF_SS32_SHIFT);
1382 if (env->hflags & HF_CS64_MASK) {
1383
1384 } else if (!(env->cr[0] & CR0_PE_MASK) ||
1385 (env->eflags & VM_MASK) ||
1386 !(env->hflags & HF_CS32_MASK)) {
1387
1388
1389
1390
1391
1392 new_hflags |= HF_ADDSEG_MASK;
1393 } else {
1394 new_hflags |= ((env->segs[R_DS].base |
1395 env->segs[R_ES].base |
1396 env->segs[R_SS].base) != 0) <<
1397 HF_ADDSEG_SHIFT;
1398 }
1399 env->hflags = (env->hflags &
1400 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
1401 }
1402}
1403
1404static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu,
1405 uint8_t sipi_vector)
1406{
1407 CPUState *cs = CPU(cpu);
1408 CPUX86State *env = &cpu->env;
1409
1410 env->eip = 0;
1411 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
1412 sipi_vector << 12,
1413 env->segs[R_CS].limit,
1414 env->segs[R_CS].flags);
1415 cs->halted = 0;
1416}
1417
1418int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
1419 target_ulong *base, unsigned int *limit,
1420 unsigned int *flags);
1421
1422
1423
1424
1425
1426
1427
1428void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
1429void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
1430void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
1431void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr);
1432void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr);
1433
1434
1435
1436
1437int cpu_x86_signal_handler(int host_signum, void *pinfo,
1438 void *puc);
1439
1440
1441void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1442 uint32_t *eax, uint32_t *ebx,
1443 uint32_t *ecx, uint32_t *edx);
1444void cpu_clear_apic_feature(CPUX86State *env);
1445void host_cpuid(uint32_t function, uint32_t count,
1446 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
1447void host_vendor_fms(char *vendor, int *family, int *model, int *stepping);
1448
1449
1450int x86_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr,
1451 int is_write, int mmu_idx);
1452void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
1453
1454#ifndef CONFIG_USER_ONLY
1455static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
1456{
1457 return !!attrs.secure;
1458}
1459
1460static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs)
1461{
1462 return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs));
1463}
1464
1465uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr);
1466uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr);
1467uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr);
1468uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr);
1469void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val);
1470void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val);
1471void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val);
1472void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val);
1473void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val);
1474#endif
1475
1476void breakpoint_handler(CPUState *cs);
1477
1478
1479void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
1480void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
1481void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
1482void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);
1483
1484
1485uint64_t cpu_get_tsc(CPUX86State *env);
1486
1487#define TARGET_PAGE_BITS 12
1488
1489#ifdef TARGET_X86_64
1490#define TARGET_PHYS_ADDR_SPACE_BITS 52
1491
1492
1493
1494#define TARGET_VIRT_ADDR_SPACE_BITS 47
1495#else
1496#define TARGET_PHYS_ADDR_SPACE_BITS 36
1497#define TARGET_VIRT_ADDR_SPACE_BITS 32
1498#endif
1499
1500
1501
1502# if defined(TARGET_X86_64)
1503# define TCG_PHYS_ADDR_BITS 40
1504# else
1505# define TCG_PHYS_ADDR_BITS 36
1506# endif
1507
1508#define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS)
1509
1510#define cpu_init(cpu_model) CPU(cpu_x86_init(cpu_model))
1511
1512#define cpu_signal_handler cpu_x86_signal_handler
1513#define cpu_list x86_cpu_list
1514
1515
1516#define MMU_MODE0_SUFFIX _ksmap
1517#define MMU_MODE1_SUFFIX _user
1518#define MMU_MODE2_SUFFIX _knosmap
1519#define MMU_KSMAP_IDX 0
1520#define MMU_USER_IDX 1
1521#define MMU_KNOSMAP_IDX 2
1522static inline int cpu_mmu_index(CPUX86State *env, bool ifetch)
1523{
1524 return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX :
1525 (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK))
1526 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
1527}
1528
1529static inline int cpu_mmu_index_kernel(CPUX86State *env)
1530{
1531 return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX :
1532 ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK))
1533 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
1534}
1535
1536#define CC_DST (env->cc_dst)
1537#define CC_SRC (env->cc_src)
1538#define CC_SRC2 (env->cc_src2)
1539#define CC_OP (env->cc_op)
1540
1541
1542static inline target_long lshift(target_long x, int n)
1543{
1544 if (n >= 0) {
1545 return x << n;
1546 } else {
1547 return x >> (-n);
1548 }
1549}
1550
1551
1552#define FT0 (env->ft0)
1553#define ST0 (env->fpregs[env->fpstt].d)
1554#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
1555#define ST1 ST(1)
1556
1557
1558void tcg_x86_init(void);
1559
1560#include "exec/cpu-all.h"
1561#include "svm.h"
1562
1563#if !defined(CONFIG_USER_ONLY)
1564#include "hw/i386/apic.h"
1565#endif
1566
1567static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc,
1568 target_ulong *cs_base, uint32_t *flags)
1569{
1570 *cs_base = env->segs[R_CS].base;
1571 *pc = *cs_base + env->eip;
1572 *flags = env->hflags |
1573 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
1574}
1575
1576void do_cpu_init(X86CPU *cpu);
1577void do_cpu_sipi(X86CPU *cpu);
1578
1579#define MCE_INJECT_BROADCAST 1
1580#define MCE_INJECT_UNCOND_AO 2
1581
1582void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
1583 uint64_t status, uint64_t mcg_status, uint64_t addr,
1584 uint64_t misc, int flags);
1585
1586
1587void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index);
1588void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index,
1589 uintptr_t retaddr);
1590void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index,
1591 int error_code);
1592void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index,
1593 int error_code, uintptr_t retaddr);
1594void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int,
1595 int error_code, int next_eip_addend);
1596
1597
1598extern const uint8_t parity_table[256];
1599uint32_t cpu_cc_compute_all(CPUX86State *env1, int op);
1600
1601static inline uint32_t cpu_compute_eflags(CPUX86State *env)
1602{
1603 uint32_t eflags = env->eflags;
1604 if (tcg_enabled()) {
1605 eflags |= cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK);
1606 }
1607 return eflags;
1608}
1609
1610
1611
1612
1613static inline void cpu_load_eflags(CPUX86State *env, int eflags,
1614 int update_mask)
1615{
1616 CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
1617 CC_OP = CC_OP_EFLAGS;
1618 env->df = 1 - (2 * ((eflags >> 10) & 1));
1619 env->eflags = (env->eflags & ~update_mask) |
1620 (eflags & update_mask) | 0x2;
1621}
1622
1623
1624
1625static inline void cpu_load_efer(CPUX86State *env, uint64_t val)
1626{
1627 env->efer = val;
1628 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK);
1629 if (env->efer & MSR_EFER_LMA) {
1630 env->hflags |= HF_LMA_MASK;
1631 }
1632 if (env->efer & MSR_EFER_SVME) {
1633 env->hflags |= HF_SVME_MASK;
1634 }
1635}
1636
1637static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env)
1638{
1639 return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 });
1640}
1641
1642static inline int32_t x86_get_a20_mask(CPUX86State *env)
1643{
1644 if (env->hflags & HF_SMM_MASK) {
1645 return -1;
1646 } else {
1647 return env->a20_mask;
1648 }
1649}
1650
1651
1652void update_fp_status(CPUX86State *env);
1653void update_mxcsr_status(CPUX86State *env);
1654
1655static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr)
1656{
1657 env->mxcsr = mxcsr;
1658 if (tcg_enabled()) {
1659 update_mxcsr_status(env);
1660 }
1661}
1662
1663static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc)
1664{
1665 env->fpuc = fpuc;
1666 if (tcg_enabled()) {
1667 update_fp_status(env);
1668 }
1669}
1670
1671
1672void helper_lock_init(void);
1673
1674
1675void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
1676 uint64_t param, uintptr_t retaddr);
1677void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_1,
1678 uintptr_t retaddr);
1679void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1);
1680
1681
1682void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw);
1683
1684
1685void do_smm_enter(X86CPU *cpu);
1686
1687
1688void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
1689void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
1690 TPRAccess access);
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701void x86_cpu_change_kvm_default(const char *prop, const char *value);
1702
1703
1704void cpu_sync_bndcs_hflags(CPUX86State *env);
1705
1706
1707const char *get_register_name_32(unsigned int reg);
1708
1709void enable_compat_apic_id_mode(void);
1710
1711#define APIC_DEFAULT_ADDRESS 0xfee00000
1712#define APIC_SPACE_SIZE 0x100000
1713
1714void x86_cpu_dump_local_apic_state(CPUState *cs, FILE *f,
1715 fprintf_function cpu_fprintf, int flags);
1716
1717
1718bool cpu_is_bsp(X86CPU *cpu);
1719
1720void x86_cpu_xrstor_all_areas(X86CPU *cpu, const X86XSaveArea *buf);
1721void x86_cpu_xsave_all_areas(X86CPU *cpu, X86XSaveArea *buf);
1722#endif
1723