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21#include "qemu/osdep.h"
22#include "qapi/error.h"
23#include "cpu.h"
24#include "qemu-common.h"
25#include "exec/exec-all.h"
26
27
28static void lm32_cpu_set_pc(CPUState *cs, vaddr value)
29{
30 LM32CPU *cpu = LM32_CPU(cs);
31
32 cpu->env.pc = value;
33}
34
35
36static gint lm32_cpu_list_compare(gconstpointer a, gconstpointer b)
37{
38 ObjectClass *class_a = (ObjectClass *)a;
39 ObjectClass *class_b = (ObjectClass *)b;
40 const char *name_a, *name_b;
41
42 name_a = object_class_get_name(class_a);
43 name_b = object_class_get_name(class_b);
44 return strcmp(name_a, name_b);
45}
46
47static void lm32_cpu_list_entry(gpointer data, gpointer user_data)
48{
49 ObjectClass *oc = data;
50 CPUListState *s = user_data;
51 const char *typename = object_class_get_name(oc);
52 char *name;
53
54 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_LM32_CPU));
55 (*s->cpu_fprintf)(s->file, " %s\n", name);
56 g_free(name);
57}
58
59
60void lm32_cpu_list(FILE *f, fprintf_function cpu_fprintf)
61{
62 CPUListState s = {
63 .file = f,
64 .cpu_fprintf = cpu_fprintf,
65 };
66 GSList *list;
67
68 list = object_class_get_list(TYPE_LM32_CPU, false);
69 list = g_slist_sort(list, lm32_cpu_list_compare);
70 (*cpu_fprintf)(f, "Available CPUs:\n");
71 g_slist_foreach(list, lm32_cpu_list_entry, &s);
72 g_slist_free(list);
73}
74
75static void lm32_cpu_init_cfg_reg(LM32CPU *cpu)
76{
77 CPULM32State *env = &cpu->env;
78 uint32_t cfg = 0;
79
80 if (cpu->features & LM32_FEATURE_MULTIPLY) {
81 cfg |= CFG_M;
82 }
83
84 if (cpu->features & LM32_FEATURE_DIVIDE) {
85 cfg |= CFG_D;
86 }
87
88 if (cpu->features & LM32_FEATURE_SHIFT) {
89 cfg |= CFG_S;
90 }
91
92 if (cpu->features & LM32_FEATURE_SIGN_EXTEND) {
93 cfg |= CFG_X;
94 }
95
96 if (cpu->features & LM32_FEATURE_I_CACHE) {
97 cfg |= CFG_IC;
98 }
99
100 if (cpu->features & LM32_FEATURE_D_CACHE) {
101 cfg |= CFG_DC;
102 }
103
104 if (cpu->features & LM32_FEATURE_CYCLE_COUNT) {
105 cfg |= CFG_CC;
106 }
107
108 cfg |= (cpu->num_interrupts << CFG_INT_SHIFT);
109 cfg |= (cpu->num_breakpoints << CFG_BP_SHIFT);
110 cfg |= (cpu->num_watchpoints << CFG_WP_SHIFT);
111 cfg |= (cpu->revision << CFG_REV_SHIFT);
112
113 env->cfg = cfg;
114}
115
116static bool lm32_cpu_has_work(CPUState *cs)
117{
118 return cs->interrupt_request & CPU_INTERRUPT_HARD;
119}
120
121
122static void lm32_cpu_reset(CPUState *s)
123{
124 LM32CPU *cpu = LM32_CPU(s);
125 LM32CPUClass *lcc = LM32_CPU_GET_CLASS(cpu);
126 CPULM32State *env = &cpu->env;
127
128 lcc->parent_reset(s);
129
130
131 memset(env, 0, offsetof(CPULM32State, end_reset_fields));
132
133 lm32_cpu_init_cfg_reg(cpu);
134}
135
136static void lm32_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
137{
138 info->mach = bfd_mach_lm32;
139 info->print_insn = print_insn_lm32;
140}
141
142static void lm32_cpu_realizefn(DeviceState *dev, Error **errp)
143{
144 CPUState *cs = CPU(dev);
145 LM32CPUClass *lcc = LM32_CPU_GET_CLASS(dev);
146 Error *local_err = NULL;
147
148 cpu_exec_realizefn(cs, &local_err);
149 if (local_err != NULL) {
150 error_propagate(errp, local_err);
151 return;
152 }
153
154 cpu_reset(cs);
155
156 qemu_init_vcpu(cs);
157
158 lcc->parent_realize(dev, errp);
159}
160
161static void lm32_cpu_initfn(Object *obj)
162{
163 CPUState *cs = CPU(obj);
164 LM32CPU *cpu = LM32_CPU(obj);
165 CPULM32State *env = &cpu->env;
166 static bool tcg_initialized;
167
168 cs->env_ptr = env;
169
170 env->flags = 0;
171
172 if (tcg_enabled() && !tcg_initialized) {
173 tcg_initialized = true;
174 lm32_translate_init();
175 }
176}
177
178static void lm32_basic_cpu_initfn(Object *obj)
179{
180 LM32CPU *cpu = LM32_CPU(obj);
181
182 cpu->revision = 3;
183 cpu->num_interrupts = 32;
184 cpu->num_breakpoints = 4;
185 cpu->num_watchpoints = 4;
186 cpu->features = LM32_FEATURE_SHIFT
187 | LM32_FEATURE_SIGN_EXTEND
188 | LM32_FEATURE_CYCLE_COUNT;
189}
190
191static void lm32_standard_cpu_initfn(Object *obj)
192{
193 LM32CPU *cpu = LM32_CPU(obj);
194
195 cpu->revision = 3;
196 cpu->num_interrupts = 32;
197 cpu->num_breakpoints = 4;
198 cpu->num_watchpoints = 4;
199 cpu->features = LM32_FEATURE_MULTIPLY
200 | LM32_FEATURE_DIVIDE
201 | LM32_FEATURE_SHIFT
202 | LM32_FEATURE_SIGN_EXTEND
203 | LM32_FEATURE_I_CACHE
204 | LM32_FEATURE_CYCLE_COUNT;
205}
206
207static void lm32_full_cpu_initfn(Object *obj)
208{
209 LM32CPU *cpu = LM32_CPU(obj);
210
211 cpu->revision = 3;
212 cpu->num_interrupts = 32;
213 cpu->num_breakpoints = 4;
214 cpu->num_watchpoints = 4;
215 cpu->features = LM32_FEATURE_MULTIPLY
216 | LM32_FEATURE_DIVIDE
217 | LM32_FEATURE_SHIFT
218 | LM32_FEATURE_SIGN_EXTEND
219 | LM32_FEATURE_I_CACHE
220 | LM32_FEATURE_D_CACHE
221 | LM32_FEATURE_CYCLE_COUNT;
222}
223
224typedef struct LM32CPUInfo {
225 const char *name;
226 void (*initfn)(Object *obj);
227} LM32CPUInfo;
228
229static const LM32CPUInfo lm32_cpus[] = {
230 {
231 .name = "lm32-basic",
232 .initfn = lm32_basic_cpu_initfn,
233 },
234 {
235 .name = "lm32-standard",
236 .initfn = lm32_standard_cpu_initfn,
237 },
238 {
239 .name = "lm32-full",
240 .initfn = lm32_full_cpu_initfn,
241 },
242};
243
244static ObjectClass *lm32_cpu_class_by_name(const char *cpu_model)
245{
246 ObjectClass *oc;
247 char *typename;
248
249 if (cpu_model == NULL) {
250 return NULL;
251 }
252
253 typename = g_strdup_printf("%s-" TYPE_LM32_CPU, cpu_model);
254 oc = object_class_by_name(typename);
255 g_free(typename);
256 if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_LM32_CPU) ||
257 object_class_is_abstract(oc))) {
258 oc = NULL;
259 }
260 return oc;
261}
262
263static void lm32_cpu_class_init(ObjectClass *oc, void *data)
264{
265 LM32CPUClass *lcc = LM32_CPU_CLASS(oc);
266 CPUClass *cc = CPU_CLASS(oc);
267 DeviceClass *dc = DEVICE_CLASS(oc);
268
269 lcc->parent_realize = dc->realize;
270 dc->realize = lm32_cpu_realizefn;
271
272 lcc->parent_reset = cc->reset;
273 cc->reset = lm32_cpu_reset;
274
275 cc->class_by_name = lm32_cpu_class_by_name;
276 cc->has_work = lm32_cpu_has_work;
277 cc->do_interrupt = lm32_cpu_do_interrupt;
278 cc->cpu_exec_interrupt = lm32_cpu_exec_interrupt;
279 cc->dump_state = lm32_cpu_dump_state;
280 cc->set_pc = lm32_cpu_set_pc;
281 cc->gdb_read_register = lm32_cpu_gdb_read_register;
282 cc->gdb_write_register = lm32_cpu_gdb_write_register;
283#ifdef CONFIG_USER_ONLY
284 cc->handle_mmu_fault = lm32_cpu_handle_mmu_fault;
285#else
286 cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
287 cc->vmsd = &vmstate_lm32_cpu;
288#endif
289 cc->gdb_num_core_regs = 32 + 7;
290 cc->gdb_stop_before_watchpoint = true;
291 cc->debug_excp_handler = lm32_debug_excp_handler;
292 cc->disas_set_info = lm32_cpu_disas_set_info;
293}
294
295static void lm32_register_cpu_type(const LM32CPUInfo *info)
296{
297 TypeInfo type_info = {
298 .parent = TYPE_LM32_CPU,
299 .instance_init = info->initfn,
300 };
301
302 type_info.name = g_strdup_printf("%s-" TYPE_LM32_CPU, info->name);
303 type_register(&type_info);
304 g_free((void *)type_info.name);
305}
306
307static const TypeInfo lm32_cpu_type_info = {
308 .name = TYPE_LM32_CPU,
309 .parent = TYPE_CPU,
310 .instance_size = sizeof(LM32CPU),
311 .instance_init = lm32_cpu_initfn,
312 .abstract = true,
313 .class_size = sizeof(LM32CPUClass),
314 .class_init = lm32_cpu_class_init,
315};
316
317static void lm32_cpu_register_types(void)
318{
319 int i;
320
321 type_register_static(&lm32_cpu_type_info);
322 for (i = 0; i < ARRAY_SIZE(lm32_cpus); i++) {
323 lm32_register_cpu_type(&lm32_cpus[i]);
324 }
325}
326
327type_init(lm32_cpu_register_types)
328
