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20#include "qemu/osdep.h"
21#include "qapi/error.h"
22#include "cpu.h"
23#include "exec/exec-all.h"
24#include "exec/helper-proto.h"
25#include "qemu/error-report.h"
26#include "sysemu/hw_accel.h"
27#include "kvm_ppc.h"
28#include "mmu-hash64.h"
29#include "exec/log.h"
30#include "hw/hw.h"
31#include "mmu-book3s-v3.h"
32
33
34
35#ifdef DEBUG_SLB
36# define LOG_SLB(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__)
37#else
38# define LOG_SLB(...) do { } while (0)
39#endif
40
41
42
43
44
45static ppc_slb_t *slb_lookup(PowerPCCPU *cpu, target_ulong eaddr)
46{
47 CPUPPCState *env = &cpu->env;
48 uint64_t esid_256M, esid_1T;
49 int n;
50
51 LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr);
52
53 esid_256M = (eaddr & SEGMENT_MASK_256M) | SLB_ESID_V;
54 esid_1T = (eaddr & SEGMENT_MASK_1T) | SLB_ESID_V;
55
56 for (n = 0; n < env->slb_nr; n++) {
57 ppc_slb_t *slb = &env->slb[n];
58
59 LOG_SLB("%s: slot %d %016" PRIx64 " %016"
60 PRIx64 "\n", __func__, n, slb->esid, slb->vsid);
61
62
63
64 if (((slb->esid == esid_256M) &&
65 ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_256M))
66 || ((slb->esid == esid_1T) &&
67 ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_1T))) {
68 return slb;
69 }
70 }
71
72 return NULL;
73}
74
75void dump_slb(FILE *f, fprintf_function cpu_fprintf, PowerPCCPU *cpu)
76{
77 CPUPPCState *env = &cpu->env;
78 int i;
79 uint64_t slbe, slbv;
80
81 cpu_synchronize_state(CPU(cpu));
82
83 cpu_fprintf(f, "SLB\tESID\t\t\tVSID\n");
84 for (i = 0; i < env->slb_nr; i++) {
85 slbe = env->slb[i].esid;
86 slbv = env->slb[i].vsid;
87 if (slbe == 0 && slbv == 0) {
88 continue;
89 }
90 cpu_fprintf(f, "%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n",
91 i, slbe, slbv);
92 }
93}
94
95void helper_slbia(CPUPPCState *env)
96{
97 int n;
98
99
100 for (n = 1; n < env->slb_nr; n++) {
101 ppc_slb_t *slb = &env->slb[n];
102
103 if (slb->esid & SLB_ESID_V) {
104 slb->esid &= ~SLB_ESID_V;
105
106
107
108
109 env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH;
110 }
111 }
112}
113
114static void __helper_slbie(CPUPPCState *env, target_ulong addr,
115 target_ulong global)
116{
117 PowerPCCPU *cpu = ppc_env_get_cpu(env);
118 ppc_slb_t *slb;
119
120 slb = slb_lookup(cpu, addr);
121 if (!slb) {
122 return;
123 }
124
125 if (slb->esid & SLB_ESID_V) {
126 slb->esid &= ~SLB_ESID_V;
127
128
129
130
131
132 env->tlb_need_flush |=
133 (global == false ? TLB_NEED_LOCAL_FLUSH : TLB_NEED_GLOBAL_FLUSH);
134 }
135}
136
137void helper_slbie(CPUPPCState *env, target_ulong addr)
138{
139 __helper_slbie(env, addr, false);
140}
141
142void helper_slbieg(CPUPPCState *env, target_ulong addr)
143{
144 __helper_slbie(env, addr, true);
145}
146
147int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
148 target_ulong esid, target_ulong vsid)
149{
150 CPUPPCState *env = &cpu->env;
151 ppc_slb_t *slb = &env->slb[slot];
152 const struct ppc_one_seg_page_size *sps = NULL;
153 int i;
154
155 if (slot >= env->slb_nr) {
156 return -1;
157 }
158 if (esid & ~(SLB_ESID_ESID | SLB_ESID_V)) {
159 return -1;
160 }
161 if (vsid & (SLB_VSID_B & ~SLB_VSID_B_1T)) {
162 return -1;
163 }
164 if ((vsid & SLB_VSID_B) && !(env->mmu_model & POWERPC_MMU_1TSEG)) {
165 return -1;
166 }
167
168 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
169 const struct ppc_one_seg_page_size *sps1 = &env->sps.sps[i];
170
171 if (!sps1->page_shift) {
172 break;
173 }
174
175 if ((vsid & SLB_VSID_LLP_MASK) == sps1->slb_enc) {
176 sps = sps1;
177 break;
178 }
179 }
180
181 if (!sps) {
182 error_report("Bad page size encoding in SLB store: slot "TARGET_FMT_lu
183 " esid 0x"TARGET_FMT_lx" vsid 0x"TARGET_FMT_lx,
184 slot, esid, vsid);
185 return -1;
186 }
187
188 slb->esid = esid;
189 slb->vsid = vsid;
190 slb->sps = sps;
191
192 LOG_SLB("%s: " TARGET_FMT_lu " " TARGET_FMT_lx " - " TARGET_FMT_lx
193 " => %016" PRIx64 " %016" PRIx64 "\n", __func__, slot, esid, vsid,
194 slb->esid, slb->vsid);
195
196 return 0;
197}
198
199static int ppc_load_slb_esid(PowerPCCPU *cpu, target_ulong rb,
200 target_ulong *rt)
201{
202 CPUPPCState *env = &cpu->env;
203 int slot = rb & 0xfff;
204 ppc_slb_t *slb = &env->slb[slot];
205
206 if (slot >= env->slb_nr) {
207 return -1;
208 }
209
210 *rt = slb->esid;
211 return 0;
212}
213
214static int ppc_load_slb_vsid(PowerPCCPU *cpu, target_ulong rb,
215 target_ulong *rt)
216{
217 CPUPPCState *env = &cpu->env;
218 int slot = rb & 0xfff;
219 ppc_slb_t *slb = &env->slb[slot];
220
221 if (slot >= env->slb_nr) {
222 return -1;
223 }
224
225 *rt = slb->vsid;
226 return 0;
227}
228
229static int ppc_find_slb_vsid(PowerPCCPU *cpu, target_ulong rb,
230 target_ulong *rt)
231{
232 CPUPPCState *env = &cpu->env;
233 ppc_slb_t *slb;
234
235 if (!msr_is_64bit(env, env->msr)) {
236 rb &= 0xffffffff;
237 }
238 slb = slb_lookup(cpu, rb);
239 if (slb == NULL) {
240 *rt = (target_ulong)-1ul;
241 } else {
242 *rt = slb->vsid;
243 }
244 return 0;
245}
246
247void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
248{
249 PowerPCCPU *cpu = ppc_env_get_cpu(env);
250
251 if (ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs) < 0) {
252 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
253 POWERPC_EXCP_INVAL, GETPC());
254 }
255}
256
257target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb)
258{
259 PowerPCCPU *cpu = ppc_env_get_cpu(env);
260 target_ulong rt = 0;
261
262 if (ppc_load_slb_esid(cpu, rb, &rt) < 0) {
263 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
264 POWERPC_EXCP_INVAL, GETPC());
265 }
266 return rt;
267}
268
269target_ulong helper_find_slb_vsid(CPUPPCState *env, target_ulong rb)
270{
271 PowerPCCPU *cpu = ppc_env_get_cpu(env);
272 target_ulong rt = 0;
273
274 if (ppc_find_slb_vsid(cpu, rb, &rt) < 0) {
275 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
276 POWERPC_EXCP_INVAL, GETPC());
277 }
278 return rt;
279}
280
281target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
282{
283 PowerPCCPU *cpu = ppc_env_get_cpu(env);
284 target_ulong rt = 0;
285
286 if (ppc_load_slb_vsid(cpu, rb, &rt) < 0) {
287 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
288 POWERPC_EXCP_INVAL, GETPC());
289 }
290 return rt;
291}
292
293
294static inline int ppc_hash64_pte_noexec_guard(PowerPCCPU *cpu,
295 ppc_hash_pte64_t pte)
296{
297
298 return (pte.pte1 & HPTE64_R_N) || (pte.pte1 & HPTE64_R_G) ?
299 PAGE_READ | PAGE_WRITE : PAGE_READ | PAGE_WRITE | PAGE_EXEC;
300}
301
302
303static int ppc_hash64_pte_prot(PowerPCCPU *cpu,
304 ppc_slb_t *slb, ppc_hash_pte64_t pte)
305{
306 CPUPPCState *env = &cpu->env;
307 unsigned pp, key;
308
309
310 int prot = 0;
311
312 key = !!(msr_pr ? (slb->vsid & SLB_VSID_KP)
313 : (slb->vsid & SLB_VSID_KS));
314 pp = (pte.pte1 & HPTE64_R_PP) | ((pte.pte1 & HPTE64_R_PP0) >> 61);
315
316 if (key == 0) {
317 switch (pp) {
318 case 0x0:
319 case 0x1:
320 case 0x2:
321 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
322 break;
323
324 case 0x3:
325 case 0x6:
326 prot = PAGE_READ | PAGE_EXEC;
327 break;
328 }
329 } else {
330 switch (pp) {
331 case 0x0:
332 case 0x6:
333 break;
334
335 case 0x1:
336 case 0x3:
337 prot = PAGE_READ | PAGE_EXEC;
338 break;
339
340 case 0x2:
341 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
342 break;
343 }
344 }
345
346 return prot;
347}
348
349
350static int ppc_hash64_iamr_prot(PowerPCCPU *cpu, int key)
351{
352 CPUPPCState *env = &cpu->env;
353 int iamr_bits = (env->spr[SPR_IAMR] >> 2 * (31 - key)) & 0x3;
354
355
356
357
358
359
360
361
362 return (iamr_bits & 0x1) ? PAGE_READ | PAGE_WRITE :
363 PAGE_READ | PAGE_WRITE | PAGE_EXEC;
364}
365
366static int ppc_hash64_amr_prot(PowerPCCPU *cpu, ppc_hash_pte64_t pte)
367{
368 CPUPPCState *env = &cpu->env;
369 int key, amrbits;
370 int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
371
372
373 if (!(env->mmu_model & POWERPC_MMU_AMR)) {
374 return prot;
375 }
376
377 key = HPTE64_R_KEY(pte.pte1);
378 amrbits = (env->spr[SPR_AMR] >> 2*(31 - key)) & 0x3;
379
380
381
382
383
384
385
386
387 if (amrbits & 0x2) {
388 prot &= ~PAGE_WRITE;
389 }
390
391
392
393
394 if (amrbits & 0x1) {
395 prot &= ~PAGE_READ;
396 }
397
398 switch (env->mmu_model) {
399
400
401
402
403
404
405 case POWERPC_MMU_2_07:
406 case POWERPC_MMU_3_00:
407 prot &= ppc_hash64_iamr_prot(cpu, key);
408 break;
409 default:
410 break;
411 }
412
413 return prot;
414}
415
416const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu,
417 hwaddr ptex, int n)
418{
419 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
420 hwaddr base = ppc_hash64_hpt_base(cpu);
421 hwaddr plen = n * HASH_PTE_SIZE_64;
422 const ppc_hash_pte64_t *hptes;
423
424 if (cpu->vhyp) {
425 PPCVirtualHypervisorClass *vhc =
426 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
427 return vhc->map_hptes(cpu->vhyp, ptex, n);
428 }
429
430 if (!base) {
431 return NULL;
432 }
433
434 hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false);
435 if (plen < (n * HASH_PTE_SIZE_64)) {
436 hw_error("%s: Unable to map all requested HPTEs\n", __func__);
437 }
438 return hptes;
439}
440
441void ppc_hash64_unmap_hptes(PowerPCCPU *cpu, const ppc_hash_pte64_t *hptes,
442 hwaddr ptex, int n)
443{
444 if (cpu->vhyp) {
445 PPCVirtualHypervisorClass *vhc =
446 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
447 vhc->unmap_hptes(cpu->vhyp, hptes, ptex, n);
448 return;
449 }
450
451 address_space_unmap(CPU(cpu)->as, (void *)hptes, n * HASH_PTE_SIZE_64,
452 false, n * HASH_PTE_SIZE_64);
453}
454
455static unsigned hpte_page_shift(const struct ppc_one_seg_page_size *sps,
456 uint64_t pte0, uint64_t pte1)
457{
458 int i;
459
460 if (!(pte0 & HPTE64_V_LARGE)) {
461 if (sps->page_shift != 12) {
462
463 return 0;
464 }
465
466 return 12;
467 }
468
469 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
470 const struct ppc_one_page_size *ps = &sps->enc[i];
471 uint64_t mask;
472
473 if (!ps->page_shift) {
474 break;
475 }
476
477 if (ps->page_shift == 12) {
478
479 continue;
480 }
481
482 mask = ((1ULL << ps->page_shift) - 1) & HPTE64_R_RPN;
483
484 if ((pte1 & mask) == ((uint64_t)ps->pte_enc << HPTE64_R_RPN_SHIFT)) {
485 return ps->page_shift;
486 }
487 }
488
489 return 0;
490}
491
492static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash,
493 const struct ppc_one_seg_page_size *sps,
494 target_ulong ptem,
495 ppc_hash_pte64_t *pte, unsigned *pshift)
496{
497 int i;
498 const ppc_hash_pte64_t *pteg;
499 target_ulong pte0, pte1;
500 target_ulong ptex;
501
502 ptex = (hash & ppc_hash64_hpt_mask(cpu)) * HPTES_PER_GROUP;
503 pteg = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP);
504 if (!pteg) {
505 return -1;
506 }
507 for (i = 0; i < HPTES_PER_GROUP; i++) {
508 pte0 = ppc_hash64_hpte0(cpu, pteg, i);
509 pte1 = ppc_hash64_hpte1(cpu, pteg, i);
510
511
512 if (HPTE64_V_COMPARE(pte0, ptem)) {
513 *pshift = hpte_page_shift(sps, pte0, pte1);
514
515
516
517
518
519
520
521 if (*pshift == 0) {
522 continue;
523 }
524
525
526
527 pte->pte0 = pte0;
528 pte->pte1 = pte1;
529 ppc_hash64_unmap_hptes(cpu, pteg, ptex, HPTES_PER_GROUP);
530 return ptex + i;
531 }
532 }
533 ppc_hash64_unmap_hptes(cpu, pteg, ptex, HPTES_PER_GROUP);
534
535
536
537 return -1;
538}
539
540static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
541 ppc_slb_t *slb, target_ulong eaddr,
542 ppc_hash_pte64_t *pte, unsigned *pshift)
543{
544 CPUPPCState *env = &cpu->env;
545 hwaddr hash, ptex;
546 uint64_t vsid, epnmask, epn, ptem;
547 const struct ppc_one_seg_page_size *sps = slb->sps;
548
549
550
551 assert(sps);
552
553
554 if (env->spr[SPR_LPCR] & LPCR_ISL) {
555
556 sps = &env->sps.sps[0];
557 assert(sps->page_shift == 12);
558 }
559
560 epnmask = ~((1ULL << sps->page_shift) - 1);
561
562 if (slb->vsid & SLB_VSID_B) {
563
564 vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT_1T;
565 epn = (eaddr & ~SEGMENT_MASK_1T) & epnmask;
566 hash = vsid ^ (vsid << 25) ^ (epn >> sps->page_shift);
567 } else {
568
569 vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT;
570 epn = (eaddr & ~SEGMENT_MASK_256M) & epnmask;
571 hash = vsid ^ (epn >> sps->page_shift);
572 }
573 ptem = (slb->vsid & SLB_VSID_PTEM) | ((epn >> 16) & HPTE64_V_AVPN);
574 ptem |= HPTE64_V_VALID;
575
576
577 qemu_log_mask(CPU_LOG_MMU,
578 "htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
579 " hash " TARGET_FMT_plx "\n",
580 ppc_hash64_hpt_base(cpu), ppc_hash64_hpt_mask(cpu), hash);
581
582
583 qemu_log_mask(CPU_LOG_MMU,
584 "0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
585 " vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
586 " hash=" TARGET_FMT_plx "\n",
587 ppc_hash64_hpt_base(cpu), ppc_hash64_hpt_mask(cpu),
588 vsid, ptem, hash);
589 ptex = ppc_hash64_pteg_search(cpu, hash, sps, ptem, pte, pshift);
590
591 if (ptex == -1) {
592
593 ptem |= HPTE64_V_SECONDARY;
594 qemu_log_mask(CPU_LOG_MMU,
595 "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
596 " vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx
597 " hash=" TARGET_FMT_plx "\n", ppc_hash64_hpt_base(cpu),
598 ppc_hash64_hpt_mask(cpu), vsid, ptem, ~hash);
599
600 ptex = ppc_hash64_pteg_search(cpu, ~hash, sps, ptem, pte, pshift);
601 }
602
603 return ptex;
604}
605
606unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
607 uint64_t pte0, uint64_t pte1)
608{
609 CPUPPCState *env = &cpu->env;
610 int i;
611
612 if (!(pte0 & HPTE64_V_LARGE)) {
613 return 12;
614 }
615
616
617
618
619
620 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
621 const struct ppc_one_seg_page_size *sps = &env->sps.sps[i];
622 unsigned shift;
623
624 if (!sps->page_shift) {
625 break;
626 }
627
628 shift = hpte_page_shift(sps, pte0, pte1);
629 if (shift) {
630 return shift;
631 }
632 }
633
634 return 0;
635}
636
637static void ppc_hash64_set_isi(CPUState *cs, CPUPPCState *env,
638 uint64_t error_code)
639{
640 bool vpm;
641
642 if (msr_ir) {
643 vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1);
644 } else {
645 switch (env->mmu_model) {
646 case POWERPC_MMU_3_00:
647
648 vpm = true;
649 break;
650 default:
651 vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
652 break;
653 }
654 }
655 if (vpm && !msr_hv) {
656 cs->exception_index = POWERPC_EXCP_HISI;
657 } else {
658 cs->exception_index = POWERPC_EXCP_ISI;
659 }
660 env->error_code = error_code;
661}
662
663static void ppc_hash64_set_dsi(CPUState *cs, CPUPPCState *env, uint64_t dar,
664 uint64_t dsisr)
665{
666 bool vpm;
667
668 if (msr_dr) {
669 vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1);
670 } else {
671 switch (env->mmu_model) {
672 case POWERPC_MMU_3_00:
673
674 vpm = true;
675 break;
676 default:
677 vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
678 break;
679 }
680 }
681 if (vpm && !msr_hv) {
682 cs->exception_index = POWERPC_EXCP_HDSI;
683 env->spr[SPR_HDAR] = dar;
684 env->spr[SPR_HDSISR] = dsisr;
685 } else {
686 cs->exception_index = POWERPC_EXCP_DSI;
687 env->spr[SPR_DAR] = dar;
688 env->spr[SPR_DSISR] = dsisr;
689 }
690 env->error_code = 0;
691}
692
693
694int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
695 int rwx, int mmu_idx)
696{
697 CPUState *cs = CPU(cpu);
698 CPUPPCState *env = &cpu->env;
699 ppc_slb_t *slb;
700 unsigned apshift;
701 hwaddr ptex;
702 ppc_hash_pte64_t pte;
703 int exec_prot, pp_prot, amr_prot, prot;
704 uint64_t new_pte1;
705 const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC};
706 hwaddr raddr;
707
708 assert((rwx == 0) || (rwx == 1) || (rwx == 2));
709
710
711
712
713
714
715
716
717
718 if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
719
720
721 raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
722
723
724 if (msr_hv || !env->has_hv_mode) {
725 if (!(eaddr >> 63)) {
726 raddr |= env->spr[SPR_HRMOR];
727 }
728 } else {
729
730 if (env->spr[SPR_LPCR] & LPCR_VPM0) {
731 slb = &env->vrma_slb;
732 if (slb->sps) {
733 goto skip_slb_search;
734 }
735
736 cs->exception_index = POWERPC_EXCP_MCHECK;
737 env->error_code = 0;
738 return 1;
739 } else if (raddr < env->rmls) {
740
741 raddr |= env->spr[SPR_RMOR];
742 } else {
743
744 if (rwx == 2) {
745 ppc_hash64_set_isi(cs, env, SRR1_PROTFAULT);
746 } else {
747 int dsisr = DSISR_PROTFAULT;
748 if (rwx == 1) {
749 dsisr |= DSISR_ISSTORE;
750 }
751 ppc_hash64_set_dsi(cs, env, eaddr, dsisr);
752 }
753 return 1;
754 }
755 }
756 tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
757 PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx,
758 TARGET_PAGE_SIZE);
759 return 0;
760 }
761
762
763 slb = slb_lookup(cpu, eaddr);
764 if (!slb) {
765
766 if ((env->mmu_model & POWERPC_MMU_V3) && ppc64_use_proc_tbl(cpu)) {
767
768 error_report("Segment Table Support Unimplemented");
769 exit(1);
770 }
771
772 if (rwx == 2) {
773 cs->exception_index = POWERPC_EXCP_ISEG;
774 env->error_code = 0;
775 } else {
776 cs->exception_index = POWERPC_EXCP_DSEG;
777 env->error_code = 0;
778 env->spr[SPR_DAR] = eaddr;
779 }
780 return 1;
781 }
782
783skip_slb_search:
784
785
786 if ((rwx == 2) && (slb->vsid & SLB_VSID_N)) {
787 ppc_hash64_set_isi(cs, env, SRR1_NOEXEC_GUARD);
788 return 1;
789 }
790
791
792 ptex = ppc_hash64_htab_lookup(cpu, slb, eaddr, &pte, &apshift);
793 if (ptex == -1) {
794 if (rwx == 2) {
795 ppc_hash64_set_isi(cs, env, SRR1_NOPTE);
796 } else {
797 int dsisr = DSISR_NOPTE;
798 if (rwx == 1) {
799 dsisr |= DSISR_ISSTORE;
800 }
801 ppc_hash64_set_dsi(cs, env, eaddr, dsisr);
802 }
803 return 1;
804 }
805 qemu_log_mask(CPU_LOG_MMU,
806 "found PTE at index %08" HWADDR_PRIx "\n", ptex);
807
808
809
810 exec_prot = ppc_hash64_pte_noexec_guard(cpu, pte);
811 pp_prot = ppc_hash64_pte_prot(cpu, slb, pte);
812 amr_prot = ppc_hash64_amr_prot(cpu, pte);
813 prot = exec_prot & pp_prot & amr_prot;
814
815 if ((need_prot[rwx] & ~prot) != 0) {
816
817 qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n");
818 if (rwx == 2) {
819 int srr1 = 0;
820 if (PAGE_EXEC & ~exec_prot) {
821 srr1 |= SRR1_NOEXEC_GUARD;
822 } else if (PAGE_EXEC & ~pp_prot) {
823 srr1 |= SRR1_PROTFAULT;
824 }
825 if (PAGE_EXEC & ~amr_prot) {
826 srr1 |= SRR1_IAMR;
827 }
828 ppc_hash64_set_isi(cs, env, srr1);
829 } else {
830 int dsisr = 0;
831 if (need_prot[rwx] & ~pp_prot) {
832 dsisr |= DSISR_PROTFAULT;
833 }
834 if (rwx == 1) {
835 dsisr |= DSISR_ISSTORE;
836 }
837 if (need_prot[rwx] & ~amr_prot) {
838 dsisr |= DSISR_AMR;
839 }
840 ppc_hash64_set_dsi(cs, env, eaddr, dsisr);
841 }
842 return 1;
843 }
844
845 qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n");
846
847
848
849 new_pte1 = pte.pte1 | HPTE64_R_R;
850 if (rwx == 1) {
851 new_pte1 |= HPTE64_R_C;
852 } else {
853
854
855 prot &= ~PAGE_WRITE;
856 }
857
858 if (new_pte1 != pte.pte1) {
859 ppc_hash64_store_hpte(cpu, ptex, pte.pte0, new_pte1);
860 }
861
862
863
864 raddr = deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, eaddr);
865
866 tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
867 prot, mmu_idx, 1ULL << apshift);
868
869 return 0;
870}
871
872hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr)
873{
874 CPUPPCState *env = &cpu->env;
875 ppc_slb_t *slb;
876 hwaddr ptex, raddr;
877 ppc_hash_pte64_t pte;
878 unsigned apshift;
879
880
881 if (msr_dr == 0) {
882
883 raddr = addr & 0x0FFFFFFFFFFFFFFFULL;
884
885
886 if ((msr_hv || !env->has_hv_mode) && !(addr >> 63)) {
887 return raddr | env->spr[SPR_HRMOR];
888 }
889
890
891 if (env->spr[SPR_LPCR] & LPCR_VPM0) {
892 slb = &env->vrma_slb;
893 if (!slb->sps) {
894 return -1;
895 }
896 } else if (raddr < env->rmls) {
897
898 return raddr | env->spr[SPR_RMOR];
899 } else {
900 return -1;
901 }
902 } else {
903 slb = slb_lookup(cpu, addr);
904 if (!slb) {
905 return -1;
906 }
907 }
908
909 ptex = ppc_hash64_htab_lookup(cpu, slb, addr, &pte, &apshift);
910 if (ptex == -1) {
911 return -1;
912 }
913
914 return deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, addr)
915 & TARGET_PAGE_MASK;
916}
917
918void ppc_hash64_store_hpte(PowerPCCPU *cpu, hwaddr ptex,
919 uint64_t pte0, uint64_t pte1)
920{
921 hwaddr base = ppc_hash64_hpt_base(cpu);
922 hwaddr offset = ptex * HASH_PTE_SIZE_64;
923
924 if (cpu->vhyp) {
925 PPCVirtualHypervisorClass *vhc =
926 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
927 vhc->store_hpte(cpu->vhyp, ptex, pte0, pte1);
928 return;
929 }
930
931 stq_phys(CPU(cpu)->as, base + offset, pte0);
932 stq_phys(CPU(cpu)->as, base + offset + HASH_PTE_SIZE_64 / 2, pte1);
933}
934
935void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong ptex,
936 target_ulong pte0, target_ulong pte1)
937{
938
939
940
941
942
943 cpu->env.tlb_need_flush = TLB_NEED_GLOBAL_FLUSH | TLB_NEED_LOCAL_FLUSH;
944}
945
946void ppc_hash64_update_rmls(CPUPPCState *env)
947{
948 uint64_t lpcr = env->spr[SPR_LPCR];
949
950
951
952
953
954
955 switch ((lpcr & LPCR_RMLS) >> LPCR_RMLS_SHIFT) {
956 case 0x8:
957 env->rmls = 0x2000000ull;
958 break;
959 case 0x3:
960 env->rmls = 0x4000000ull;
961 break;
962 case 0x7:
963 env->rmls = 0x8000000ull;
964 break;
965 case 0x4:
966 env->rmls = 0x10000000ull;
967 break;
968 case 0x2:
969 env->rmls = 0x40000000ull;
970 break;
971 case 0x1:
972 env->rmls = 0x400000000ull;
973 break;
974 default:
975
976 env->rmls = 0;
977 }
978}
979
980void ppc_hash64_update_vrma(CPUPPCState *env)
981{
982 const struct ppc_one_seg_page_size *sps = NULL;
983 target_ulong esid, vsid, lpcr;
984 ppc_slb_t *slb = &env->vrma_slb;
985 uint32_t vrmasd;
986 int i;
987
988
989 slb->esid = slb->vsid = 0;
990 slb->sps = NULL;
991
992
993 lpcr = env->spr[SPR_LPCR];
994 if (!(lpcr & LPCR_VPM0)) {
995 return;
996 }
997
998
999
1000
1001 vsid = SLB_VSID_VRMA;
1002 vrmasd = (lpcr & LPCR_VRMASD) >> LPCR_VRMASD_SHIFT;
1003 vsid |= (vrmasd << 4) & (SLB_VSID_L | SLB_VSID_LP);
1004 esid = SLB_ESID_V;
1005
1006 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
1007 const struct ppc_one_seg_page_size *sps1 = &env->sps.sps[i];
1008
1009 if (!sps1->page_shift) {
1010 break;
1011 }
1012
1013 if ((vsid & SLB_VSID_LLP_MASK) == sps1->slb_enc) {
1014 sps = sps1;
1015 break;
1016 }
1017 }
1018
1019 if (!sps) {
1020 error_report("Bad page size encoding esid 0x"TARGET_FMT_lx
1021 " vsid 0x"TARGET_FMT_lx, esid, vsid);
1022 return;
1023 }
1024
1025 slb->vsid = vsid;
1026 slb->esid = esid;
1027 slb->sps = sps;
1028}
1029
1030void helper_store_lpcr(CPUPPCState *env, target_ulong val)
1031{
1032 uint64_t lpcr = 0;
1033
1034
1035 switch (POWERPC_MMU_VER(env->mmu_model)) {
1036 case POWERPC_MMU_VER_64B:
1037 if (val & 0x40) {
1038 lpcr |= LPCR_LPES0;
1039 }
1040 if (val & 0x8000000000000000ull) {
1041 lpcr |= LPCR_LPES1;
1042 }
1043 if (val & 0x20) {
1044 lpcr |= (0x4ull << LPCR_RMLS_SHIFT);
1045 }
1046 if (val & 0x4000000000000000ull) {
1047 lpcr |= (0x2ull << LPCR_RMLS_SHIFT);
1048 }
1049 if (val & 0x2000000000000000ull) {
1050 lpcr |= (0x1ull << LPCR_RMLS_SHIFT);
1051 }
1052 env->spr[SPR_RMOR] = ((lpcr >> 41) & 0xffffull) << 26;
1053
1054
1055
1056
1057
1058
1059
1060
1061 break;
1062 case POWERPC_MMU_VER_2_03:
1063 lpcr = val & (LPCR_RMLS | LPCR_ILE |
1064 LPCR_LPES0 | LPCR_LPES1 |
1065 LPCR_RMI | LPCR_HDICE);
1066 break;
1067 case POWERPC_MMU_VER_2_06:
1068 lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
1069 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
1070 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
1071 LPCR_MER | LPCR_TC |
1072 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE);
1073 break;
1074 case POWERPC_MMU_VER_2_07:
1075 lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
1076 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
1077 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
1078 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
1079 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE);
1080 break;
1081 case POWERPC_MMU_VER_3_00:
1082 lpcr = val & (LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
1083 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
1084 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL |
1085 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
1086 LPCR_DEE | LPCR_OEE)) | LPCR_MER | LPCR_GTSE | LPCR_TC |
1087 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE);
1088 break;
1089 default:
1090 ;
1091 }
1092 env->spr[SPR_LPCR] = lpcr;
1093 ppc_hash64_update_rmls(env);
1094 ppc_hash64_update_vrma(env);
1095}
1096