LXR qemu/target/ppc/translate

   1/*
   2 *  PowerPC CPU initialization for qemu.
   3 *
   4 *  Copyright (c) 2003-2007 Jocelyn Mayer
   5 *  Copyright 2011 Freescale Semiconductor, Inc.
   6 *
   7 * This library is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU Lesser General Public
   9 * License as published by the Free Software Foundation; either
  10 * version 2 of the License, or (at your option) any later version.
  11 *
  12 * This library is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 * Lesser General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU Lesser General Public
  18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19 */
  20
  21#include "qemu/osdep.h"
  22#include "disas/bfd.h"
  23#include "exec/gdbstub.h"
  24#include "kvm_ppc.h"
  25#include "sysemu/arch_init.h"
  26#include "sysemu/cpus.h"
  27#include "sysemu/hw_accel.h"
  28#include "cpu-models.h"
  29#include "mmu-hash32.h"
  30#include "mmu-hash64.h"
  31#include "qemu/error-report.h"
  32#include "qapi/visitor.h"
  33#include "hw/qdev-properties.h"
  34#include "hw/ppc/ppc.h"
  35#include "mmu-book3s-v3.h"
  36#include "sysemu/qtest.h"
  37
  38//#define PPC_DUMP_CPU
  39//#define PPC_DEBUG_SPR
  40//#define PPC_DUMP_SPR_ACCESSES
  41/* #define USE_APPLE_GDB */
  42
  43/* Generic callbacks:
  44 * do nothing but store/retrieve spr value
  45 */
  46static void spr_load_dump_spr(int sprn)
  47{
  48#ifdef PPC_DUMP_SPR_ACCESSES
  49    TCGv_i32 t0 = tcg_const_i32(sprn);
  50    gen_helper_load_dump_spr(cpu_env, t0);
  51    tcg_temp_free_i32(t0);
  52#endif
  53}
  54
  55static void spr_read_generic (DisasContext *ctx, int gprn, int sprn)
  56{
  57    gen_load_spr(cpu_gpr[gprn], sprn);
  58    spr_load_dump_spr(sprn);
  59}
  60
  61static void spr_store_dump_spr(int sprn)
  62{
  63#ifdef PPC_DUMP_SPR_ACCESSES
  64    TCGv_i32 t0 = tcg_const_i32(sprn);
  65    gen_helper_store_dump_spr(cpu_env, t0);
  66    tcg_temp_free_i32(t0);
  67#endif
  68}
  69
  70static void spr_write_generic(DisasContext *ctx, int sprn, int gprn)
  71{
  72    gen_store_spr(sprn, cpu_gpr[gprn]);
  73    spr_store_dump_spr(sprn);
  74}
  75
  76#if !defined(CONFIG_USER_ONLY)
  77static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
  78{
  79#ifdef TARGET_PPC64
  80    TCGv t0 = tcg_temp_new();
  81    tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
  82    gen_store_spr(sprn, t0);
  83    tcg_temp_free(t0);
  84    spr_store_dump_spr(sprn);
  85#else
  86    spr_write_generic(ctx, sprn, gprn);
  87#endif
  88}
  89
  90static void spr_write_clear(DisasContext *ctx, int sprn, int gprn)
  91{
  92    TCGv t0 = tcg_temp_new();
  93    TCGv t1 = tcg_temp_new();
  94    gen_load_spr(t0, sprn);
  95    tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
  96    tcg_gen_and_tl(t0, t0, t1);
  97    gen_store_spr(sprn, t0);
  98    tcg_temp_free(t0);
  99    tcg_temp_free(t1);
 100}
 101
 102static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
 103{
 104}
 105
 106#endif
 107
 108/* SPR common to all PowerPC */
 109/* XER */
 110static void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
 111{
 112    gen_read_xer(ctx, cpu_gpr[gprn]);
 113}
 114
 115static void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
 116{
 117    gen_write_xer(cpu_gpr[gprn]);
 118}
 119
 120/* LR */
 121static void spr_read_lr(DisasContext *ctx, int gprn, int sprn)
 122{
 123    tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
 124}
 125
 126static void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
 127{
 128    tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
 129}
 130
 131/* CFAR */
 132#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
 133static void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
 134{
 135    tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
 136}
 137
 138static void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
 139{
 140    tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
 141}
 142#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
 143
 144/* CTR */
 145static void spr_read_ctr(DisasContext *ctx, int gprn, int sprn)
 146{
 147    tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
 148}
 149
 150static void spr_write_ctr(DisasContext *ctx, int sprn, int gprn)
 151{
 152    tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
 153}
 154
 155/* User read access to SPR */
 156/* USPRx */
 157/* UMMCRx */
 158/* UPMCx */
 159/* USIA */
 160/* UDECR */
 161static void spr_read_ureg(DisasContext *ctx, int gprn, int sprn)
 162{
 163    gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
 164}
 165
 166#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
 167static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
 168{
 169    gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
 170}
 171#endif
 172
 173/* SPR common to all non-embedded PowerPC */
 174/* DECR */
 175#if !defined(CONFIG_USER_ONLY)
 176static void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
 177{
 178    if (ctx->tb->cflags & CF_USE_ICOUNT) {
 179        gen_io_start();
 180    }
 181    gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
 182    if (ctx->tb->cflags & CF_USE_ICOUNT) {
 183        gen_io_end();
 184        gen_stop_exception(ctx);
 185    }
 186}
 187
 188static void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
 189{
 190    if (ctx->tb->cflags & CF_USE_ICOUNT) {
 191        gen_io_start();
 192    }
 193    gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
 194    if (ctx->tb->cflags & CF_USE_ICOUNT) {
 195        gen_io_end();
 196        gen_stop_exception(ctx);
 197    }
 198}
 199#endif
 200
 201/* SPR common to all non-embedded PowerPC, except 601 */
 202/* Time base */
 203static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
 204{
 205    if (ctx->tb->cflags & CF_USE_ICOUNT) {
 206        gen_io_start();
 207    }
 208    gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
 209    if (ctx->tb->cflags & CF_USE_ICOUNT) {
 210        gen_io_end();
 211        gen_stop_exception(ctx);
 212    }
 213}
 214
 215static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
 216{
 217    if (ctx->tb->cflags & CF_USE_ICOUNT) {
 218        gen_io_start();
 219    }
 220    gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
 221    if (ctx->tb->cflags & CF_USE_ICOUNT) {
 222        gen_io_end();
 223        gen_stop_exception(ctx);
 224    }
 225}
 226
 227__attribute__ (( unused ))
 228static void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
 229{
 230    gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
 231}
 232
 233__attribute__ (( unused ))
 234static void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
 235{
 236    gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
 237}
 238
 239#if !defined(CONFIG_USER_ONLY)
 240static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
 241{
 242    if (ctx->tb->cflags & CF_USE_ICOUNT) {
 243        gen_io_start();
 244    }
 245    gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
 246    if (ctx->tb->cflags & CF_USE_ICOUNT) {
 247        gen_io_end();
 248        gen_stop_exception(ctx);
 249    }
 250}
 251
 252static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
 253{
 254    if (ctx->tb->cflags & CF_USE_ICOUNT) {
 255        gen_io_start();
 256    }
 257    gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
 258    if (ctx->tb->cflags & CF_USE_ICOUNT) {
 259        gen_io_end();
 260        gen_stop_exception(ctx);
 261    }
 262}
 263
 264__attribute__ (( unused ))
 265static void spr_write_atbl(DisasContext *ctx, int sprn, int gprn)
 266{
 267    gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
 268}
 269
 270__attribute__ (( unused ))
 271static void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
 272{
 273    gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
 274}
 275
 276#if defined(TARGET_PPC64)
 277__attribute__ (( unused ))
 278static void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
 279{
 280    gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
 281}
 282
 283/* HDECR */
 284static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
 285{
 286    if (ctx->tb->cflags & CF_USE_ICOUNT) {
 287        gen_io_start();
 288    }
 289    gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
 290    if (ctx->tb->cflags & CF_USE_ICOUNT) {
 291        gen_io_end();
 292        gen_stop_exception(ctx);
 293    }
 294}
 295
 296static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
 297{
 298    if (ctx->tb->cflags & CF_USE_ICOUNT) {
 299        gen_io_start();
 300    }
 301    gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
 302    if (ctx->tb->cflags & CF_USE_ICOUNT) {
 303        gen_io_end();
 304        gen_stop_exception(ctx);
 305    }
 306}
 307
 308#endif
 309#endif
 310
 311#if !defined(CONFIG_USER_ONLY)
 312/* IBAT0U...IBAT0U */
 313/* IBAT0L...IBAT7L */
 314static void spr_read_ibat(DisasContext *ctx, int gprn, int sprn)
 315{
 316    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
 317}
 318
 319static void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
 320{
 321    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
 322}
 323
 324static void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
 325{
 326    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
 327    gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
 328    tcg_temp_free_i32(t0);
 329}
 330
 331static void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
 332{
 333    TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
 334    gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
 335    tcg_temp_free_i32(t0);
 336}
 337
 338static void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
 339{
 340    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
 341    gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
 342    tcg_temp_free_i32(t0);
 343}
 344
 345static void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
 346{
 347    TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
 348    gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
 349    tcg_temp_free_i32(t0);
 350}
 351
 352/* DBAT0U...DBAT7U */
 353/* DBAT0L...DBAT7L */
 354static void spr_read_dbat(DisasContext *ctx, int gprn, int sprn)
 355{
 356    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
 357}
 358
 359static void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
 360{
 361    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
 362}
 363
 364static void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
 365{
 366    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
 367    gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
 368    tcg_temp_free_i32(t0);
 369}
 370
 371static void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
 372{
 373    TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
 374    gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
 375    tcg_temp_free_i32(t0);
 376}
 377
 378static void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
 379{
 380    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
 381    gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
 382    tcg_temp_free_i32(t0);
 383}
 384
 385static void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
 386{
 387    TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
 388    gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
 389    tcg_temp_free_i32(t0);
 390}
 391
 392/* SDR1 */
 393static void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn)
 394{
 395    gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
 396}
 397
 398#if defined(TARGET_PPC64)
 399/* 64 bits PowerPC specific SPRs */
 400/* PIDR */
 401static void spr_write_pidr(DisasContext *ctx, int sprn, int gprn)
 402{
 403    gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]);
 404}
 405
 406static void spr_read_hior(DisasContext *ctx, int gprn, int sprn)
 407{
 408    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
 409}
 410
 411static void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
 412{
 413    TCGv t0 = tcg_temp_new();
 414    tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
 415    tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
 416    tcg_temp_free(t0);
 417}
 418#endif
 419#endif
 420
 421/* PowerPC 601 specific registers */
 422/* RTC */
 423static void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn)
 424{
 425    gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
 426}
 427
 428static void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn)
 429{
 430    gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
 431}
 432
 433#if !defined(CONFIG_USER_ONLY)
 434static void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn)
 435{
 436    gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
 437}
 438
 439static void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn)
 440{
 441    gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
 442}
 443
 444static void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn)
 445{
 446    gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
 447    /* Must stop the translation as endianness may have changed */
 448    gen_stop_exception(ctx);
 449}
 450#endif
 451
 452/* Unified bats */
 453#if !defined(CONFIG_USER_ONLY)
 454static void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn)
 455{
 456    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
 457}
 458
 459static void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn)
 460{
 461    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
 462    gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
 463    tcg_temp_free_i32(t0);
 464}
 465
 466static void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn)
 467{
 468    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
 469    gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
 470    tcg_temp_free_i32(t0);
 471}
 472#endif
 473
 474/* PowerPC 40x specific registers */
 475#if !defined(CONFIG_USER_ONLY)
 476static void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
 477{
 478    gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
 479}
 480
 481static void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
 482{
 483    gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
 484}
 485
 486static void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
 487{
 488    gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
 489    /* We must stop translation as we may have rebooted */
 490    gen_stop_exception(ctx);
 491}
 492
 493static void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
 494{
 495    gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
 496}
 497
 498static void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
 499{
 500    gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
 501}
 502
 503static void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
 504{
 505    gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
 506}
 507#endif
 508
 509/* PowerPC 403 specific registers */
 510/* PBL1 / PBU1 / PBL2 / PBU2 */
 511#if !defined(CONFIG_USER_ONLY)
 512static void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn)
 513{
 514    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
 515}
 516
 517static void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn)
 518{
 519    TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
 520    gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
 521    tcg_temp_free_i32(t0);
 522}
 523
 524static void spr_write_pir(DisasContext *ctx, int sprn, int gprn)
 525{
 526    TCGv t0 = tcg_temp_new();
 527    tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
 528    gen_store_spr(SPR_PIR, t0);
 529    tcg_temp_free(t0);
 530}
 531#endif
 532
 533/* SPE specific registers */
 534static void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn)
 535{
 536    TCGv_i32 t0 = tcg_temp_new_i32();
 537    tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
 538    tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
 539    tcg_temp_free_i32(t0);
 540}
 541
 542static void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn)
 543{
 544    TCGv_i32 t0 = tcg_temp_new_i32();
 545    tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
 546    tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
 547    tcg_temp_free_i32(t0);
 548}
 549
 550#if !defined(CONFIG_USER_ONLY)
 551/* Callback used to write the exception vector base */
 552static void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn)
 553{
 554    TCGv t0 = tcg_temp_new();
 555    tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
 556    tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
 557    tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
 558    gen_store_spr(sprn, t0);
 559    tcg_temp_free(t0);
 560}
 561
 562static void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
 563{
 564    int sprn_offs;
 565
 566    if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
 567        sprn_offs = sprn - SPR_BOOKE_IVOR0;
 568    } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
 569        sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
 570    } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
 571        sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
 572    } else {
 573        printf("Trying to write an unknown exception vector %d %03x\n",
 574               sprn, sprn);
 575        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
 576        return;
 577    }
 578
 579    TCGv t0 = tcg_temp_new();
 580    tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
 581    tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
 582    tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
 583    gen_store_spr(sprn, t0);
 584    tcg_temp_free(t0);
 585}
 586#endif
 587
 588static inline void vscr_init(CPUPPCState *env, uint32_t val)
 589{
 590    env->vscr = val;
 591    /* Altivec always uses round-to-nearest */
 592    set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
 593    set_flush_to_zero(vscr_nj, &env->vec_status);
 594}
 595
 596#ifdef CONFIG_USER_ONLY
 597#define spr_register_kvm(env, num, name, uea_read, uea_write,                  \
 598                         oea_read, oea_write, one_reg_id, initial_value)       \
 599    _spr_register(env, num, name, uea_read, uea_write, initial_value)
 600#define spr_register_kvm_hv(env, num, name, uea_read, uea_write,               \
 601                            oea_read, oea_write, hea_read, hea_write,          \
 602                            one_reg_id, initial_value)                         \
 603    _spr_register(env, num, name, uea_read, uea_write, initial_value)
 604#else
 605#if !defined(CONFIG_KVM)
 606#define spr_register_kvm(env, num, name, uea_read, uea_write,                  \
 607                         oea_read, oea_write, one_reg_id, initial_value)       \
 608    _spr_register(env, num, name, uea_read, uea_write,                         \
 609                  oea_read, oea_write, oea_read, oea_write, initial_value)
 610#define spr_register_kvm_hv(env, num, name, uea_read, uea_write,               \
 611                            oea_read, oea_write, hea_read, hea_write,          \
 612                            one_reg_id, initial_value)                         \
 613    _spr_register(env, num, name, uea_read, uea_write,                         \
 614                  oea_read, oea_write, hea_read, hea_write, initial_value)
 615#else
 616#define spr_register_kvm(env, num, name, uea_read, uea_write,                  \
 617                         oea_read, oea_write, one_reg_id, initial_value)       \
 618    _spr_register(env, num, name, uea_read, uea_write,                         \
 619                  oea_read, oea_write, oea_read, oea_write,                    \
 620                  one_reg_id, initial_value)
 621#define spr_register_kvm_hv(env, num, name, uea_read, uea_write,               \
 622                            oea_read, oea_write, hea_read, hea_write,          \
 623                            one_reg_id, initial_value)                         \
 624    _spr_register(env, num, name, uea_read, uea_write,                         \
 625                  oea_read, oea_write, hea_read, hea_write,                    \
 626                  one_reg_id, initial_value)
 627#endif
 628#endif
 629
 630#define spr_register(env, num, name, uea_read, uea_write,                      \
 631                     oea_read, oea_write, initial_value)                       \
 632    spr_register_kvm(env, num, name, uea_read, uea_write,                      \
 633                     oea_read, oea_write, 0, initial_value)
 634
 635#define spr_register_hv(env, num, name, uea_read, uea_write,                   \
 636                        oea_read, oea_write, hea_read, hea_write,              \
 637                        initial_value)                                         \
 638    spr_register_kvm_hv(env, num, name, uea_read, uea_write,                   \
 639                        oea_read, oea_write, hea_read, hea_write,              \
 640                        0, initial_value)
 641
 642static inline void _spr_register(CPUPPCState *env, int num,
 643                                 const char *name,
 644                                 void (*uea_read)(DisasContext *ctx, int gprn, int sprn),
 645                                 void (*uea_write)(DisasContext *ctx, int sprn, int gprn),
 646#if !defined(CONFIG_USER_ONLY)
 647
 648                                 void (*oea_read)(DisasContext *ctx, int gprn, int sprn),
 649                                 void (*oea_write)(DisasContext *ctx, int sprn, int gprn),
 650                                 void (*hea_read)(DisasContext *opaque, int gprn, int sprn),
 651                                 void (*hea_write)(DisasContext *opaque, int sprn, int gprn),
 652#endif
 653#if defined(CONFIG_KVM)
 654                                 uint64_t one_reg_id,
 655#endif
 656                                 target_ulong initial_value)
 657{
 658    ppc_spr_t *spr;
 659
 660    spr = &env->spr_cb[num];
 661    if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
 662#if !defined(CONFIG_USER_ONLY)
 663        spr->oea_read != NULL || spr->oea_write != NULL ||
 664#endif
 665        spr->uea_read != NULL || spr->uea_write != NULL) {
 666        printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
 667        exit(1);
 668    }
 669#if defined(PPC_DEBUG_SPR)
 670    printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
 671           name, initial_value);
 672#endif
 673    spr->name = name;
 674    spr->uea_read = uea_read;
 675    spr->uea_write = uea_write;
 676#if !defined(CONFIG_USER_ONLY)
 677    spr->oea_read = oea_read;
 678    spr->oea_write = oea_write;
 679    spr->hea_read = hea_read;
 680    spr->hea_write = hea_write;
 681#endif
 682#if defined(CONFIG_KVM)
 683    spr->one_reg_id = one_reg_id,
 684#endif
 685    env->spr[num] = spr->default_value = initial_value;
 686}
 687
 688/* Generic PowerPC SPRs */
 689static void gen_spr_generic(CPUPPCState *env)
 690{
 691    /* Integer processing */
 692    spr_register(env, SPR_XER, "XER",
 693                 &spr_read_xer, &spr_write_xer,
 694                 &spr_read_xer, &spr_write_xer,
 695                 0x00000000);
 696    /* Branch contol */
 697    spr_register(env, SPR_LR, "LR",
 698                 &spr_read_lr, &spr_write_lr,
 699                 &spr_read_lr, &spr_write_lr,
 700                 0x00000000);
 701    spr_register(env, SPR_CTR, "CTR",
 702                 &spr_read_ctr, &spr_write_ctr,
 703                 &spr_read_ctr, &spr_write_ctr,
 704                 0x00000000);
 705    /* Interrupt processing */
 706    spr_register(env, SPR_SRR0, "SRR0",
 707                 SPR_NOACCESS, SPR_NOACCESS,
 708                 &spr_read_generic, &spr_write_generic,
 709                 0x00000000);
 710    spr_register(env, SPR_SRR1, "SRR1",
 711                 SPR_NOACCESS, SPR_NOACCESS,
 712                 &spr_read_generic, &spr_write_generic,
 713                 0x00000000);
 714    /* Processor control */
 715    spr_register(env, SPR_SPRG0, "SPRG0",
 716                 SPR_NOACCESS, SPR_NOACCESS,
 717                 &spr_read_generic, &spr_write_generic,
 718                 0x00000000);
 719    spr_register(env, SPR_SPRG1, "SPRG1",
 720                 SPR_NOACCESS, SPR_NOACCESS,
 721                 &spr_read_generic, &spr_write_generic,
 722                 0x00000000);
 723    spr_register(env, SPR_SPRG2, "SPRG2",
 724                 SPR_NOACCESS, SPR_NOACCESS,
 725                 &spr_read_generic, &spr_write_generic,
 726                 0x00000000);
 727    spr_register(env, SPR_SPRG3, "SPRG3",
 728                 SPR_NOACCESS, SPR_NOACCESS,
 729                 &spr_read_generic, &spr_write_generic,
 730                 0x00000000);
 731}
 732
 733/* SPR common to all non-embedded PowerPC, including 601 */
 734static void gen_spr_ne_601(CPUPPCState *env)
 735{
 736    /* Exception processing */
 737    spr_register_kvm(env, SPR_DSISR, "DSISR",
 738                     SPR_NOACCESS, SPR_NOACCESS,
 739                     &spr_read_generic, &spr_write_generic,
 740                     KVM_REG_PPC_DSISR, 0x00000000);
 741    spr_register_kvm(env, SPR_DAR, "DAR",
 742                     SPR_NOACCESS, SPR_NOACCESS,
 743                     &spr_read_generic, &spr_write_generic,
 744                     KVM_REG_PPC_DAR, 0x00000000);
 745    /* Timer */
 746    spr_register(env, SPR_DECR, "DECR",
 747                 SPR_NOACCESS, SPR_NOACCESS,
 748                 &spr_read_decr, &spr_write_decr,
 749                 0x00000000);
 750}
 751
 752/* Storage Description Register 1 */
 753static void gen_spr_sdr1(CPUPPCState *env)
 754{
 755#ifndef CONFIG_USER_ONLY
 756    if (env->has_hv_mode) {
 757        /* SDR1 is a hypervisor resource on CPUs which have a
 758         * hypervisor mode */
 759        spr_register_hv(env, SPR_SDR1, "SDR1",
 760                        SPR_NOACCESS, SPR_NOACCESS,
 761                        SPR_NOACCESS, SPR_NOACCESS,
 762                        &spr_read_generic, &spr_write_sdr1,
 763                        0x00000000);
 764    } else {
 765        spr_register(env, SPR_SDR1, "SDR1",
 766                     SPR_NOACCESS, SPR_NOACCESS,
 767                     &spr_read_generic, &spr_write_sdr1,
 768                     0x00000000);
 769    }
 770#endif
 771}
 772
 773/* BATs 0-3 */
 774static void gen_low_BATs(CPUPPCState *env)
 775{
 776#if !defined(CONFIG_USER_ONLY)
 777    spr_register(env, SPR_IBAT0U, "IBAT0U",
 778                 SPR_NOACCESS, SPR_NOACCESS,
 779                 &spr_read_ibat, &spr_write_ibatu,
 780                 0x00000000);
 781    spr_register(env, SPR_IBAT0L, "IBAT0L",
 782                 SPR_NOACCESS, SPR_NOACCESS,
 783                 &spr_read_ibat, &spr_write_ibatl,
 784                 0x00000000);
 785    spr_register(env, SPR_IBAT1U, "IBAT1U",
 786                 SPR_NOACCESS, SPR_NOACCESS,
 787                 &spr_read_ibat, &spr_write_ibatu,
 788                 0x00000000);
 789    spr_register(env, SPR_IBAT1L, "IBAT1L",
 790                 SPR_NOACCESS, SPR_NOACCESS,
 791                 &spr_read_ibat, &spr_write_ibatl,
 792                 0x00000000);
 793    spr_register(env, SPR_IBAT2U, "IBAT2U",
 794                 SPR_NOACCESS, SPR_NOACCESS,
 795                 &spr_read_ibat, &spr_write_ibatu,
 796                 0x00000000);
 797    spr_register(env, SPR_IBAT2L, "IBAT2L",
 798                 SPR_NOACCESS, SPR_NOACCESS,
 799                 &spr_read_ibat, &spr_write_ibatl,
 800                 0x00000000);
 801    spr_register(env, SPR_IBAT3U, "IBAT3U",
 802                 SPR_NOACCESS, SPR_NOACCESS,
 803                 &spr_read_ibat, &spr_write_ibatu,
 804                 0x00000000);
 805    spr_register(env, SPR_IBAT3L, "IBAT3L",
 806                 SPR_NOACCESS, SPR_NOACCESS,
 807                 &spr_read_ibat, &spr_write_ibatl,
 808                 0x00000000);
 809    spr_register(env, SPR_DBAT0U, "DBAT0U",
 810                 SPR_NOACCESS, SPR_NOACCESS,
 811                 &spr_read_dbat, &spr_write_dbatu,
 812                 0x00000000);
 813    spr_register(env, SPR_DBAT0L, "DBAT0L",
 814                 SPR_NOACCESS, SPR_NOACCESS,
 815                 &spr_read_dbat, &spr_write_dbatl,
 816                 0x00000000);
 817    spr_register(env, SPR_DBAT1U, "DBAT1U",
 818                 SPR_NOACCESS, SPR_NOACCESS,
 819                 &spr_read_dbat, &spr_write_dbatu,
 820                 0x00000000);
 821    spr_register(env, SPR_DBAT1L, "DBAT1L",
 822                 SPR_NOACCESS, SPR_NOACCESS,
 823                 &spr_read_dbat, &spr_write_dbatl,
 824                 0x00000000);
 825    spr_register(env, SPR_DBAT2U, "DBAT2U",
 826                 SPR_NOACCESS, SPR_NOACCESS,
 827                 &spr_read_dbat, &spr_write_dbatu,
 828                 0x00000000);
 829    spr_register(env, SPR_DBAT2L, "DBAT2L",
 830                 SPR_NOACCESS, SPR_NOACCESS,
 831                 &spr_read_dbat, &spr_write_dbatl,
 832                 0x00000000);
 833    spr_register(env, SPR_DBAT3U, "DBAT3U",
 834                 SPR_NOACCESS, SPR_NOACCESS,
 835                 &spr_read_dbat, &spr_write_dbatu,
 836                 0x00000000);
 837    spr_register(env, SPR_DBAT3L, "DBAT3L",
 838                 SPR_NOACCESS, SPR_NOACCESS,
 839                 &spr_read_dbat, &spr_write_dbatl,
 840                 0x00000000);
 841    env->nb_BATs += 4;
 842#endif
 843}
 844
 845/* BATs 4-7 */
 846static void gen_high_BATs(CPUPPCState *env)
 847{
 848#if !defined(CONFIG_USER_ONLY)
 849    spr_register(env, SPR_IBAT4U, "IBAT4U",
 850                 SPR_NOACCESS, SPR_NOACCESS,
 851                 &spr_read_ibat_h, &spr_write_ibatu_h,
 852                 0x00000000);
 853    spr_register(env, SPR_IBAT4L, "IBAT4L",
 854                 SPR_NOACCESS, SPR_NOACCESS,
 855                 &spr_read_ibat_h, &spr_write_ibatl_h,
 856                 0x00000000);
 857    spr_register(env, SPR_IBAT5U, "IBAT5U",
 858                 SPR_NOACCESS, SPR_NOACCESS,
 859                 &spr_read_ibat_h, &spr_write_ibatu_h,
 860                 0x00000000);
 861    spr_register(env, SPR_IBAT5L, "IBAT5L",
 862                 SPR_NOACCESS, SPR_NOACCESS,
 863                 &spr_read_ibat_h, &spr_write_ibatl_h,
 864                 0x00000000);
 865    spr_register(env, SPR_IBAT6U, "IBAT6U",
 866                 SPR_NOACCESS, SPR_NOACCESS,
 867                 &spr_read_ibat_h, &spr_write_ibatu_h,
 868                 0x00000000);
 869    spr_register(env, SPR_IBAT6L, "IBAT6L",
 870                 SPR_NOACCESS, SPR_NOACCESS,
 871                 &spr_read_ibat_h, &spr_write_ibatl_h,
 872                 0x00000000);
 873    spr_register(env, SPR_IBAT7U, "IBAT7U",
 874                 SPR_NOACCESS, SPR_NOACCESS,
 875                 &spr_read_ibat_h, &spr_write_ibatu_h,
 876                 0x00000000);
 877    spr_register(env, SPR_IBAT7L, "IBAT7L",
 878                 SPR_NOACCESS, SPR_NOACCESS,
 879                 &spr_read_ibat_h, &spr_write_ibatl_h,
 880                 0x00000000);
 881    spr_register(env, SPR_DBAT4U, "DBAT4U",
 882                 SPR_NOACCESS, SPR_NOACCESS,
 883                 &spr_read_dbat_h, &spr_write_dbatu_h,
 884                 0x00000000);
 885    spr_register(env, SPR_DBAT4L, "DBAT4L",
 886                 SPR_NOACCESS, SPR_NOACCESS,
 887                 &spr_read_dbat_h, &spr_write_dbatl_h,
 888                 0x00000000);
 889    spr_register(env, SPR_DBAT5U, "DBAT5U",
 890                 SPR_NOACCESS, SPR_NOACCESS,
 891                 &spr_read_dbat_h, &spr_write_dbatu_h,
 892                 0x00000000);
 893    spr_register(env, SPR_DBAT5L, "DBAT5L",
 894                 SPR_NOACCESS, SPR_NOACCESS,
 895                 &spr_read_dbat_h, &spr_write_dbatl_h,
 896                 0x00000000);
 897    spr_register(env, SPR_DBAT6U, "DBAT6U",
 898                 SPR_NOACCESS, SPR_NOACCESS,
 899                 &spr_read_dbat_h, &spr_write_dbatu_h,
 900                 0x00000000);
 901    spr_register(env, SPR_DBAT6L, "DBAT6L",
 902                 SPR_NOACCESS, SPR_NOACCESS,
 903                 &spr_read_dbat_h, &spr_write_dbatl_h,
 904                 0x00000000);
 905    spr_register(env, SPR_DBAT7U, "DBAT7U",
 906                 SPR_NOACCESS, SPR_NOACCESS,
 907                 &spr_read_dbat_h, &spr_write_dbatu_h,
 908                 0x00000000);
 909    spr_register(env, SPR_DBAT7L, "DBAT7L",
 910                 SPR_NOACCESS, SPR_NOACCESS,
 911                 &spr_read_dbat_h, &spr_write_dbatl_h,
 912                 0x00000000);
 913    env->nb_BATs += 4;
 914#endif
 915}
 916
 917/* Generic PowerPC time base */
 918static void gen_tbl(CPUPPCState *env)
 919{
 920    spr_register(env, SPR_VTBL,  "TBL",
 921                 &spr_read_tbl, SPR_NOACCESS,
 922                 &spr_read_tbl, SPR_NOACCESS,
 923                 0x00000000);
 924    spr_register(env, SPR_TBL,   "TBL",
 925                 &spr_read_tbl, SPR_NOACCESS,
 926                 &spr_read_tbl, &spr_write_tbl,
 927                 0x00000000);
 928    spr_register(env, SPR_VTBU,  "TBU",
 929                 &spr_read_tbu, SPR_NOACCESS,
 930                 &spr_read_tbu, SPR_NOACCESS,
 931                 0x00000000);
 932    spr_register(env, SPR_TBU,   "TBU",
 933                 &spr_read_tbu, SPR_NOACCESS,
 934                 &spr_read_tbu, &spr_write_tbu,
 935                 0x00000000);
 936}
 937
 938/* Softare table search registers */
 939static void gen_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
 940{
 941#if !defined(CONFIG_USER_ONLY)
 942    env->nb_tlb = nb_tlbs;
 943    env->nb_ways = nb_ways;
 944    env->id_tlbs = 1;
 945    env->tlb_type = TLB_6XX;
 946    spr_register(env, SPR_DMISS, "DMISS",
 947                 SPR_NOACCESS, SPR_NOACCESS,
 948                 &spr_read_generic, SPR_NOACCESS,
 949                 0x00000000);
 950    spr_register(env, SPR_DCMP, "DCMP",
 951                 SPR_NOACCESS, SPR_NOACCESS,
 952                 &spr_read_generic, SPR_NOACCESS,
 953                 0x00000000);
 954    spr_register(env, SPR_HASH1, "HASH1",
 955                 SPR_NOACCESS, SPR_NOACCESS,
 956                 &spr_read_generic, SPR_NOACCESS,
 957                 0x00000000);
 958    spr_register(env, SPR_HASH2, "HASH2",
 959                 SPR_NOACCESS, SPR_NOACCESS,
 960                 &spr_read_generic, SPR_NOACCESS,
 961                 0x00000000);
 962    spr_register(env, SPR_IMISS, "IMISS",
 963                 SPR_NOACCESS, SPR_NOACCESS,
 964                 &spr_read_generic, SPR_NOACCESS,
 965                 0x00000000);
 966    spr_register(env, SPR_ICMP, "ICMP",
 967                 SPR_NOACCESS, SPR_NOACCESS,
 968                 &spr_read_generic, SPR_NOACCESS,
 969                 0x00000000);
 970    spr_register(env, SPR_RPA, "RPA",
 971                 SPR_NOACCESS, SPR_NOACCESS,
 972                 &spr_read_generic, &spr_write_generic,
 973                 0x00000000);
 974#endif
 975}
 976
 977/* SPR common to MPC755 and G2 */
 978static void gen_spr_G2_755(CPUPPCState *env)
 979{
 980    /* SGPRs */
 981    spr_register(env, SPR_SPRG4, "SPRG4",
 982                 SPR_NOACCESS, SPR_NOACCESS,
 983                 &spr_read_generic, &spr_write_generic,
 984                 0x00000000);
 985    spr_register(env, SPR_SPRG5, "SPRG5",
 986                 SPR_NOACCESS, SPR_NOACCESS,
 987                 &spr_read_generic, &spr_write_generic,
 988                 0x00000000);
 989    spr_register(env, SPR_SPRG6, "SPRG6",
 990                 SPR_NOACCESS, SPR_NOACCESS,
 991                 &spr_read_generic, &spr_write_generic,
 992                 0x00000000);
 993    spr_register(env, SPR_SPRG7, "SPRG7",
 994                 SPR_NOACCESS, SPR_NOACCESS,
 995                 &spr_read_generic, &spr_write_generic,
 996                 0x00000000);
 997}
 998
 999/* SPR common to all 7xx PowerPC implementations */
1000static void gen_spr_7xx(CPUPPCState *env)

1001{
1002    /* Breakpoints */
1003    /* XXX : not implemented */
1004    spr_register_kvm(env, SPR_DABR, "DABR",
1005                     SPR_NOACCESS, SPR_NOACCESS,
1006                     &spr_read_generic, &spr_write_generic,
1007                     KVM_REG_PPC_DABR, 0x00000000);
1008    /* XXX : not implemented */
1009    spr_register(env, SPR_IABR, "IABR",
1010                 SPR_NOACCESS, SPR_NOACCESS,
1011                 &spr_read_generic, &spr_write_generic,
1012                 0x00000000);
1013    /* Cache management */
1014    /* XXX : not implemented */
1015    spr_register(env, SPR_ICTC, "ICTC",
1016                 SPR_NOACCESS, SPR_NOACCESS,
1017                 &spr_read_generic, &spr_write_generic,
1018                 0x00000000);
1019    /* Performance monitors */
1020    /* XXX : not implemented */
1021    spr_register(env, SPR_7XX_MMCR0, "MMCR0",
1022                 SPR_NOACCESS, SPR_NOACCESS,
1023                 &spr_read_generic, &spr_write_generic,
1024                 0x00000000);
1025    /* XXX : not implemented */
1026    spr_register(env, SPR_7XX_MMCR1, "MMCR1",
1027                 SPR_NOACCESS, SPR_NOACCESS,
1028                 &spr_read_generic, &spr_write_generic,
1029                 0x00000000);
1030    /* XXX : not implemented */
1031    spr_register(env, SPR_7XX_PMC1, "PMC1",
1032                 SPR_NOACCESS, SPR_NOACCESS,
1033                 &spr_read_generic, &spr_write_generic,
1034                 0x00000000);
1035    /* XXX : not implemented */
1036    spr_register(env, SPR_7XX_PMC2, "PMC2",
1037                 SPR_NOACCESS, SPR_NOACCESS,
1038                 &spr_read_generic, &spr_write_generic,
1039                 0x00000000);
1040    /* XXX : not implemented */
1041    spr_register(env, SPR_7XX_PMC3, "PMC3",
1042                 SPR_NOACCESS, SPR_NOACCESS,
1043                 &spr_read_generic, &spr_write_generic,
1044                 0x00000000);
1045    /* XXX : not implemented */
1046    spr_register(env, SPR_7XX_PMC4, "PMC4",
1047                 SPR_NOACCESS, SPR_NOACCESS,
1048                 &spr_read_generic, &spr_write_generic,
1049                 0x00000000);
1050    /* XXX : not implemented */
1051    spr_register(env, SPR_7XX_SIAR, "SIAR",
1052                 SPR_NOACCESS, SPR_NOACCESS,
1053                 &spr_read_generic, SPR_NOACCESS,
1054                 0x00000000);
1055    /* XXX : not implemented */
1056    spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
1057                 &spr_read_ureg, SPR_NOACCESS,
1058                 &spr_read_ureg, SPR_NOACCESS,
1059                 0x00000000);
1060    /* XXX : not implemented */
1061    spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
1062                 &spr_read_ureg, SPR_NOACCESS,
1063                 &spr_read_ureg, SPR_NOACCESS,
1064                 0x00000000);
1065    /* XXX : not implemented */
1066    spr_register(env, SPR_7XX_UPMC1, "UPMC1",
1067                 &spr_read_ureg, SPR_NOACCESS,
1068                 &spr_read_ureg, SPR_NOACCESS,
1069                 0x00000000);
1070    /* XXX : not implemented */
1071    spr_register(env, SPR_7XX_UPMC2, "UPMC2",
1072                 &spr_read_ureg, SPR_NOACCESS,
1073                 &spr_read_ureg, SPR_NOACCESS,
1074                 0x00000000);
1075    /* XXX : not implemented */
1076    spr_register(env, SPR_7XX_UPMC3, "UPMC3",
1077                 &spr_read_ureg, SPR_NOACCESS,
1078                 &spr_read_ureg, SPR_NOACCESS,
1079                 0x00000000);
1080    /* XXX : not implemented */
1081    spr_register(env, SPR_7XX_UPMC4, "UPMC4",
1082                 &spr_read_ureg, SPR_NOACCESS,
1083                 &spr_read_ureg, SPR_NOACCESS,
1084                 0x00000000);
1085    /* XXX : not implemented */
1086    spr_register(env, SPR_7XX_USIAR, "USIAR",
1087                 &spr_read_ureg, SPR_NOACCESS,
1088                 &spr_read_ureg, SPR_NOACCESS,
1089                 0x00000000);
1090    /* External access control */
1091    /* XXX : not implemented */
1092    spr_register(env, SPR_EAR, "EAR",
1093                 SPR_NOACCESS, SPR_NOACCESS,
1094                 &spr_read_generic, &spr_write_generic,
1095                 0x00000000);
1096}
1097
1098#ifdef TARGET_PPC64
1099#ifndef CONFIG_USER_ONLY
1100static void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
1101{
1102    TCGv t0 = tcg_temp_new();
1103    TCGv t1 = tcg_temp_new();
1104    TCGv t2 = tcg_temp_new();
1105
1106    /* Note, the HV=1 PR=0 case is handled earlier by simply using
1107     * spr_write_generic for HV mode in the SPR table
1108     */
1109
1110    /* Build insertion mask into t1 based on context */
1111    if (ctx->pr) {
1112        gen_load_spr(t1, SPR_UAMOR);
1113    } else {
1114        gen_load_spr(t1, SPR_AMOR);
1115    }
1116
1117    /* Mask new bits into t2 */
1118    tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1119
1120    /* Load AMR and clear new bits in t0 */
1121    gen_load_spr(t0, SPR_AMR);
1122    tcg_gen_andc_tl(t0, t0, t1);
1123
1124    /* Or'in new bits and write it out */
1125    tcg_gen_or_tl(t0, t0, t2);
1126    gen_store_spr(SPR_AMR, t0);
1127    spr_store_dump_spr(SPR_AMR);
1128
1129    tcg_temp_free(t0);
1130    tcg_temp_free(t1);
1131    tcg_temp_free(t2);
1132}
1133
1134static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
1135{
1136    TCGv t0 = tcg_temp_new();
1137    TCGv t1 = tcg_temp_new();
1138    TCGv t2 = tcg_temp_new();
1139
1140    /* Note, the HV=1 case is handled earlier by simply using
1141     * spr_write_generic for HV mode in the SPR table
1142     */
1143
1144    /* Build insertion mask into t1 based on context */
1145    gen_load_spr(t1, SPR_AMOR);
1146
1147    /* Mask new bits into t2 */
1148    tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1149
1150    /* Load AMR and clear new bits in t0 */
1151    gen_load_spr(t0, SPR_UAMOR);
1152    tcg_gen_andc_tl(t0, t0, t1);
1153
1154    /* Or'in new bits and write it out */
1155    tcg_gen_or_tl(t0, t0, t2);
1156    gen_store_spr(SPR_UAMOR, t0);
1157    spr_store_dump_spr(SPR_UAMOR);
1158
1159    tcg_temp_free(t0);
1160    tcg_temp_free(t1);
1161    tcg_temp_free(t2);
1162}
1163
1164static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
1165{
1166    TCGv t0 = tcg_temp_new();
1167    TCGv t1 = tcg_temp_new();
1168    TCGv t2 = tcg_temp_new();
1169
1170    /* Note, the HV=1 case is handled earlier by simply using
1171     * spr_write_generic for HV mode in the SPR table
1172     */
1173
1174    /* Build insertion mask into t1 based on context */
1175    gen_load_spr(t1, SPR_AMOR);
1176
1177    /* Mask new bits into t2 */
1178    tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1179
1180    /* Load AMR and clear new bits in t0 */
1181    gen_load_spr(t0, SPR_IAMR);
1182    tcg_gen_andc_tl(t0, t0, t1);
1183
1184    /* Or'in new bits and write it out */
1185    tcg_gen_or_tl(t0, t0, t2);
1186    gen_store_spr(SPR_IAMR, t0);
1187    spr_store_dump_spr(SPR_IAMR);
1188
1189    tcg_temp_free(t0);
1190    tcg_temp_free(t1);
1191    tcg_temp_free(t2);
1192}
1193#endif /* CONFIG_USER_ONLY */
1194
1195static void gen_spr_amr(CPUPPCState *env)
1196{
1197#ifndef CONFIG_USER_ONLY
1198    /* Virtual Page Class Key protection */
1199    /* The AMR is accessible either via SPR 13 or SPR 29.  13 is
1200     * userspace accessible, 29 is privileged.  So we only need to set
1201     * the kvm ONE_REG id on one of them, we use 29 */
1202    spr_register(env, SPR_UAMR, "UAMR",
1203                 &spr_read_generic, &spr_write_amr,
1204                 &spr_read_generic, &spr_write_amr,
1205                 0);
1206    spr_register_kvm_hv(env, SPR_AMR, "AMR",
1207                     SPR_NOACCESS, SPR_NOACCESS,
1208                     &spr_read_generic, &spr_write_amr,
1209                     &spr_read_generic, &spr_write_generic,
1210                     KVM_REG_PPC_AMR, 0);
1211    spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
1212                     SPR_NOACCESS, SPR_NOACCESS,
1213                     &spr_read_generic, &spr_write_uamor,
1214                     &spr_read_generic, &spr_write_generic,
1215                     KVM_REG_PPC_UAMOR, 0);
1216    spr_register_hv(env, SPR_AMOR, "AMOR",
1217                    SPR_NOACCESS, SPR_NOACCESS,
1218                    SPR_NOACCESS, SPR_NOACCESS,
1219                    &spr_read_generic, &spr_write_generic,
1220                    0);
1221#endif /* !CONFIG_USER_ONLY */
1222}
1223
1224static void gen_spr_iamr(CPUPPCState *env)
1225{
1226#ifndef CONFIG_USER_ONLY
1227    spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
1228                        SPR_NOACCESS, SPR_NOACCESS,
1229                        &spr_read_generic, &spr_write_iamr,
1230                        &spr_read_generic, &spr_write_generic,
1231                        KVM_REG_PPC_IAMR, 0);
1232#endif /* !CONFIG_USER_ONLY */
1233}
1234#endif /* TARGET_PPC64 */
1235
1236#ifndef CONFIG_USER_ONLY
1237static void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
1238{
1239    gen_helper_fixup_thrm(cpu_env);
1240    gen_load_spr(cpu_gpr[gprn], sprn);
1241    spr_load_dump_spr(sprn);
1242}
1243#endif /* !CONFIG_USER_ONLY */
1244
1245static void gen_spr_thrm(CPUPPCState *env)
1246{
1247    /* Thermal management */
1248    /* XXX : not implemented */
1249    spr_register(env, SPR_THRM1, "THRM1",
1250                 SPR_NOACCESS, SPR_NOACCESS,
1251                 &spr_read_thrm, &spr_write_generic,
1252                 0x00000000);
1253    /* XXX : not implemented */
1254    spr_register(env, SPR_THRM2, "THRM2",
1255                 SPR_NOACCESS, SPR_NOACCESS,
1256                 &spr_read_thrm, &spr_write_generic,
1257                 0x00000000);
1258    /* XXX : not implemented */
1259    spr_register(env, SPR_THRM3, "THRM3",
1260                 SPR_NOACCESS, SPR_NOACCESS,
1261                 &spr_read_thrm, &spr_write_generic,
1262                 0x00000000);
1263}
1264
1265/* SPR specific to PowerPC 604 implementation */
1266static void gen_spr_604(CPUPPCState *env)
1267{
1268    /* Processor identification */
1269    spr_register(env, SPR_PIR, "PIR",
1270                 SPR_NOACCESS, SPR_NOACCESS,
1271                 &spr_read_generic, &spr_write_pir,
1272                 0x00000000);
1273    /* Breakpoints */
1274    /* XXX : not implemented */
1275    spr_register(env, SPR_IABR, "IABR",
1276                 SPR_NOACCESS, SPR_NOACCESS,
1277                 &spr_read_generic, &spr_write_generic,
1278                 0x00000000);
1279    /* XXX : not implemented */
1280    spr_register_kvm(env, SPR_DABR, "DABR",
1281                     SPR_NOACCESS, SPR_NOACCESS,
1282                     &spr_read_generic, &spr_write_generic,
1283                     KVM_REG_PPC_DABR, 0x00000000);
1284    /* Performance counters */
1285    /* XXX : not implemented */
1286    spr_register(env, SPR_7XX_MMCR0, "MMCR0",
1287                 SPR_NOACCESS, SPR_NOACCESS,
1288                 &spr_read_generic, &spr_write_generic,
1289                 0x00000000);
1290    /* XXX : not implemented */
1291    spr_register(env, SPR_7XX_PMC1, "PMC1",
1292                 SPR_NOACCESS, SPR_NOACCESS,
1293                 &spr_read_generic, &spr_write_generic,
1294                 0x00000000);
1295    /* XXX : not implemented */
1296    spr_register(env, SPR_7XX_PMC2, "PMC2",
1297                 SPR_NOACCESS, SPR_NOACCESS,
1298                 &spr_read_generic, &spr_write_generic,
1299                 0x00000000);
1300    /* XXX : not implemented */
1301    spr_register(env, SPR_7XX_SIAR, "SIAR",
1302                 SPR_NOACCESS, SPR_NOACCESS,
1303                 &spr_read_generic, SPR_NOACCESS,
1304                 0x00000000);
1305    /* XXX : not implemented */
1306    spr_register(env, SPR_SDA, "SDA",
1307                 SPR_NOACCESS, SPR_NOACCESS,
1308                 &spr_read_generic, SPR_NOACCESS,
1309                 0x00000000);
1310    /* External access control */
1311    /* XXX : not implemented */
1312    spr_register(env, SPR_EAR, "EAR",
1313                 SPR_NOACCESS, SPR_NOACCESS,
1314                 &spr_read_generic, &spr_write_generic,
1315                 0x00000000);
1316}
1317
1318/* SPR specific to PowerPC 603 implementation */
1319static void gen_spr_603(CPUPPCState *env)
1320{
1321    /* External access control */
1322    /* XXX : not implemented */
1323    spr_register(env, SPR_EAR, "EAR",
1324                 SPR_NOACCESS, SPR_NOACCESS,
1325                 &spr_read_generic, &spr_write_generic,
1326                 0x00000000);
1327    /* Breakpoints */
1328    /* XXX : not implemented */
1329    spr_register(env, SPR_IABR, "IABR",
1330                 SPR_NOACCESS, SPR_NOACCESS,
1331                 &spr_read_generic, &spr_write_generic,
1332                 0x00000000);
1333
1334}
1335
1336/* SPR specific to PowerPC G2 implementation */
1337static void gen_spr_G2(CPUPPCState *env)
1338{
1339    /* Memory base address */
1340    /* MBAR */
1341    /* XXX : not implemented */
1342    spr_register(env, SPR_MBAR, "MBAR",
1343                 SPR_NOACCESS, SPR_NOACCESS,
1344                 &spr_read_generic, &spr_write_generic,
1345                 0x00000000);
1346    /* Exception processing */
1347    spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1348                 SPR_NOACCESS, SPR_NOACCESS,
1349                 &spr_read_generic, &spr_write_generic,
1350                 0x00000000);
1351    spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1352                 SPR_NOACCESS, SPR_NOACCESS,
1353                 &spr_read_generic, &spr_write_generic,
1354                 0x00000000);
1355    /* Breakpoints */
1356    /* XXX : not implemented */
1357    spr_register(env, SPR_DABR, "DABR",
1358                 SPR_NOACCESS, SPR_NOACCESS,
1359                 &spr_read_generic, &spr_write_generic,
1360                 0x00000000);
1361    /* XXX : not implemented */
1362    spr_register(env, SPR_DABR2, "DABR2",
1363                 SPR_NOACCESS, SPR_NOACCESS,
1364                 &spr_read_generic, &spr_write_generic,
1365                 0x00000000);
1366    /* XXX : not implemented */
1367    spr_register(env, SPR_IABR, "IABR",
1368                 SPR_NOACCESS, SPR_NOACCESS,
1369                 &spr_read_generic, &spr_write_generic,
1370                 0x00000000);
1371    /* XXX : not implemented */
1372    spr_register(env, SPR_IABR2, "IABR2",
1373                 SPR_NOACCESS, SPR_NOACCESS,
1374                 &spr_read_generic, &spr_write_generic,
1375                 0x00000000);
1376    /* XXX : not implemented */
1377    spr_register(env, SPR_IBCR, "IBCR",
1378                 SPR_NOACCESS, SPR_NOACCESS,
1379                 &spr_read_generic, &spr_write_generic,
1380                 0x00000000);
1381    /* XXX : not implemented */
1382    spr_register(env, SPR_DBCR, "DBCR",
1383                 SPR_NOACCESS, SPR_NOACCESS,
1384                 &spr_read_generic, &spr_write_generic,
1385                 0x00000000);
1386}
1387
1388/* SPR specific to PowerPC 602 implementation */
1389static void gen_spr_602(CPUPPCState *env)
1390{
1391    /* ESA registers */
1392    /* XXX : not implemented */
1393    spr_register(env, SPR_SER, "SER",
1394                 SPR_NOACCESS, SPR_NOACCESS,
1395                 &spr_read_generic, &spr_write_generic,
1396                 0x00000000);
1397    /* XXX : not implemented */
1398    spr_register(env, SPR_SEBR, "SEBR",
1399                 SPR_NOACCESS, SPR_NOACCESS,
1400                 &spr_read_generic, &spr_write_generic,
1401                 0x00000000);
1402    /* XXX : not implemented */
1403    spr_register(env, SPR_ESASRR, "ESASRR",
1404                 SPR_NOACCESS, SPR_NOACCESS,
1405                 &spr_read_generic, &spr_write_generic,
1406                 0x00000000);
1407    /* Floating point status */
1408    /* XXX : not implemented */
1409    spr_register(env, SPR_SP, "SP",
1410                 SPR_NOACCESS, SPR_NOACCESS,
1411                 &spr_read_generic, &spr_write_generic,
1412                 0x00000000);
1413    /* XXX : not implemented */
1414    spr_register(env, SPR_LT, "LT",
1415                 SPR_NOACCESS, SPR_NOACCESS,
1416                 &spr_read_generic, &spr_write_generic,
1417                 0x00000000);
1418    /* Watchdog timer */
1419    /* XXX : not implemented */
1420    spr_register(env, SPR_TCR, "TCR",
1421                 SPR_NOACCESS, SPR_NOACCESS,
1422                 &spr_read_generic, &spr_write_generic,
1423                 0x00000000);
1424    /* Interrupt base */
1425    spr_register(env, SPR_IBR, "IBR",
1426                 SPR_NOACCESS, SPR_NOACCESS,
1427                 &spr_read_generic, &spr_write_generic,
1428                 0x00000000);
1429    /* XXX : not implemented */
1430    spr_register(env, SPR_IABR, "IABR",
1431                 SPR_NOACCESS, SPR_NOACCESS,
1432                 &spr_read_generic, &spr_write_generic,
1433                 0x00000000);
1434}
1435
1436/* SPR specific to PowerPC 601 implementation */
1437static void gen_spr_601(CPUPPCState *env)
1438{
1439    /* Multiplication/division register */
1440    /* MQ */
1441    spr_register(env, SPR_MQ, "MQ",
1442                 &spr_read_generic, &spr_write_generic,
1443                 &spr_read_generic, &spr_write_generic,
1444                 0x00000000);
1445    /* RTC registers */
1446    spr_register(env, SPR_601_RTCU, "RTCU",
1447                 SPR_NOACCESS, SPR_NOACCESS,
1448                 SPR_NOACCESS, &spr_write_601_rtcu,
1449                 0x00000000);
1450    spr_register(env, SPR_601_VRTCU, "RTCU",
1451                 &spr_read_601_rtcu, SPR_NOACCESS,
1452                 &spr_read_601_rtcu, SPR_NOACCESS,
1453                 0x00000000);
1454    spr_register(env, SPR_601_RTCL, "RTCL",
1455                 SPR_NOACCESS, SPR_NOACCESS,
1456                 SPR_NOACCESS, &spr_write_601_rtcl,
1457                 0x00000000);
1458    spr_register(env, SPR_601_VRTCL, "RTCL",
1459                 &spr_read_601_rtcl, SPR_NOACCESS,
1460                 &spr_read_601_rtcl, SPR_NOACCESS,
1461                 0x00000000);
1462    /* Timer */
1463#if 0 /* ? */
1464    spr_register(env, SPR_601_UDECR, "UDECR",
1465                 &spr_read_decr, SPR_NOACCESS,
1466                 &spr_read_decr, SPR_NOACCESS,
1467                 0x00000000);
1468#endif
1469    /* External access control */
1470    /* XXX : not implemented */
1471    spr_register(env, SPR_EAR, "EAR",
1472                 SPR_NOACCESS, SPR_NOACCESS,
1473                 &spr_read_generic, &spr_write_generic,
1474                 0x00000000);
1475    /* Memory management */
1476#if !defined(CONFIG_USER_ONLY)
1477    spr_register(env, SPR_IBAT0U, "IBAT0U",
1478                 SPR_NOACCESS, SPR_NOACCESS,
1479                 &spr_read_601_ubat, &spr_write_601_ubatu,
1480                 0x00000000);
1481    spr_register(env, SPR_IBAT0L, "IBAT0L",
1482                 SPR_NOACCESS, SPR_NOACCESS,
1483                 &spr_read_601_ubat, &spr_write_601_ubatl,
1484                 0x00000000);
1485    spr_register(env, SPR_IBAT1U, "IBAT1U",
1486                 SPR_NOACCESS, SPR_NOACCESS,
1487                 &spr_read_601_ubat, &spr_write_601_ubatu,
1488                 0x00000000);
1489    spr_register(env, SPR_IBAT1L, "IBAT1L",
1490                 SPR_NOACCESS, SPR_NOACCESS,
1491                 &spr_read_601_ubat, &spr_write_601_ubatl,
1492                 0x00000000);
1493    spr_register(env, SPR_IBAT2U, "IBAT2U",
1494                 SPR_NOACCESS, SPR_NOACCESS,
1495                 &spr_read_601_ubat, &spr_write_601_ubatu,
1496                 0x00000000);
1497    spr_register(env, SPR_IBAT2L, "IBAT2L",
1498                 SPR_NOACCESS, SPR_NOACCESS,
1499                 &spr_read_601_ubat, &spr_write_601_ubatl,
1500                 0x00000000);
1501    spr_register(env, SPR_IBAT3U, "IBAT3U",
1502                 SPR_NOACCESS, SPR_NOACCESS,
1503                 &spr_read_601_ubat, &spr_write_601_ubatu,
1504                 0x00000000);
1505    spr_register(env, SPR_IBAT3L, "IBAT3L",
1506                 SPR_NOACCESS, SPR_NOACCESS,
1507                 &spr_read_601_ubat, &spr_write_601_ubatl,
1508                 0x00000000);
1509    env->nb_BATs = 4;
1510#endif
1511}
1512
1513static void gen_spr_74xx(CPUPPCState *env)
1514{
1515    /* Processor identification */
1516    spr_register(env, SPR_PIR, "PIR",
1517                 SPR_NOACCESS, SPR_NOACCESS,
1518                 &spr_read_generic, &spr_write_pir,
1519                 0x00000000);
1520    /* XXX : not implemented */
1521    spr_register(env, SPR_74XX_MMCR2, "MMCR2",
1522                 SPR_NOACCESS, SPR_NOACCESS,
1523                 &spr_read_generic, &spr_write_generic,
1524                 0x00000000);
1525    /* XXX : not implemented */
1526    spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
1527                 &spr_read_ureg, SPR_NOACCESS,
1528                 &spr_read_ureg, SPR_NOACCESS,
1529                 0x00000000);
1530    /* XXX: not implemented */
1531    spr_register(env, SPR_BAMR, "BAMR",
1532                 SPR_NOACCESS, SPR_NOACCESS,
1533                 &spr_read_generic, &spr_write_generic,
1534                 0x00000000);
1535    /* XXX : not implemented */
1536    spr_register(env, SPR_MSSCR0, "MSSCR0",
1537                 SPR_NOACCESS, SPR_NOACCESS,
1538                 &spr_read_generic, &spr_write_generic,
1539                 0x00000000);
1540    /* Hardware implementation registers */
1541    /* XXX : not implemented */
1542    spr_register(env, SPR_HID0, "HID0",
1543                 SPR_NOACCESS, SPR_NOACCESS,
1544                 &spr_read_generic, &spr_write_generic,
1545                 0x00000000);
1546    /* XXX : not implemented */
1547    spr_register(env, SPR_HID1, "HID1",
1548                 SPR_NOACCESS, SPR_NOACCESS,
1549                 &spr_read_generic, &spr_write_generic,
1550                 0x00000000);
1551    /* Altivec */
1552    spr_register(env, SPR_VRSAVE, "VRSAVE",
1553                 &spr_read_generic, &spr_write_generic,
1554                 &spr_read_generic, &spr_write_generic,
1555                 0x00000000);
1556    /* XXX : not implemented */
1557    spr_register(env, SPR_L2CR, "L2CR",
1558                 SPR_NOACCESS, SPR_NOACCESS,
1559                 &spr_read_generic, spr_access_nop,
1560                 0x00000000);
1561    /* Not strictly an SPR */
1562    vscr_init(env, 0x00010000);
1563}
1564
1565static void gen_l3_ctrl(CPUPPCState *env)
1566{
1567    /* L3CR */
1568    /* XXX : not implemented */
1569    spr_register(env, SPR_L3CR, "L3CR",
1570                 SPR_NOACCESS, SPR_NOACCESS,
1571                 &spr_read_generic, &spr_write_generic,
1572                 0x00000000);
1573    /* L3ITCR0 */
1574    /* XXX : not implemented */
1575    spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1576                 SPR_NOACCESS, SPR_NOACCESS,
1577                 &spr_read_generic, &spr_write_generic,
1578                 0x00000000);
1579    /* L3PM */
1580    /* XXX : not implemented */
1581    spr_register(env, SPR_L3PM, "L3PM",
1582                 SPR_NOACCESS, SPR_NOACCESS,
1583                 &spr_read_generic, &spr_write_generic,
1584                 0x00000000);
1585}
1586
1587static void gen_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
1588{
1589#if !defined(CONFIG_USER_ONLY)
1590    env->nb_tlb = nb_tlbs;
1591    env->nb_ways = nb_ways;
1592    env->id_tlbs = 1;
1593    env->tlb_type = TLB_6XX;
1594    /* XXX : not implemented */
1595    spr_register(env, SPR_PTEHI, "PTEHI",
1596                 SPR_NOACCESS, SPR_NOACCESS,
1597                 &spr_read_generic, &spr_write_generic,
1598                 0x00000000);
1599    /* XXX : not implemented */
1600    spr_register(env, SPR_PTELO, "PTELO",
1601                 SPR_NOACCESS, SPR_NOACCESS,
1602                 &spr_read_generic, &spr_write_generic,
1603                 0x00000000);
1604    /* XXX : not implemented */
1605    spr_register(env, SPR_TLBMISS, "TLBMISS",
1606                 SPR_NOACCESS, SPR_NOACCESS,
1607                 &spr_read_generic, &spr_write_generic,
1608                 0x00000000);
1609#endif
1610}
1611
1612#if !defined(CONFIG_USER_ONLY)
1613static void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn)
1614{
1615    TCGv t0 = tcg_temp_new();
1616
1617    tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
1618    gen_store_spr(sprn, t0);
1619    tcg_temp_free(t0);
1620}
1621
1622static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
1623{
1624    TCGv t0 = tcg_temp_new();
1625
1626    tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
1627    gen_store_spr(sprn, t0);
1628    tcg_temp_free(t0);
1629}
1630
1631static void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
1632{
1633    gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
1634}
1635
1636static void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
1637{
1638    TCGv_i32 t0 = tcg_const_i32(sprn);
1639    gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1640    tcg_temp_free_i32(t0);
1641}
1642#endif
1643
1644static void gen_spr_usprg3(CPUPPCState *env)
1645{
1646    spr_register(env, SPR_USPRG3, "USPRG3",
1647                 &spr_read_ureg, SPR_NOACCESS,
1648                 &spr_read_ureg, SPR_NOACCESS,
1649                 0x00000000);
1650}
1651
1652static void gen_spr_usprgh(CPUPPCState *env)
1653{
1654    spr_register(env, SPR_USPRG4, "USPRG4",
1655                 &spr_read_ureg, SPR_NOACCESS,
1656                 &spr_read_ureg, SPR_NOACCESS,
1657                 0x00000000);
1658    spr_register(env, SPR_USPRG5, "USPRG5",
1659                 &spr_read_ureg, SPR_NOACCESS,
1660                 &spr_read_ureg, SPR_NOACCESS,
1661                 0x00000000);
1662    spr_register(env, SPR_USPRG6, "USPRG6",
1663                 &spr_read_ureg, SPR_NOACCESS,
1664                 &spr_read_ureg, SPR_NOACCESS,
1665                 0x00000000);
1666    spr_register(env, SPR_USPRG7, "USPRG7",
1667                 &spr_read_ureg, SPR_NOACCESS,
1668                 &spr_read_ureg, SPR_NOACCESS,
1669                 0x00000000);
1670}
1671
1672/* PowerPC BookE SPR */
1673static void gen_spr_BookE(CPUPPCState *env, uint64_t ivor_mask)
1674{
1675    const char *ivor_names[64] = {
1676        "IVOR0",  "IVOR1",  "IVOR2",  "IVOR3",
1677        "IVOR4",  "IVOR5",  "IVOR6",  "IVOR7",
1678        "IVOR8",  "IVOR9",  "IVOR10", "IVOR11",
1679        "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1680        "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1681        "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1682        "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1683        "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1684        "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1685        "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1686        "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1687        "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1688        "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1689        "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1690        "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1691        "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1692    };
1693#define SPR_BOOKE_IVORxx (-1)
1694    int ivor_sprn[64] = {
1695        SPR_BOOKE_IVOR0,  SPR_BOOKE_IVOR1,  SPR_BOOKE_IVOR2,  SPR_BOOKE_IVOR3,
1696        SPR_BOOKE_IVOR4,  SPR_BOOKE_IVOR5,  SPR_BOOKE_IVOR6,  SPR_BOOKE_IVOR7,
1697        SPR_BOOKE_IVOR8,  SPR_BOOKE_IVOR9,  SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1698        SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1699        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1700        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1701        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1702        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1703        SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1704        SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1705        SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1706        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1707        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1708        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1709        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1710        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1711    };
1712    int i;
1713
1714    /* Interrupt processing */
1715    spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1716                 SPR_NOACCESS, SPR_NOACCESS,
1717                 &spr_read_generic, &spr_write_generic,
1718                 0x00000000);
1719    spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1720                 SPR_NOACCESS, SPR_NOACCESS,
1721                 &spr_read_generic, &spr_write_generic,
1722                 0x00000000);
1723    /* Debug */
1724    /* XXX : not implemented */
1725    spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1726                 SPR_NOACCESS, SPR_NOACCESS,
1727                 &spr_read_generic, &spr_write_generic,
1728                 0x00000000);
1729    /* XXX : not implemented */
1730    spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1731                 SPR_NOACCESS, SPR_NOACCESS,
1732                 &spr_read_generic, &spr_write_generic,
1733                 0x00000000);
1734    /* XXX : not implemented */
1735    spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1736                 SPR_NOACCESS, SPR_NOACCESS,
1737                 &spr_read_generic, &spr_write_generic,
1738                 0x00000000);
1739    /* XXX : not implemented */
1740    spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1741                 SPR_NOACCESS, SPR_NOACCESS,
1742                 &spr_read_generic, &spr_write_generic,
1743                 0x00000000);
1744    /* XXX : not implemented */
1745    spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1746                 SPR_NOACCESS, SPR_NOACCESS,
1747                 &spr_read_generic, &spr_write_40x_dbcr0,
1748                 0x00000000);
1749    /* XXX : not implemented */
1750    spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1751                 SPR_NOACCESS, SPR_NOACCESS,
1752                 &spr_read_generic, &spr_write_generic,
1753                 0x00000000);
1754    /* XXX : not implemented */
1755    spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1756                 SPR_NOACCESS, SPR_NOACCESS,
1757                 &spr_read_generic, &spr_write_generic,
1758                 0x00000000);
1759    /* XXX : not implemented */
1760    spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1761                 SPR_NOACCESS, SPR_NOACCESS,
1762                 &spr_read_generic, &spr_write_clear,
1763                 0x00000000);
1764    spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1765                 SPR_NOACCESS, SPR_NOACCESS,
1766                 &spr_read_generic, &spr_write_generic,
1767                 0x00000000);
1768    spr_register(env, SPR_BOOKE_ESR, "ESR",
1769                 SPR_NOACCESS, SPR_NOACCESS,
1770                 &spr_read_generic, &spr_write_generic,
1771                 0x00000000);
1772    spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1773                 SPR_NOACCESS, SPR_NOACCESS,
1774                 &spr_read_generic, &spr_write_excp_prefix,
1775                 0x00000000);
1776    /* Exception vectors */
1777    for (i = 0; i < 64; i++) {
1778        if (ivor_mask & (1ULL << i)) {
1779            if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1780                fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1781                exit(1);
1782            }
1783            spr_register(env, ivor_sprn[i], ivor_names[i],
1784                         SPR_NOACCESS, SPR_NOACCESS,
1785                         &spr_read_generic, &spr_write_excp_vector,
1786                         0x00000000);
1787        }
1788    }
1789    spr_register(env, SPR_BOOKE_PID, "PID",
1790                 SPR_NOACCESS, SPR_NOACCESS,
1791                 &spr_read_generic, &spr_write_booke_pid,
1792                 0x00000000);
1793    spr_register(env, SPR_BOOKE_TCR, "TCR",
1794                 SPR_NOACCESS, SPR_NOACCESS,
1795                 &spr_read_generic, &spr_write_booke_tcr,
1796                 0x00000000);
1797    spr_register(env, SPR_BOOKE_TSR, "TSR",
1798                 SPR_NOACCESS, SPR_NOACCESS,
1799                 &spr_read_generic, &spr_write_booke_tsr,
1800                 0x00000000);
1801    /* Timer */
1802    spr_register(env, SPR_DECR, "DECR",
1803                 SPR_NOACCESS, SPR_NOACCESS,
1804                 &spr_read_decr, &spr_write_decr,
1805                 0x00000000);
1806    spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1807                 SPR_NOACCESS, SPR_NOACCESS,
1808                 SPR_NOACCESS, &spr_write_generic,
1809                 0x00000000);
1810    /* SPRGs */
1811    spr_register(env, SPR_USPRG0, "USPRG0",
1812                 &spr_read_generic, &spr_write_generic,
1813                 &spr_read_generic, &spr_write_generic,
1814                 0x00000000);
1815    spr_register(env, SPR_SPRG4, "SPRG4",
1816                 SPR_NOACCESS, SPR_NOACCESS,
1817                 &spr_read_generic, &spr_write_generic,
1818                 0x00000000);
1819    spr_register(env, SPR_SPRG5, "SPRG5",
1820                 SPR_NOACCESS, SPR_NOACCESS,
1821                 &spr_read_generic, &spr_write_generic,
1822                 0x00000000);
1823    spr_register(env, SPR_SPRG6, "SPRG6",
1824                 SPR_NOACCESS, SPR_NOACCESS,
1825                 &spr_read_generic, &spr_write_generic,
1826                 0x00000000);
1827    spr_register(env, SPR_SPRG7, "SPRG7",
1828                 SPR_NOACCESS, SPR_NOACCESS,
1829                 &spr_read_generic, &spr_write_generic,
1830                 0x00000000);
1831}
1832
1833static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1834                                   uint32_t maxsize, uint32_t flags,
1835                                   uint32_t nentries)
1836{
1837    return (assoc << TLBnCFG_ASSOC_SHIFT) |
1838           (minsize << TLBnCFG_MINSIZE_SHIFT) |
1839           (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1840           flags | nentries;
1841}
1842
1843/* BookE 2.06 storage control registers */
1844static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1845                              uint32_t *tlbncfg)
1846{
1847#if !defined(CONFIG_USER_ONLY)
1848    const char *mas_names[8] = {
1849        "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1850    };
1851    int mas_sprn[8] = {
1852        SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1853        SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1854    };
1855    int i;
1856
1857    /* TLB assist registers */
1858    /* XXX : not implemented */
1859    for (i = 0; i < 8; i++) {
1860        void (*uea_write)(DisasContext *ctx, int sprn, int gprn) = &spr_write_generic32;
1861        if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1862            uea_write = &spr_write_generic;
1863        }
1864        if (mas_mask & (1 << i)) {
1865            spr_register(env, mas_sprn[i], mas_names[i],
1866                         SPR_NOACCESS, SPR_NOACCESS,
1867                         &spr_read_generic, uea_write,
1868                         0x00000000);
1869        }
1870    }
1871    if (env->nb_pids > 1) {
1872        /* XXX : not implemented */
1873        spr_register(env, SPR_BOOKE_PID1, "PID1",
1874                     SPR_NOACCESS, SPR_NOACCESS,
1875                     &spr_read_generic, &spr_write_booke_pid,
1876                     0x00000000);
1877    }
1878    if (env->nb_pids > 2) {
1879        /* XXX : not implemented */
1880        spr_register(env, SPR_BOOKE_PID2, "PID2",
1881                     SPR_NOACCESS, SPR_NOACCESS,
1882                     &spr_read_generic, &spr_write_booke_pid,
1883                     0x00000000);
1884    }
1885    /* XXX : not implemented */
1886    spr_register(env, SPR_MMUCFG, "MMUCFG",
1887                 SPR_NOACCESS, SPR_NOACCESS,
1888                 &spr_read_generic, SPR_NOACCESS,
1889                 0x00000000); /* TOFIX */
1890    switch (env->nb_ways) {
1891    case 4:
1892        spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1893                     SPR_NOACCESS, SPR_NOACCESS,
1894                     &spr_read_generic, SPR_NOACCESS,
1895                     tlbncfg[3]);
1896        /* Fallthru */
1897    case 3:
1898        spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1899                     SPR_NOACCESS, SPR_NOACCESS,
1900                     &spr_read_generic, SPR_NOACCESS,
1901                     tlbncfg[2]);
1902        /* Fallthru */
1903    case 2:
1904        spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1905                     SPR_NOACCESS, SPR_NOACCESS,
1906                     &spr_read_generic, SPR_NOACCESS,
1907                     tlbncfg[1]);
1908        /* Fallthru */
1909    case 1:
1910        spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1911                     SPR_NOACCESS, SPR_NOACCESS,
1912                     &spr_read_generic, SPR_NOACCESS,
1913                     tlbncfg[0]);
1914        /* Fallthru */
1915    case 0:
1916    default:
1917        break;
1918    }
1919#endif
1920
1921    gen_spr_usprgh(env);
1922}
1923
1924/* SPR specific to PowerPC 440 implementation */
1925static void gen_spr_440(CPUPPCState *env)
1926{
1927    /* Cache control */
1928    /* XXX : not implemented */
1929    spr_register(env, SPR_440_DNV0, "DNV0",
1930                 SPR_NOACCESS, SPR_NOACCESS,
1931                 &spr_read_generic, &spr_write_generic,
1932                 0x00000000);
1933    /* XXX : not implemented */
1934    spr_register(env, SPR_440_DNV1, "DNV1",
1935                 SPR_NOACCESS, SPR_NOACCESS,
1936                 &spr_read_generic, &spr_write_generic,
1937                 0x00000000);
1938    /* XXX : not implemented */
1939    spr_register(env, SPR_440_DNV2, "DNV2",
1940                 SPR_NOACCESS, SPR_NOACCESS,
1941                 &spr_read_generic, &spr_write_generic,
1942                 0x00000000);
1943    /* XXX : not implemented */
1944    spr_register(env, SPR_440_DNV3, "DNV3",
1945                 SPR_NOACCESS, SPR_NOACCESS,
1946                 &spr_read_generic, &spr_write_generic,
1947                 0x00000000);
1948    /* XXX : not implemented */
1949    spr_register(env, SPR_440_DTV0, "DTV0",
1950                 SPR_NOACCESS, SPR_NOACCESS,
1951                 &spr_read_generic, &spr_write_generic,
1952                 0x00000000);
1953    /* XXX : not implemented */
1954    spr_register(env, SPR_440_DTV1, "DTV1",
1955                 SPR_NOACCESS, SPR_NOACCESS,
1956                 &spr_read_generic, &spr_write_generic,
1957                 0x00000000);
1958    /* XXX : not implemented */
1959    spr_register(env, SPR_440_DTV2, "DTV2",
1960                 SPR_NOACCESS, SPR_NOACCESS,
1961                 &spr_read_generic, &spr_write_generic,
1962                 0x00000000);
1963    /* XXX : not implemented */
1964    spr_register(env, SPR_440_DTV3, "DTV3",
1965                 SPR_NOACCESS, SPR_NOACCESS,
1966                 &spr_read_generic, &spr_write_generic,
1967                 0x00000000);
1968    /* XXX : not implemented */
1969    spr_register(env, SPR_440_DVLIM, "DVLIM",
1970                 SPR_NOACCESS, SPR_NOACCESS,
1971                 &spr_read_generic, &spr_write_generic,
1972                 0x00000000);
1973    /* XXX : not implemented */
1974    spr_register(env, SPR_440_INV0, "INV0",
1975                 SPR_NOACCESS, SPR_NOACCESS,
1976                 &spr_read_generic, &spr_write_generic,
1977                 0x00000000);
1978    /* XXX : not implemented */
1979    spr_register(env, SPR_440_INV1, "INV1",
1980                 SPR_NOACCESS, SPR_NOACCESS,
1981                 &spr_read_generic, &spr_write_generic,
1982                 0x00000000);
1983    /* XXX : not implemented */
1984    spr_register(env, SPR_440_INV2, "INV2",
1985                 SPR_NOACCESS, SPR_NOACCESS,
1986                 &spr_read_generic, &spr_write_generic,
1987                 0x00000000);
1988    /* XXX : not implemented */
1989    spr_register(env, SPR_440_INV3, "INV3",
1990                 SPR_NOACCESS, SPR_NOACCESS,
1991                 &spr_read_generic, &spr_write_generic,
1992                 0x00000000);
1993    /* XXX : not implemented */
1994    spr_register(env, SPR_440_ITV0, "ITV0",
1995                 SPR_NOACCESS, SPR_NOACCESS,
1996                 &spr_read_generic, &spr_write_generic,
1997                 0x00000000);
1998    /* XXX : not implemented */
1999    spr_register(env, SPR_440_ITV1, "ITV1",
2000                 SPR_NOACCESS, SPR_NOACCESS,

2001                 &spr_read_generic, &spr_write_generic,
2002                 0x00000000);
2003    /* XXX : not implemented */
2004    spr_register(env, SPR_440_ITV2, "ITV2",
2005                 SPR_NOACCESS, SPR_NOACCESS,
2006                 &spr_read_generic, &spr_write_generic,
2007                 0x00000000);
2008    /* XXX : not implemented */
2009    spr_register(env, SPR_440_ITV3, "ITV3",
2010                 SPR_NOACCESS, SPR_NOACCESS,
2011                 &spr_read_generic, &spr_write_generic,
2012                 0x00000000);
2013    /* XXX : not implemented */
2014    spr_register(env, SPR_440_IVLIM, "IVLIM",
2015                 SPR_NOACCESS, SPR_NOACCESS,
2016                 &spr_read_generic, &spr_write_generic,
2017                 0x00000000);
2018    /* Cache debug */
2019    /* XXX : not implemented */
2020    spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
2021                 SPR_NOACCESS, SPR_NOACCESS,
2022                 &spr_read_generic, SPR_NOACCESS,
2023                 0x00000000);
2024    /* XXX : not implemented */
2025    spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
2026                 SPR_NOACCESS, SPR_NOACCESS,
2027                 &spr_read_generic, SPR_NOACCESS,
2028                 0x00000000);
2029    /* XXX : not implemented */
2030    spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
2031                 SPR_NOACCESS, SPR_NOACCESS,
2032                 &spr_read_generic, SPR_NOACCESS,
2033                 0x00000000);
2034    /* XXX : not implemented */
2035    spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
2036                 SPR_NOACCESS, SPR_NOACCESS,
2037                 &spr_read_generic, SPR_NOACCESS,
2038                 0x00000000);
2039    /* XXX : not implemented */
2040    spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
2041                 SPR_NOACCESS, SPR_NOACCESS,
2042                 &spr_read_generic, SPR_NOACCESS,
2043                 0x00000000);
2044    /* XXX : not implemented */
2045    spr_register(env, SPR_440_DBDR, "DBDR",
2046                 SPR_NOACCESS, SPR_NOACCESS,
2047                 &spr_read_generic, &spr_write_generic,
2048                 0x00000000);
2049    /* Processor control */
2050    spr_register(env, SPR_4xx_CCR0, "CCR0",
2051                 SPR_NOACCESS, SPR_NOACCESS,
2052                 &spr_read_generic, &spr_write_generic,
2053                 0x00000000);
2054    spr_register(env, SPR_440_RSTCFG, "RSTCFG",
2055                 SPR_NOACCESS, SPR_NOACCESS,
2056                 &spr_read_generic, SPR_NOACCESS,
2057                 0x00000000);
2058    /* Storage control */
2059    spr_register(env, SPR_440_MMUCR, "MMUCR",
2060                 SPR_NOACCESS, SPR_NOACCESS,
2061                 &spr_read_generic, &spr_write_generic,
2062                 0x00000000);
2063}
2064
2065/* SPR shared between PowerPC 40x implementations */
2066static void gen_spr_40x(CPUPPCState *env)
2067{
2068    /* Cache */
2069    /* not emulated, as QEMU do not emulate caches */
2070    spr_register(env, SPR_40x_DCCR, "DCCR",
2071                 SPR_NOACCESS, SPR_NOACCESS,
2072                 &spr_read_generic, &spr_write_generic,
2073                 0x00000000);
2074    /* not emulated, as QEMU do not emulate caches */
2075    spr_register(env, SPR_40x_ICCR, "ICCR",
2076                 SPR_NOACCESS, SPR_NOACCESS,
2077                 &spr_read_generic, &spr_write_generic,
2078                 0x00000000);
2079    /* not emulated, as QEMU do not emulate caches */
2080    spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
2081                 SPR_NOACCESS, SPR_NOACCESS,
2082                 &spr_read_generic, SPR_NOACCESS,
2083                 0x00000000);
2084    /* Exception */
2085    spr_register(env, SPR_40x_DEAR, "DEAR",
2086                 SPR_NOACCESS, SPR_NOACCESS,
2087                 &spr_read_generic, &spr_write_generic,
2088                 0x00000000);
2089    spr_register(env, SPR_40x_ESR, "ESR",
2090                 SPR_NOACCESS, SPR_NOACCESS,
2091                 &spr_read_generic, &spr_write_generic,
2092                 0x00000000);
2093    spr_register(env, SPR_40x_EVPR, "EVPR",
2094                 SPR_NOACCESS, SPR_NOACCESS,
2095                 &spr_read_generic, &spr_write_excp_prefix,
2096                 0x00000000);
2097    spr_register(env, SPR_40x_SRR2, "SRR2",
2098                 &spr_read_generic, &spr_write_generic,
2099                 &spr_read_generic, &spr_write_generic,
2100                 0x00000000);
2101    spr_register(env, SPR_40x_SRR3, "SRR3",
2102                 &spr_read_generic, &spr_write_generic,
2103                 &spr_read_generic, &spr_write_generic,
2104                 0x00000000);
2105    /* Timers */
2106    spr_register(env, SPR_40x_PIT, "PIT",
2107                 SPR_NOACCESS, SPR_NOACCESS,
2108                 &spr_read_40x_pit, &spr_write_40x_pit,
2109                 0x00000000);
2110    spr_register(env, SPR_40x_TCR, "TCR",
2111                 SPR_NOACCESS, SPR_NOACCESS,
2112                 &spr_read_generic, &spr_write_booke_tcr,
2113                 0x00000000);
2114    spr_register(env, SPR_40x_TSR, "TSR",
2115                 SPR_NOACCESS, SPR_NOACCESS,
2116                 &spr_read_generic, &spr_write_booke_tsr,
2117                 0x00000000);
2118}
2119
2120/* SPR specific to PowerPC 405 implementation */
2121static void gen_spr_405(CPUPPCState *env)
2122{
2123    /* MMU */
2124    spr_register(env, SPR_40x_PID, "PID",
2125                 SPR_NOACCESS, SPR_NOACCESS,
2126                 &spr_read_generic, &spr_write_generic,
2127                 0x00000000);
2128    spr_register(env, SPR_4xx_CCR0, "CCR0",
2129                 SPR_NOACCESS, SPR_NOACCESS,
2130                 &spr_read_generic, &spr_write_generic,
2131                 0x00700000);
2132    /* Debug interface */
2133    /* XXX : not implemented */
2134    spr_register(env, SPR_40x_DBCR0, "DBCR0",
2135                 SPR_NOACCESS, SPR_NOACCESS,
2136                 &spr_read_generic, &spr_write_40x_dbcr0,
2137                 0x00000000);
2138    /* XXX : not implemented */
2139    spr_register(env, SPR_405_DBCR1, "DBCR1",
2140                 SPR_NOACCESS, SPR_NOACCESS,
2141                 &spr_read_generic, &spr_write_generic,
2142                 0x00000000);
2143    /* XXX : not implemented */
2144    spr_register(env, SPR_40x_DBSR, "DBSR",
2145                 SPR_NOACCESS, SPR_NOACCESS,
2146                 &spr_read_generic, &spr_write_clear,
2147                 /* Last reset was system reset */
2148                 0x00000300);
2149    /* XXX : not implemented */
2150    spr_register(env, SPR_40x_DAC1, "DAC1",
2151                 SPR_NOACCESS, SPR_NOACCESS,
2152                 &spr_read_generic, &spr_write_generic,
2153                 0x00000000);
2154    spr_register(env, SPR_40x_DAC2, "DAC2",
2155                 SPR_NOACCESS, SPR_NOACCESS,
2156                 &spr_read_generic, &spr_write_generic,
2157                 0x00000000);
2158    /* XXX : not implemented */
2159    spr_register(env, SPR_405_DVC1, "DVC1",
2160                 SPR_NOACCESS, SPR_NOACCESS,
2161                 &spr_read_generic, &spr_write_generic,
2162                 0x00000000);
2163    /* XXX : not implemented */
2164    spr_register(env, SPR_405_DVC2, "DVC2",
2165                 SPR_NOACCESS, SPR_NOACCESS,
2166                 &spr_read_generic, &spr_write_generic,
2167                 0x00000000);
2168    /* XXX : not implemented */
2169    spr_register(env, SPR_40x_IAC1, "IAC1",
2170                 SPR_NOACCESS, SPR_NOACCESS,
2171                 &spr_read_generic, &spr_write_generic,
2172                 0x00000000);
2173    spr_register(env, SPR_40x_IAC2, "IAC2",
2174                 SPR_NOACCESS, SPR_NOACCESS,
2175                 &spr_read_generic, &spr_write_generic,
2176                 0x00000000);
2177    /* XXX : not implemented */
2178    spr_register(env, SPR_405_IAC3, "IAC3",
2179                 SPR_NOACCESS, SPR_NOACCESS,
2180                 &spr_read_generic, &spr_write_generic,
2181                 0x00000000);
2182    /* XXX : not implemented */
2183    spr_register(env, SPR_405_IAC4, "IAC4",
2184                 SPR_NOACCESS, SPR_NOACCESS,
2185                 &spr_read_generic, &spr_write_generic,
2186                 0x00000000);
2187    /* Storage control */
2188    /* XXX: TODO: not implemented */
2189    spr_register(env, SPR_405_SLER, "SLER",
2190                 SPR_NOACCESS, SPR_NOACCESS,
2191                 &spr_read_generic, &spr_write_40x_sler,
2192                 0x00000000);
2193    spr_register(env, SPR_40x_ZPR, "ZPR",
2194                 SPR_NOACCESS, SPR_NOACCESS,
2195                 &spr_read_generic, &spr_write_generic,
2196                 0x00000000);
2197    /* XXX : not implemented */
2198    spr_register(env, SPR_405_SU0R, "SU0R",
2199                 SPR_NOACCESS, SPR_NOACCESS,
2200                 &spr_read_generic, &spr_write_generic,
2201                 0x00000000);
2202    /* SPRG */
2203    spr_register(env, SPR_USPRG0, "USPRG0",
2204                 &spr_read_ureg, SPR_NOACCESS,
2205                 &spr_read_ureg, SPR_NOACCESS,
2206                 0x00000000);
2207    spr_register(env, SPR_SPRG4, "SPRG4",
2208                 SPR_NOACCESS, SPR_NOACCESS,
2209                 &spr_read_generic, &spr_write_generic,
2210                 0x00000000);
2211    spr_register(env, SPR_SPRG5, "SPRG5",
2212                 SPR_NOACCESS, SPR_NOACCESS,
2213                 spr_read_generic, &spr_write_generic,
2214                 0x00000000);
2215    spr_register(env, SPR_SPRG6, "SPRG6",
2216                 SPR_NOACCESS, SPR_NOACCESS,
2217                 spr_read_generic, &spr_write_generic,
2218                 0x00000000);
2219    spr_register(env, SPR_SPRG7, "SPRG7",
2220                 SPR_NOACCESS, SPR_NOACCESS,
2221                 spr_read_generic, &spr_write_generic,
2222                 0x00000000);
2223    gen_spr_usprgh(env);
2224}
2225
2226/* SPR shared between PowerPC 401 & 403 implementations */
2227static void gen_spr_401_403(CPUPPCState *env)
2228{
2229    /* Time base */
2230    spr_register(env, SPR_403_VTBL,  "TBL",
2231                 &spr_read_tbl, SPR_NOACCESS,
2232                 &spr_read_tbl, SPR_NOACCESS,
2233                 0x00000000);
2234    spr_register(env, SPR_403_TBL,   "TBL",
2235                 SPR_NOACCESS, SPR_NOACCESS,
2236                 SPR_NOACCESS, &spr_write_tbl,
2237                 0x00000000);
2238    spr_register(env, SPR_403_VTBU,  "TBU",
2239                 &spr_read_tbu, SPR_NOACCESS,
2240                 &spr_read_tbu, SPR_NOACCESS,
2241                 0x00000000);
2242    spr_register(env, SPR_403_TBU,   "TBU",
2243                 SPR_NOACCESS, SPR_NOACCESS,
2244                 SPR_NOACCESS, &spr_write_tbu,
2245                 0x00000000);
2246    /* Debug */
2247    /* not emulated, as QEMU do not emulate caches */
2248    spr_register(env, SPR_403_CDBCR, "CDBCR",
2249                 SPR_NOACCESS, SPR_NOACCESS,
2250                 &spr_read_generic, &spr_write_generic,
2251                 0x00000000);
2252}
2253
2254/* SPR specific to PowerPC 401 implementation */
2255static void gen_spr_401(CPUPPCState *env)
2256{
2257    /* Debug interface */
2258    /* XXX : not implemented */
2259    spr_register(env, SPR_40x_DBCR0, "DBCR",
2260                 SPR_NOACCESS, SPR_NOACCESS,
2261                 &spr_read_generic, &spr_write_40x_dbcr0,
2262                 0x00000000);
2263    /* XXX : not implemented */
2264    spr_register(env, SPR_40x_DBSR, "DBSR",
2265                 SPR_NOACCESS, SPR_NOACCESS,
2266                 &spr_read_generic, &spr_write_clear,
2267                 /* Last reset was system reset */
2268                 0x00000300);
2269    /* XXX : not implemented */
2270    spr_register(env, SPR_40x_DAC1, "DAC",
2271                 SPR_NOACCESS, SPR_NOACCESS,
2272                 &spr_read_generic, &spr_write_generic,
2273                 0x00000000);
2274    /* XXX : not implemented */
2275    spr_register(env, SPR_40x_IAC1, "IAC",
2276                 SPR_NOACCESS, SPR_NOACCESS,
2277                 &spr_read_generic, &spr_write_generic,
2278                 0x00000000);
2279    /* Storage control */
2280    /* XXX: TODO: not implemented */
2281    spr_register(env, SPR_405_SLER, "SLER",
2282                 SPR_NOACCESS, SPR_NOACCESS,
2283                 &spr_read_generic, &spr_write_40x_sler,
2284                 0x00000000);
2285    /* not emulated, as QEMU never does speculative access */
2286    spr_register(env, SPR_40x_SGR, "SGR",
2287                 SPR_NOACCESS, SPR_NOACCESS,
2288                 &spr_read_generic, &spr_write_generic,
2289                 0xFFFFFFFF);
2290    /* not emulated, as QEMU do not emulate caches */
2291    spr_register(env, SPR_40x_DCWR, "DCWR",
2292                 SPR_NOACCESS, SPR_NOACCESS,
2293                 &spr_read_generic, &spr_write_generic,
2294                 0x00000000);
2295}
2296
2297static void gen_spr_401x2(CPUPPCState *env)
2298{
2299    gen_spr_401(env);
2300    spr_register(env, SPR_40x_PID, "PID",
2301                 SPR_NOACCESS, SPR_NOACCESS,
2302                 &spr_read_generic, &spr_write_generic,
2303                 0x00000000);
2304    spr_register(env, SPR_40x_ZPR, "ZPR",
2305                 SPR_NOACCESS, SPR_NOACCESS,
2306                 &spr_read_generic, &spr_write_generic,
2307                 0x00000000);
2308}
2309
2310/* SPR specific to PowerPC 403 implementation */
2311static void gen_spr_403(CPUPPCState *env)
2312{
2313    /* Debug interface */
2314    /* XXX : not implemented */
2315    spr_register(env, SPR_40x_DBCR0, "DBCR0",
2316                 SPR_NOACCESS, SPR_NOACCESS,
2317                 &spr_read_generic, &spr_write_40x_dbcr0,
2318                 0x00000000);
2319    /* XXX : not implemented */
2320    spr_register(env, SPR_40x_DBSR, "DBSR",
2321                 SPR_NOACCESS, SPR_NOACCESS,
2322                 &spr_read_generic, &spr_write_clear,
2323                 /* Last reset was system reset */
2324                 0x00000300);
2325    /* XXX : not implemented */
2326    spr_register(env, SPR_40x_DAC1, "DAC1",
2327                 SPR_NOACCESS, SPR_NOACCESS,
2328                 &spr_read_generic, &spr_write_generic,
2329                 0x00000000);
2330    /* XXX : not implemented */
2331    spr_register(env, SPR_40x_DAC2, "DAC2",
2332                 SPR_NOACCESS, SPR_NOACCESS,
2333                 &spr_read_generic, &spr_write_generic,
2334                 0x00000000);
2335    /* XXX : not implemented */
2336    spr_register(env, SPR_40x_IAC1, "IAC1",
2337                 SPR_NOACCESS, SPR_NOACCESS,
2338                 &spr_read_generic, &spr_write_generic,
2339                 0x00000000);
2340    /* XXX : not implemented */
2341    spr_register(env, SPR_40x_IAC2, "IAC2",
2342                 SPR_NOACCESS, SPR_NOACCESS,
2343                 &spr_read_generic, &spr_write_generic,
2344                 0x00000000);
2345}
2346
2347static void gen_spr_403_real(CPUPPCState *env)
2348{
2349    spr_register(env, SPR_403_PBL1,  "PBL1",
2350                 SPR_NOACCESS, SPR_NOACCESS,
2351                 &spr_read_403_pbr, &spr_write_403_pbr,
2352                 0x00000000);
2353    spr_register(env, SPR_403_PBU1,  "PBU1",
2354                 SPR_NOACCESS, SPR_NOACCESS,
2355                 &spr_read_403_pbr, &spr_write_403_pbr,
2356                 0x00000000);
2357    spr_register(env, SPR_403_PBL2,  "PBL2",
2358                 SPR_NOACCESS, SPR_NOACCESS,
2359                 &spr_read_403_pbr, &spr_write_403_pbr,
2360                 0x00000000);
2361    spr_register(env, SPR_403_PBU2,  "PBU2",
2362                 SPR_NOACCESS, SPR_NOACCESS,
2363                 &spr_read_403_pbr, &spr_write_403_pbr,
2364                 0x00000000);
2365}
2366
2367static void gen_spr_403_mmu(CPUPPCState *env)
2368{
2369    /* MMU */
2370    spr_register(env, SPR_40x_PID, "PID",
2371                 SPR_NOACCESS, SPR_NOACCESS,
2372                 &spr_read_generic, &spr_write_generic,
2373                 0x00000000);
2374    spr_register(env, SPR_40x_ZPR, "ZPR",
2375                 SPR_NOACCESS, SPR_NOACCESS,
2376                 &spr_read_generic, &spr_write_generic,
2377                 0x00000000);
2378}
2379
2380/* SPR specific to PowerPC compression coprocessor extension */
2381static void gen_spr_compress(CPUPPCState *env)
2382{
2383    /* XXX : not implemented */
2384    spr_register(env, SPR_401_SKR, "SKR",
2385                 SPR_NOACCESS, SPR_NOACCESS,
2386                 &spr_read_generic, &spr_write_generic,
2387                 0x00000000);
2388}
2389
2390static void gen_spr_5xx_8xx(CPUPPCState *env)
2391{
2392    /* Exception processing */
2393    spr_register_kvm(env, SPR_DSISR, "DSISR",
2394                     SPR_NOACCESS, SPR_NOACCESS,
2395                     &spr_read_generic, &spr_write_generic,
2396                     KVM_REG_PPC_DSISR, 0x00000000);
2397    spr_register_kvm(env, SPR_DAR, "DAR",
2398                     SPR_NOACCESS, SPR_NOACCESS,
2399                     &spr_read_generic, &spr_write_generic,
2400                     KVM_REG_PPC_DAR, 0x00000000);
2401    /* Timer */
2402    spr_register(env, SPR_DECR, "DECR",
2403                 SPR_NOACCESS, SPR_NOACCESS,
2404                 &spr_read_decr, &spr_write_decr,
2405                 0x00000000);
2406    /* XXX : not implemented */
2407    spr_register(env, SPR_MPC_EIE, "EIE",
2408                 SPR_NOACCESS, SPR_NOACCESS,
2409                 &spr_read_generic, &spr_write_generic,
2410                 0x00000000);
2411    /* XXX : not implemented */
2412    spr_register(env, SPR_MPC_EID, "EID",
2413                 SPR_NOACCESS, SPR_NOACCESS,
2414                 &spr_read_generic, &spr_write_generic,
2415                 0x00000000);
2416    /* XXX : not implemented */
2417    spr_register(env, SPR_MPC_NRI, "NRI",
2418                 SPR_NOACCESS, SPR_NOACCESS,
2419                 &spr_read_generic, &spr_write_generic,
2420                 0x00000000);
2421    /* XXX : not implemented */
2422    spr_register(env, SPR_MPC_CMPA, "CMPA",
2423                 SPR_NOACCESS, SPR_NOACCESS,
2424                 &spr_read_generic, &spr_write_generic,
2425                 0x00000000);
2426    /* XXX : not implemented */
2427    spr_register(env, SPR_MPC_CMPB, "CMPB",
2428                 SPR_NOACCESS, SPR_NOACCESS,
2429                 &spr_read_generic, &spr_write_generic,
2430                 0x00000000);
2431    /* XXX : not implemented */
2432    spr_register(env, SPR_MPC_CMPC, "CMPC",
2433                 SPR_NOACCESS, SPR_NOACCESS,
2434                 &spr_read_generic, &spr_write_generic,
2435                 0x00000000);
2436    /* XXX : not implemented */
2437    spr_register(env, SPR_MPC_CMPD, "CMPD",
2438                 SPR_NOACCESS, SPR_NOACCESS,
2439                 &spr_read_generic, &spr_write_generic,
2440                 0x00000000);
2441    /* XXX : not implemented */
2442    spr_register(env, SPR_MPC_ECR, "ECR",
2443                 SPR_NOACCESS, SPR_NOACCESS,
2444                 &spr_read_generic, &spr_write_generic,
2445                 0x00000000);
2446    /* XXX : not implemented */
2447    spr_register(env, SPR_MPC_DER, "DER",
2448                 SPR_NOACCESS, SPR_NOACCESS,
2449                 &spr_read_generic, &spr_write_generic,
2450                 0x00000000);
2451    /* XXX : not implemented */
2452    spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2453                 SPR_NOACCESS, SPR_NOACCESS,
2454                 &spr_read_generic, &spr_write_generic,
2455                 0x00000000);
2456    /* XXX : not implemented */
2457    spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2458                 SPR_NOACCESS, SPR_NOACCESS,
2459                 &spr_read_generic, &spr_write_generic,
2460                 0x00000000);
2461    /* XXX : not implemented */
2462    spr_register(env, SPR_MPC_CMPE, "CMPE",
2463                 SPR_NOACCESS, SPR_NOACCESS,
2464                 &spr_read_generic, &spr_write_generic,
2465                 0x00000000);
2466    /* XXX : not implemented */
2467    spr_register(env, SPR_MPC_CMPF, "CMPF",
2468                 SPR_NOACCESS, SPR_NOACCESS,
2469                 &spr_read_generic, &spr_write_generic,
2470                 0x00000000);
2471    /* XXX : not implemented */
2472    spr_register(env, SPR_MPC_CMPG, "CMPG",
2473                 SPR_NOACCESS, SPR_NOACCESS,
2474                 &spr_read_generic, &spr_write_generic,
2475                 0x00000000);
2476    /* XXX : not implemented */
2477    spr_register(env, SPR_MPC_CMPH, "CMPH",
2478                 SPR_NOACCESS, SPR_NOACCESS,
2479                 &spr_read_generic, &spr_write_generic,
2480                 0x00000000);
2481    /* XXX : not implemented */
2482    spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2483                 SPR_NOACCESS, SPR_NOACCESS,
2484                 &spr_read_generic, &spr_write_generic,
2485                 0x00000000);
2486    /* XXX : not implemented */
2487    spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2488                 SPR_NOACCESS, SPR_NOACCESS,
2489                 &spr_read_generic, &spr_write_generic,
2490                 0x00000000);
2491    /* XXX : not implemented */
2492    spr_register(env, SPR_MPC_BAR, "BAR",
2493                 SPR_NOACCESS, SPR_NOACCESS,
2494                 &spr_read_generic, &spr_write_generic,
2495                 0x00000000);
2496    /* XXX : not implemented */
2497    spr_register(env, SPR_MPC_DPDR, "DPDR",
2498                 SPR_NOACCESS, SPR_NOACCESS,
2499                 &spr_read_generic, &spr_write_generic,
2500                 0x00000000);
2501    /* XXX : not implemented */
2502    spr_register(env, SPR_MPC_IMMR, "IMMR",
2503                 SPR_NOACCESS, SPR_NOACCESS,
2504                 &spr_read_generic, &spr_write_generic,
2505                 0x00000000);
2506}
2507
2508static void gen_spr_5xx(CPUPPCState *env)
2509{
2510    /* XXX : not implemented */
2511    spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2512                 SPR_NOACCESS, SPR_NOACCESS,
2513                 &spr_read_generic, &spr_write_generic,
2514                 0x00000000);
2515    /* XXX : not implemented */
2516    spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2517                 SPR_NOACCESS, SPR_NOACCESS,
2518                 &spr_read_generic, &spr_write_generic,
2519                 0x00000000);
2520    /* XXX : not implemented */
2521    spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2522                 SPR_NOACCESS, SPR_NOACCESS,
2523                 &spr_read_generic, &spr_write_generic,
2524                 0x00000000);
2525    /* XXX : not implemented */
2526    spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2527                 SPR_NOACCESS, SPR_NOACCESS,
2528                 &spr_read_generic, &spr_write_generic,
2529                 0x00000000);
2530    /* XXX : not implemented */
2531    spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2532                 SPR_NOACCESS, SPR_NOACCESS,
2533                 &spr_read_generic, &spr_write_generic,
2534                 0x00000000);
2535    /* XXX : not implemented */
2536    spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2537                 SPR_NOACCESS, SPR_NOACCESS,
2538                 &spr_read_generic, &spr_write_generic,
2539                 0x00000000);
2540    /* XXX : not implemented */
2541    spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2542                 SPR_NOACCESS, SPR_NOACCESS,
2543                 &spr_read_generic, &spr_write_generic,
2544                 0x00000000);
2545    /* XXX : not implemented */
2546    spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2547                 SPR_NOACCESS, SPR_NOACCESS,
2548                 &spr_read_generic, &spr_write_generic,
2549                 0x00000000);
2550    /* XXX : not implemented */
2551    spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2552                 SPR_NOACCESS, SPR_NOACCESS,
2553                 &spr_read_generic, &spr_write_generic,
2554                 0x00000000);
2555    /* XXX : not implemented */
2556    spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2557                 SPR_NOACCESS, SPR_NOACCESS,
2558                 &spr_read_generic, &spr_write_generic,
2559                 0x00000000);
2560    /* XXX : not implemented */
2561    spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2562                 SPR_NOACCESS, SPR_NOACCESS,
2563                 &spr_read_generic, &spr_write_generic,
2564                 0x00000000);
2565    /* XXX : not implemented */
2566    spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2567                 SPR_NOACCESS, SPR_NOACCESS,
2568                 &spr_read_generic, &spr_write_generic,
2569                 0x00000000);
2570    /* XXX : not implemented */
2571    spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2572                 SPR_NOACCESS, SPR_NOACCESS,
2573                 &spr_read_generic, &spr_write_generic,
2574                 0x00000000);
2575    /* XXX : not implemented */
2576    spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2577                 SPR_NOACCESS, SPR_NOACCESS,
2578                 &spr_read_generic, &spr_write_generic,
2579                 0x00000000);
2580    /* XXX : not implemented */
2581    spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2582                 SPR_NOACCESS, SPR_NOACCESS,
2583                 &spr_read_generic, &spr_write_generic,
2584                 0x00000000);
2585    /* XXX : not implemented */
2586    spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2587                 SPR_NOACCESS, SPR_NOACCESS,
2588                 &spr_read_generic, &spr_write_generic,
2589                 0x00000000);
2590    /* XXX : not implemented */
2591    spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2592                 SPR_NOACCESS, SPR_NOACCESS,
2593                 &spr_read_generic, &spr_write_generic,
2594                 0x00000000);
2595    /* XXX : not implemented */
2596    spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2597                 SPR_NOACCESS, SPR_NOACCESS,
2598                 &spr_read_generic, &spr_write_generic,
2599                 0x00000000);
2600    /* XXX : not implemented */
2601    spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2602                 SPR_NOACCESS, SPR_NOACCESS,
2603                 &spr_read_generic, &spr_write_generic,
2604                 0x00000000);
2605    /* XXX : not implemented */
2606    spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2607                 SPR_NOACCESS, SPR_NOACCESS,
2608                 &spr_read_generic, &spr_write_generic,
2609                 0x00000000);
2610    /* XXX : not implemented */
2611    spr_register(env, SPR_RCPU_FPECR, "FPECR",
2612                 SPR_NOACCESS, SPR_NOACCESS,
2613                 &spr_read_generic, &spr_write_generic,
2614                 0x00000000);
2615}
2616
2617static void gen_spr_8xx(CPUPPCState *env)
2618{
2619    /* XXX : not implemented */
2620    spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2621                 SPR_NOACCESS, SPR_NOACCESS,
2622                 &spr_read_generic, &spr_write_generic,
2623                 0x00000000);
2624    /* XXX : not implemented */
2625    spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2626                 SPR_NOACCESS, SPR_NOACCESS,
2627                 &spr_read_generic, &spr_write_generic,
2628                 0x00000000);
2629    /* XXX : not implemented */
2630    spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2631                 SPR_NOACCESS, SPR_NOACCESS,
2632                 &spr_read_generic, &spr_write_generic,
2633                 0x00000000);
2634    /* XXX : not implemented */
2635    spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2636                 SPR_NOACCESS, SPR_NOACCESS,
2637                 &spr_read_generic, &spr_write_generic,
2638                 0x00000000);
2639    /* XXX : not implemented */
2640    spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2641                 SPR_NOACCESS, SPR_NOACCESS,
2642                 &spr_read_generic, &spr_write_generic,
2643                 0x00000000);
2644    /* XXX : not implemented */
2645    spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2646                 SPR_NOACCESS, SPR_NOACCESS,
2647                 &spr_read_generic, &spr_write_generic,
2648                 0x00000000);
2649    /* XXX : not implemented */
2650    spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2651                 SPR_NOACCESS, SPR_NOACCESS,
2652                 &spr_read_generic, &spr_write_generic,
2653                 0x00000000);
2654    /* XXX : not implemented */
2655    spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2656                 SPR_NOACCESS, SPR_NOACCESS,
2657                 &spr_read_generic, &spr_write_generic,
2658                 0x00000000);
2659    /* XXX : not implemented */
2660    spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2661                 SPR_NOACCESS, SPR_NOACCESS,
2662                 &spr_read_generic, &spr_write_generic,
2663                 0x00000000);
2664    /* XXX : not implemented */
2665    spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2666                 SPR_NOACCESS, SPR_NOACCESS,
2667                 &spr_read_generic, &spr_write_generic,
2668                 0x00000000);
2669    /* XXX : not implemented */
2670    spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2671                 SPR_NOACCESS, SPR_NOACCESS,
2672                 &spr_read_generic, &spr_write_generic,
2673                 0x00000000);
2674    /* XXX : not implemented */
2675    spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2676                 SPR_NOACCESS, SPR_NOACCESS,
2677                 &spr_read_generic, &spr_write_generic,
2678                 0x00000000);
2679    /* XXX : not implemented */
2680    spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2681                 SPR_NOACCESS, SPR_NOACCESS,
2682                 &spr_read_generic, &spr_write_generic,
2683                 0x00000000);
2684    /* XXX : not implemented */
2685    spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2686                 SPR_NOACCESS, SPR_NOACCESS,
2687                 &spr_read_generic, &spr_write_generic,
2688                 0x00000000);
2689    /* XXX : not implemented */
2690    spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2691                 SPR_NOACCESS, SPR_NOACCESS,
2692                 &spr_read_generic, &spr_write_generic,
2693                 0x00000000);
2694    /* XXX : not implemented */
2695    spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2696                 SPR_NOACCESS, SPR_NOACCESS,
2697                 &spr_read_generic, &spr_write_generic,
2698                 0x00000000);
2699    /* XXX : not implemented */
2700    spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2701                 SPR_NOACCESS, SPR_NOACCESS,
2702                 &spr_read_generic, &spr_write_generic,
2703                 0x00000000);
2704    /* XXX : not implemented */
2705    spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2706                 SPR_NOACCESS, SPR_NOACCESS,
2707                 &spr_read_generic, &spr_write_generic,
2708                 0x00000000);
2709    /* XXX : not implemented */
2710    spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2711                 SPR_NOACCESS, SPR_NOACCESS,
2712                 &spr_read_generic, &spr_write_generic,
2713                 0x00000000);
2714    /* XXX : not implemented */
2715    spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2716                 SPR_NOACCESS, SPR_NOACCESS,
2717                 &spr_read_generic, &spr_write_generic,
2718                 0x00000000);
2719    /* XXX : not implemented */
2720    spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2721                 SPR_NOACCESS, SPR_NOACCESS,
2722                 &spr_read_generic, &spr_write_generic,
2723                 0x00000000);
2724    /* XXX : not implemented */
2725    spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2726                 SPR_NOACCESS, SPR_NOACCESS,
2727                 &spr_read_generic, &spr_write_generic,
2728                 0x00000000);
2729    /* XXX : not implemented */
2730    spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2731                 SPR_NOACCESS, SPR_NOACCESS,
2732                 &spr_read_generic, &spr_write_generic,
2733                 0x00000000);
2734    /* XXX : not implemented */
2735    spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2736                 SPR_NOACCESS, SPR_NOACCESS,
2737                 &spr_read_generic, &spr_write_generic,
2738                 0x00000000);
2739    /* XXX : not implemented */
2740    spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2741                 SPR_NOACCESS, SPR_NOACCESS,
2742                 &spr_read_generic, &spr_write_generic,
2743                 0x00000000);
2744}
2745
2746// XXX: TODO
2747/*
2748 * AMR     => SPR 29 (Power 2.04)
2749 * CTRL    => SPR 136 (Power 2.04)
2750 * CTRL    => SPR 152 (Power 2.04)
2751 * SCOMC   => SPR 276 (64 bits ?)
2752 * SCOMD   => SPR 277 (64 bits ?)
2753 * TBU40   => SPR 286 (Power 2.04 hypv)
2754 * HSPRG0  => SPR 304 (Power 2.04 hypv)
2755 * HSPRG1  => SPR 305 (Power 2.04 hypv)
2756 * HDSISR  => SPR 306 (Power 2.04 hypv)
2757 * HDAR    => SPR 307 (Power 2.04 hypv)
2758 * PURR    => SPR 309 (Power 2.04 hypv)
2759 * HDEC    => SPR 310 (Power 2.04 hypv)
2760 * HIOR    => SPR 311 (hypv)
2761 * RMOR    => SPR 312 (970)
2762 * HRMOR   => SPR 313 (Power 2.04 hypv)
2763 * HSRR0   => SPR 314 (Power 2.04 hypv)
2764 * HSRR1   => SPR 315 (Power 2.04 hypv)
2765 * LPIDR   => SPR 317 (970)
2766 * EPR     => SPR 702 (Power 2.04 emb)
2767 * perf    => 768-783 (Power 2.04)
2768 * perf    => 784-799 (Power 2.04)
2769 * PPR     => SPR 896 (Power 2.04)
2770 * EPLC    => SPR 947 (Power 2.04 emb)
2771 * EPSC    => SPR 948 (Power 2.04 emb)
2772 * DABRX   => 1015    (Power 2.04 hypv)
2773 * FPECR   => SPR 1022 (?)
2774 * ... and more (thermal management, performance counters, ...)
2775 */
2776
2777/*****************************************************************************/
2778/* Exception vectors models                                                  */
2779static void init_excp_4xx_real(CPUPPCState *env)
2780{
2781#if !defined(CONFIG_USER_ONLY)
2782    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2783    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2784    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2785    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2786    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2787    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2788    env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2789    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2790    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2791    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2792    env->ivor_mask = 0x0000FFF0UL;
2793    env->ivpr_mask = 0xFFFF0000UL;
2794    /* Hardware reset vector */
2795    env->hreset_vector = 0xFFFFFFFCUL;
2796#endif
2797}
2798
2799static void init_excp_4xx_softmmu(CPUPPCState *env)
2800{
2801#if !defined(CONFIG_USER_ONLY)
2802    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2803    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2804    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2805    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2806    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2807    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2808    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2809    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2810    env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2811    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2812    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2813    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001100;
2814    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001200;
2815    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2816    env->ivor_mask = 0x0000FFF0UL;
2817    env->ivpr_mask = 0xFFFF0000UL;
2818    /* Hardware reset vector */
2819    env->hreset_vector = 0xFFFFFFFCUL;
2820#endif
2821}
2822
2823static void init_excp_MPC5xx(CPUPPCState *env)
2824{
2825#if !defined(CONFIG_USER_ONLY)
2826    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2827    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2828    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2829    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2830    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2831    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
2832    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2833    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2834    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2835    env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2836    env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001000;
2837    env->excp_vectors[POWERPC_EXCP_DABR]     = 0x00001C00;
2838    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001C00;
2839    env->excp_vectors[POWERPC_EXCP_MEXTBR]   = 0x00001E00;
2840    env->excp_vectors[POWERPC_EXCP_NMEXTBR]  = 0x00001F00;
2841    env->ivor_mask = 0x0000FFF0UL;
2842    env->ivpr_mask = 0xFFFF0000UL;
2843    /* Hardware reset vector */
2844    env->hreset_vector = 0x00000100UL;
2845#endif
2846}
2847
2848static void init_excp_MPC8xx(CPUPPCState *env)
2849{
2850#if !defined(CONFIG_USER_ONLY)
2851    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2852    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2853    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2854    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2855    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2856    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2857    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2858    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
2859    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2860    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2861    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2862    env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2863    env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001000;
2864    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001100;
2865    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001200;
2866    env->excp_vectors[POWERPC_EXCP_ITLBE]    = 0x00001300;
2867    env->excp_vectors[POWERPC_EXCP_DTLBE]    = 0x00001400;
2868    env->excp_vectors[POWERPC_EXCP_DABR]     = 0x00001C00;
2869    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001C00;
2870    env->excp_vectors[POWERPC_EXCP_MEXTBR]   = 0x00001E00;
2871    env->excp_vectors[POWERPC_EXCP_NMEXTBR]  = 0x00001F00;
2872    env->ivor_mask = 0x0000FFF0UL;
2873    env->ivpr_mask = 0xFFFF0000UL;
2874    /* Hardware reset vector */
2875    env->hreset_vector = 0x00000100UL;
2876#endif
2877}
2878
2879static void init_excp_G2(CPUPPCState *env)
2880{
2881#if !defined(CONFIG_USER_ONLY)
2882    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2883    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2884    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2885    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2886    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2887    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2888    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2889    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2890    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2891    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2892    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2893    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2894    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2895    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2896    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2897    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2898    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2899    /* Hardware reset vector */
2900    env->hreset_vector = 0x00000100UL;
2901#endif
2902}
2903
2904static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2905{
2906#if !defined(CONFIG_USER_ONLY)
2907    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000FFC;
2908    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2909    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
2910    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
2911    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
2912    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2913    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
2914    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
2915    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
2916    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
2917    env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
2918    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
2919    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
2920    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
2921    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
2922    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
2923    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
2924    env->excp_vectors[POWERPC_EXCP_SPEU]     = 0x00000000;
2925    env->excp_vectors[POWERPC_EXCP_EFPDI]    = 0x00000000;
2926    env->excp_vectors[POWERPC_EXCP_EFPRI]    = 0x00000000;
2927    env->ivor_mask = 0x0000FFF7UL;
2928    env->ivpr_mask = ivpr_mask;
2929    /* Hardware reset vector */
2930    env->hreset_vector = 0xFFFFFFFCUL;
2931#endif
2932}
2933
2934static void init_excp_BookE(CPUPPCState *env)
2935{
2936#if !defined(CONFIG_USER_ONLY)
2937    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2938    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
2939    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
2940    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
2941    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2942    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
2943    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
2944    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
2945    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
2946    env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
2947    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
2948    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
2949    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
2950    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
2951    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
2952    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
2953    env->ivor_mask = 0x0000FFF0UL;
2954    env->ivpr_mask = 0xFFFF0000UL;
2955    /* Hardware reset vector */
2956    env->hreset_vector = 0xFFFFFFFCUL;
2957#endif
2958}
2959
2960static void init_excp_601(CPUPPCState *env)
2961{
2962#if !defined(CONFIG_USER_ONLY)
2963    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2964    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2965    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2966    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2967    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2968    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2969    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2970    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2971    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2972    env->excp_vectors[POWERPC_EXCP_IO]       = 0x00000A00;
2973    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2974    env->excp_vectors[POWERPC_EXCP_RUNM]     = 0x00002000;
2975    /* Hardware reset vector */
2976    env->hreset_vector = 0x00000100UL;
2977#endif
2978}
2979
2980static void init_excp_602(CPUPPCState *env)
2981{
2982#if !defined(CONFIG_USER_ONLY)
2983    /* XXX: exception prefix has a special behavior on 602 */
2984    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2985    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2986    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2987    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2988    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2989    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2990    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2991    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2992    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2993    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2994    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2995    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2996    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2997    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2998    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2999    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3000    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001500;

3001    env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001600;
3002    /* Hardware reset vector */
3003    env->hreset_vector = 0x00000100UL;
3004#endif
3005}
3006
3007static void init_excp_603(CPUPPCState *env)
3008{
3009#if !defined(CONFIG_USER_ONLY)
3010    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3011    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3012    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3013    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3014    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3015    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3016    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3017    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3018    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3019    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3020    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3021    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
3022    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
3023    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
3024    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3025    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3026    /* Hardware reset vector */
3027    env->hreset_vector = 0x00000100UL;
3028#endif
3029}
3030
3031static void init_excp_604(CPUPPCState *env)
3032{
3033#if !defined(CONFIG_USER_ONLY)
3034    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3035    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3036    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3037    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3038    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3039    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3040    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3041    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3042    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3043    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3044    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3045    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3046    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3047    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3048    /* Hardware reset vector */
3049    env->hreset_vector = 0x00000100UL;
3050#endif
3051}
3052
3053static void init_excp_7x0(CPUPPCState *env)
3054{
3055#if !defined(CONFIG_USER_ONLY)
3056    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3057    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3058    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3059    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3060    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3061    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3062    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3063    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3064    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3065    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3066    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3067    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3068    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3069    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3070    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
3071    /* Hardware reset vector */
3072    env->hreset_vector = 0x00000100UL;
3073#endif
3074}
3075
3076static void init_excp_750cl(CPUPPCState *env)
3077{
3078#if !defined(CONFIG_USER_ONLY)
3079    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3080    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3081    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3082    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3083    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3084    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3085    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3086    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3087    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3088    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3089    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3090    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3091    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3092    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3093    /* Hardware reset vector */
3094    env->hreset_vector = 0x00000100UL;
3095#endif
3096}
3097
3098static void init_excp_750cx(CPUPPCState *env)
3099{
3100#if !defined(CONFIG_USER_ONLY)
3101    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3102    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3103    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3104    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3105    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3106    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3107    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3108    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3109    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3110    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3111    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3112    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3113    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3114    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
3115    /* Hardware reset vector */
3116    env->hreset_vector = 0x00000100UL;
3117#endif
3118}
3119
3120/* XXX: Check if this is correct */
3121static void init_excp_7x5(CPUPPCState *env)
3122{
3123#if !defined(CONFIG_USER_ONLY)
3124    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3125    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3126    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3127    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3128    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3129    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3130    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3131    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3132    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3133    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3134    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3135    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3136    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
3137    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
3138    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
3139    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3140    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3141    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
3142    /* Hardware reset vector */
3143    env->hreset_vector = 0x00000100UL;
3144#endif
3145}
3146
3147static void init_excp_7400(CPUPPCState *env)
3148{
3149#if !defined(CONFIG_USER_ONLY)
3150    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3151    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3152    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3153    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3154    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3155    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3156    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3157    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3158    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3159    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3160    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3161    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3162    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3163    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3164    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3165    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
3166    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
3167    /* Hardware reset vector */
3168    env->hreset_vector = 0x00000100UL;
3169#endif
3170}
3171
3172static void init_excp_7450(CPUPPCState *env)
3173{
3174#if !defined(CONFIG_USER_ONLY)
3175    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3176    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3177    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3178    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3179    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3180    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3181    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3182    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3183    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3184    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3185    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3186    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3187    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3188    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
3189    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
3190    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
3191    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3192    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3193    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
3194    /* Hardware reset vector */
3195    env->hreset_vector = 0x00000100UL;
3196#endif
3197}
3198
3199#if defined(TARGET_PPC64)
3200static void init_excp_970(CPUPPCState *env)
3201{
3202#if !defined(CONFIG_USER_ONLY)
3203    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3204    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3205    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3206    env->excp_vectors[POWERPC_EXCP_DSEG]     = 0x00000380;
3207    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3208    env->excp_vectors[POWERPC_EXCP_ISEG]     = 0x00000480;
3209    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3210    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3211    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3212    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3213    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3214    env->excp_vectors[POWERPC_EXCP_HDECR]    = 0x00000980;
3215    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3216    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3217    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3218    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3219    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3220    env->excp_vectors[POWERPC_EXCP_MAINT]    = 0x00001600;
3221    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001700;
3222    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001800;
3223    /* Hardware reset vector */
3224    env->hreset_vector = 0x0000000000000100ULL;
3225#endif
3226}
3227
3228static void init_excp_POWER7(CPUPPCState *env)
3229{
3230#if !defined(CONFIG_USER_ONLY)
3231    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3232    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3233    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3234    env->excp_vectors[POWERPC_EXCP_DSEG]     = 0x00000380;
3235    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3236    env->excp_vectors[POWERPC_EXCP_ISEG]     = 0x00000480;
3237    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3238    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3239    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3240    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3241    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3242    env->excp_vectors[POWERPC_EXCP_HDECR]    = 0x00000980;
3243    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3244    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3245    env->excp_vectors[POWERPC_EXCP_HDSI]     = 0x00000E00;
3246    env->excp_vectors[POWERPC_EXCP_HISI]     = 0x00000E20;
3247    env->excp_vectors[POWERPC_EXCP_HV_EMU]   = 0x00000E40;
3248    env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60;
3249    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3250    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3251    env->excp_vectors[POWERPC_EXCP_VSXU]     = 0x00000F40;
3252    /* Hardware reset vector */
3253    env->hreset_vector = 0x0000000000000100ULL;
3254#endif
3255}
3256
3257static void init_excp_POWER8(CPUPPCState *env)
3258{
3259    init_excp_POWER7(env);
3260
3261#if !defined(CONFIG_USER_ONLY)
3262    env->excp_vectors[POWERPC_EXCP_SDOOR]    = 0x00000A00;
3263    env->excp_vectors[POWERPC_EXCP_FU]       = 0x00000F60;
3264    env->excp_vectors[POWERPC_EXCP_HV_FU]    = 0x00000F80;
3265    env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80;
3266#endif
3267}
3268
3269#endif
3270
3271/*****************************************************************************/
3272/* Power management enable checks                                            */
3273static int check_pow_none(CPUPPCState *env)
3274{
3275    return 0;
3276}
3277
3278static int check_pow_nocheck(CPUPPCState *env)
3279{
3280    return 1;
3281}
3282
3283static int check_pow_hid0(CPUPPCState *env)
3284{
3285    if (env->spr[SPR_HID0] & 0x00E00000)
3286        return 1;
3287
3288    return 0;
3289}
3290
3291static int check_pow_hid0_74xx(CPUPPCState *env)
3292{
3293    if (env->spr[SPR_HID0] & 0x00600000)
3294        return 1;
3295
3296    return 0;
3297}
3298
3299static bool ppc_cpu_interrupts_big_endian_always(PowerPCCPU *cpu)
3300{
3301    return true;
3302}
3303
3304#ifdef TARGET_PPC64
3305static bool ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU *cpu)
3306{
3307    return !(cpu->env.spr[SPR_LPCR] & LPCR_ILE);
3308}
3309#endif
3310
3311/*****************************************************************************/
3312/* PowerPC implementations definitions                                       */
3313
3314#define POWERPC_FAMILY(_name)                                               \
3315    static void                                                             \
3316    glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
3317                                                                            \
3318    static const TypeInfo                                                   \
3319    glue(glue(ppc_, _name), _cpu_family_type_info) = {                      \
3320        .name = stringify(_name) "-family-" TYPE_POWERPC_CPU,               \
3321        .parent = TYPE_POWERPC_CPU,                                         \
3322        .abstract = true,                                                   \
3323        .class_init = glue(glue(ppc_, _name), _cpu_family_class_init),      \
3324    };                                                                      \
3325                                                                            \
3326    static void glue(glue(ppc_, _name), _cpu_family_register_types)(void)   \
3327    {                                                                       \
3328        type_register_static(                                               \
3329            &glue(glue(ppc_, _name), _cpu_family_type_info));               \
3330    }                                                                       \
3331                                                                            \
3332    type_init(glue(glue(ppc_, _name), _cpu_family_register_types))          \
3333                                                                            \
3334    static void glue(glue(ppc_, _name), _cpu_family_class_init)
3335
3336static void init_proc_401(CPUPPCState *env)
3337{
3338    gen_spr_40x(env);
3339    gen_spr_401_403(env);
3340    gen_spr_401(env);
3341    init_excp_4xx_real(env);
3342    env->dcache_line_size = 32;
3343    env->icache_line_size = 32;
3344    /* Allocate hardware IRQ controller */
3345    ppc40x_irq_init(ppc_env_get_cpu(env));
3346
3347    SET_FIT_PERIOD(12, 16, 20, 24);
3348    SET_WDT_PERIOD(16, 20, 24, 28);
3349}
3350
3351POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
3352{
3353    DeviceClass *dc = DEVICE_CLASS(oc);
3354    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3355
3356    dc->desc = "PowerPC 401";
3357    pcc->init_proc = init_proc_401;
3358    pcc->check_pow = check_pow_nocheck;
3359    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3360                       PPC_WRTEE | PPC_DCR |
3361                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3362                       PPC_CACHE_DCBZ |
3363                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3364                       PPC_4xx_COMMON | PPC_40x_EXCP;
3365    pcc->msr_mask = (1ull << MSR_KEY) |
3366                    (1ull << MSR_POW) |
3367                    (1ull << MSR_CE) |
3368                    (1ull << MSR_ILE) |
3369                    (1ull << MSR_EE) |
3370                    (1ull << MSR_PR) |
3371                    (1ull << MSR_ME) |
3372                    (1ull << MSR_DE) |
3373                    (1ull << MSR_LE);
3374    pcc->mmu_model = POWERPC_MMU_REAL;
3375    pcc->excp_model = POWERPC_EXCP_40x;
3376    pcc->bus_model = PPC_FLAGS_INPUT_401;
3377    pcc->bfd_mach = bfd_mach_ppc_403;
3378    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3379                 POWERPC_FLAG_BUS_CLK;
3380}
3381
3382static void init_proc_401x2(CPUPPCState *env)
3383{
3384    gen_spr_40x(env);
3385    gen_spr_401_403(env);
3386    gen_spr_401x2(env);
3387    gen_spr_compress(env);
3388    /* Memory management */
3389#if !defined(CONFIG_USER_ONLY)
3390    env->nb_tlb = 64;
3391    env->nb_ways = 1;
3392    env->id_tlbs = 0;
3393    env->tlb_type = TLB_EMB;
3394#endif
3395    init_excp_4xx_softmmu(env);
3396    env->dcache_line_size = 32;
3397    env->icache_line_size = 32;
3398    /* Allocate hardware IRQ controller */
3399    ppc40x_irq_init(ppc_env_get_cpu(env));
3400
3401    SET_FIT_PERIOD(12, 16, 20, 24);
3402    SET_WDT_PERIOD(16, 20, 24, 28);
3403}
3404
3405POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
3406{
3407    DeviceClass *dc = DEVICE_CLASS(oc);
3408    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3409
3410    dc->desc = "PowerPC 401x2";
3411    pcc->init_proc = init_proc_401x2;
3412    pcc->check_pow = check_pow_nocheck;
3413    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3414                       PPC_DCR | PPC_WRTEE |
3415                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3416                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3417                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3418                       PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3419                       PPC_4xx_COMMON | PPC_40x_EXCP;
3420    pcc->msr_mask = (1ull << 20) |
3421                    (1ull << MSR_KEY) |
3422                    (1ull << MSR_POW) |
3423                    (1ull << MSR_CE) |
3424                    (1ull << MSR_ILE) |
3425                    (1ull << MSR_EE) |
3426                    (1ull << MSR_PR) |
3427                    (1ull << MSR_ME) |
3428                    (1ull << MSR_DE) |
3429                    (1ull << MSR_IR) |
3430                    (1ull << MSR_DR) |
3431                    (1ull << MSR_LE);
3432    pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3433    pcc->excp_model = POWERPC_EXCP_40x;
3434    pcc->bus_model = PPC_FLAGS_INPUT_401;
3435    pcc->bfd_mach = bfd_mach_ppc_403;
3436    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3437                 POWERPC_FLAG_BUS_CLK;
3438}
3439
3440static void init_proc_401x3(CPUPPCState *env)
3441{
3442    gen_spr_40x(env);
3443    gen_spr_401_403(env);
3444    gen_spr_401(env);
3445    gen_spr_401x2(env);
3446    gen_spr_compress(env);
3447    init_excp_4xx_softmmu(env);
3448    env->dcache_line_size = 32;
3449    env->icache_line_size = 32;
3450    /* Allocate hardware IRQ controller */
3451    ppc40x_irq_init(ppc_env_get_cpu(env));
3452
3453    SET_FIT_PERIOD(12, 16, 20, 24);
3454    SET_WDT_PERIOD(16, 20, 24, 28);
3455}
3456
3457POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
3458{
3459    DeviceClass *dc = DEVICE_CLASS(oc);
3460    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3461
3462    dc->desc = "PowerPC 401x3";
3463    pcc->init_proc = init_proc_401x3;
3464    pcc->check_pow = check_pow_nocheck;
3465    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3466                       PPC_DCR | PPC_WRTEE |
3467                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3468                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3469                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3470                       PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3471                       PPC_4xx_COMMON | PPC_40x_EXCP;
3472    pcc->msr_mask = (1ull << 20) |
3473                    (1ull << MSR_KEY) |
3474                    (1ull << MSR_POW) |
3475                    (1ull << MSR_CE) |
3476                    (1ull << MSR_ILE) |
3477                    (1ull << MSR_EE) |
3478                    (1ull << MSR_PR) |
3479                    (1ull << MSR_ME) |
3480                    (1ull << MSR_DWE) |
3481                    (1ull << MSR_DE) |
3482                    (1ull << MSR_IR) |
3483                    (1ull << MSR_DR) |
3484                    (1ull << MSR_LE);
3485    pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3486    pcc->excp_model = POWERPC_EXCP_40x;
3487    pcc->bus_model = PPC_FLAGS_INPUT_401;
3488    pcc->bfd_mach = bfd_mach_ppc_403;
3489    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3490                 POWERPC_FLAG_BUS_CLK;
3491}
3492
3493static void init_proc_IOP480(CPUPPCState *env)
3494{
3495    gen_spr_40x(env);
3496    gen_spr_401_403(env);
3497    gen_spr_401x2(env);
3498    gen_spr_compress(env);
3499    /* Memory management */
3500#if !defined(CONFIG_USER_ONLY)
3501    env->nb_tlb = 64;
3502    env->nb_ways = 1;
3503    env->id_tlbs = 0;
3504    env->tlb_type = TLB_EMB;
3505#endif
3506    init_excp_4xx_softmmu(env);
3507    env->dcache_line_size = 32;
3508    env->icache_line_size = 32;
3509    /* Allocate hardware IRQ controller */
3510    ppc40x_irq_init(ppc_env_get_cpu(env));
3511
3512    SET_FIT_PERIOD(8, 12, 16, 20);
3513    SET_WDT_PERIOD(16, 20, 24, 28);
3514}
3515
3516POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
3517{
3518    DeviceClass *dc = DEVICE_CLASS(oc);
3519    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3520
3521    dc->desc = "IOP480";
3522    pcc->init_proc = init_proc_IOP480;
3523    pcc->check_pow = check_pow_nocheck;
3524    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3525                       PPC_DCR | PPC_WRTEE |
3526                       PPC_CACHE | PPC_CACHE_ICBI |  PPC_40x_ICBT |
3527                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3528                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3529                       PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3530                       PPC_4xx_COMMON | PPC_40x_EXCP;
3531    pcc->msr_mask = (1ull << 20) |
3532                    (1ull << MSR_KEY) |
3533                    (1ull << MSR_POW) |
3534                    (1ull << MSR_CE) |
3535                    (1ull << MSR_ILE) |
3536                    (1ull << MSR_EE) |
3537                    (1ull << MSR_PR) |
3538                    (1ull << MSR_ME) |
3539                    (1ull << MSR_DE) |
3540                    (1ull << MSR_IR) |
3541                    (1ull << MSR_DR) |
3542                    (1ull << MSR_LE);
3543    pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3544    pcc->excp_model = POWERPC_EXCP_40x;
3545    pcc->bus_model = PPC_FLAGS_INPUT_401;
3546    pcc->bfd_mach = bfd_mach_ppc_403;
3547    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3548                 POWERPC_FLAG_BUS_CLK;
3549}
3550
3551static void init_proc_403(CPUPPCState *env)
3552{
3553    gen_spr_40x(env);
3554    gen_spr_401_403(env);
3555    gen_spr_403(env);
3556    gen_spr_403_real(env);
3557    init_excp_4xx_real(env);
3558    env->dcache_line_size = 32;
3559    env->icache_line_size = 32;
3560    /* Allocate hardware IRQ controller */
3561    ppc40x_irq_init(ppc_env_get_cpu(env));
3562
3563    SET_FIT_PERIOD(8, 12, 16, 20);
3564    SET_WDT_PERIOD(16, 20, 24, 28);
3565}
3566
3567POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
3568{
3569    DeviceClass *dc = DEVICE_CLASS(oc);
3570    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3571
3572    dc->desc = "PowerPC 403";
3573    pcc->init_proc = init_proc_403;
3574    pcc->check_pow = check_pow_nocheck;
3575    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3576                       PPC_DCR | PPC_WRTEE |
3577                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3578                       PPC_CACHE_DCBZ |
3579                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3580                       PPC_4xx_COMMON | PPC_40x_EXCP;
3581    pcc->msr_mask = (1ull << MSR_POW) |
3582                    (1ull << MSR_CE) |
3583                    (1ull << MSR_ILE) |
3584                    (1ull << MSR_EE) |
3585                    (1ull << MSR_PR) |
3586                    (1ull << MSR_ME) |
3587                    (1ull << MSR_PE) |
3588                    (1ull << MSR_PX) |
3589                    (1ull << MSR_LE);
3590    pcc->mmu_model = POWERPC_MMU_REAL;
3591    pcc->excp_model = POWERPC_EXCP_40x;
3592    pcc->bus_model = PPC_FLAGS_INPUT_401;
3593    pcc->bfd_mach = bfd_mach_ppc_403;
3594    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3595                 POWERPC_FLAG_BUS_CLK;
3596}
3597
3598static void init_proc_403GCX(CPUPPCState *env)
3599{
3600    gen_spr_40x(env);
3601    gen_spr_401_403(env);
3602    gen_spr_403(env);
3603    gen_spr_403_real(env);
3604    gen_spr_403_mmu(env);
3605    /* Bus access control */
3606    /* not emulated, as QEMU never does speculative access */
3607    spr_register(env, SPR_40x_SGR, "SGR",
3608                 SPR_NOACCESS, SPR_NOACCESS,
3609                 &spr_read_generic, &spr_write_generic,
3610                 0xFFFFFFFF);
3611    /* not emulated, as QEMU do not emulate caches */
3612    spr_register(env, SPR_40x_DCWR, "DCWR",
3613                 SPR_NOACCESS, SPR_NOACCESS,
3614                 &spr_read_generic, &spr_write_generic,
3615                 0x00000000);
3616    /* Memory management */
3617#if !defined(CONFIG_USER_ONLY)
3618    env->nb_tlb = 64;
3619    env->nb_ways = 1;
3620    env->id_tlbs = 0;
3621    env->tlb_type = TLB_EMB;
3622#endif
3623    init_excp_4xx_softmmu(env);
3624    env->dcache_line_size = 32;
3625    env->icache_line_size = 32;
3626    /* Allocate hardware IRQ controller */
3627    ppc40x_irq_init(ppc_env_get_cpu(env));
3628
3629    SET_FIT_PERIOD(8, 12, 16, 20);
3630    SET_WDT_PERIOD(16, 20, 24, 28);
3631}
3632
3633POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
3634{
3635    DeviceClass *dc = DEVICE_CLASS(oc);
3636    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3637
3638    dc->desc = "PowerPC 403 GCX";
3639    pcc->init_proc = init_proc_403GCX;
3640    pcc->check_pow = check_pow_nocheck;
3641    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3642                       PPC_DCR | PPC_WRTEE |
3643                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3644                       PPC_CACHE_DCBZ |
3645                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3646                       PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3647                       PPC_4xx_COMMON | PPC_40x_EXCP;
3648    pcc->msr_mask = (1ull << MSR_POW) |
3649                    (1ull << MSR_CE) |
3650                    (1ull << MSR_ILE) |
3651                    (1ull << MSR_EE) |
3652                    (1ull << MSR_PR) |
3653                    (1ull << MSR_ME) |
3654                    (1ull << MSR_PE) |
3655                    (1ull << MSR_PX) |
3656                    (1ull << MSR_LE);
3657    pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3658    pcc->excp_model = POWERPC_EXCP_40x;
3659    pcc->bus_model = PPC_FLAGS_INPUT_401;
3660    pcc->bfd_mach = bfd_mach_ppc_403;
3661    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3662                 POWERPC_FLAG_BUS_CLK;
3663}
3664
3665static void init_proc_405(CPUPPCState *env)
3666{
3667    /* Time base */
3668    gen_tbl(env);
3669    gen_spr_40x(env);
3670    gen_spr_405(env);
3671    /* Bus access control */
3672    /* not emulated, as QEMU never does speculative access */
3673    spr_register(env, SPR_40x_SGR, "SGR",
3674                 SPR_NOACCESS, SPR_NOACCESS,
3675                 &spr_read_generic, &spr_write_generic,
3676                 0xFFFFFFFF);
3677    /* not emulated, as QEMU do not emulate caches */
3678    spr_register(env, SPR_40x_DCWR, "DCWR",
3679                 SPR_NOACCESS, SPR_NOACCESS,
3680                 &spr_read_generic, &spr_write_generic,
3681                 0x00000000);
3682    /* Memory management */
3683#if !defined(CONFIG_USER_ONLY)
3684    env->nb_tlb = 64;
3685    env->nb_ways = 1;
3686    env->id_tlbs = 0;
3687    env->tlb_type = TLB_EMB;
3688#endif
3689    init_excp_4xx_softmmu(env);
3690    env->dcache_line_size = 32;
3691    env->icache_line_size = 32;
3692    /* Allocate hardware IRQ controller */
3693    ppc40x_irq_init(ppc_env_get_cpu(env));
3694
3695    SET_FIT_PERIOD(8, 12, 16, 20);
3696    SET_WDT_PERIOD(16, 20, 24, 28);
3697}
3698
3699POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
3700{
3701    DeviceClass *dc = DEVICE_CLASS(oc);
3702    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3703
3704    dc->desc = "PowerPC 405";
3705    pcc->init_proc = init_proc_405;
3706    pcc->check_pow = check_pow_nocheck;
3707    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3708                       PPC_DCR | PPC_WRTEE |
3709                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3710                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3711                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3712                       PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3713                       PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
3714    pcc->msr_mask = (1ull << MSR_POW) |
3715                    (1ull << MSR_CE) |
3716                    (1ull << MSR_EE) |
3717                    (1ull << MSR_PR) |
3718                    (1ull << MSR_FP) |
3719                    (1ull << MSR_DWE) |
3720                    (1ull << MSR_DE) |
3721                    (1ull << MSR_IR) |
3722                    (1ull << MSR_DR);
3723    pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
3724    pcc->excp_model = POWERPC_EXCP_40x;
3725    pcc->bus_model = PPC_FLAGS_INPUT_405;
3726    pcc->bfd_mach = bfd_mach_ppc_403;
3727    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3728                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3729}
3730
3731static void init_proc_440EP(CPUPPCState *env)
3732{
3733    /* Time base */
3734    gen_tbl(env);
3735    gen_spr_BookE(env, 0x000000000000FFFFULL);
3736    gen_spr_440(env);
3737    gen_spr_usprgh(env);
3738    /* Processor identification */
3739    spr_register(env, SPR_BOOKE_PIR, "PIR",
3740                 SPR_NOACCESS, SPR_NOACCESS,
3741                 &spr_read_generic, &spr_write_pir,
3742                 0x00000000);
3743    /* XXX : not implemented */
3744    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3745                 SPR_NOACCESS, SPR_NOACCESS,
3746                 &spr_read_generic, &spr_write_generic,
3747                 0x00000000);
3748    /* XXX : not implemented */
3749    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3750                 SPR_NOACCESS, SPR_NOACCESS,
3751                 &spr_read_generic, &spr_write_generic,
3752                 0x00000000);
3753    /* XXX : not implemented */
3754    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3755                 SPR_NOACCESS, SPR_NOACCESS,
3756                 &spr_read_generic, &spr_write_generic,
3757                 0x00000000);
3758    /* XXX : not implemented */
3759    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3760                 SPR_NOACCESS, SPR_NOACCESS,
3761                 &spr_read_generic, &spr_write_generic,
3762                 0x00000000);
3763    /* XXX : not implemented */
3764    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3765                 SPR_NOACCESS, SPR_NOACCESS,
3766                 &spr_read_generic, &spr_write_generic,
3767                 0x00000000);
3768    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3769                 SPR_NOACCESS, SPR_NOACCESS,
3770                 &spr_read_generic, &spr_write_generic,
3771                 0x00000000);
3772    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3773                 SPR_NOACCESS, SPR_NOACCESS,
3774                 &spr_read_generic, &spr_write_generic,
3775                 0x00000000);
3776    /* XXX : not implemented */
3777    spr_register(env, SPR_440_CCR1, "CCR1",
3778                 SPR_NOACCESS, SPR_NOACCESS,
3779                 &spr_read_generic, &spr_write_generic,
3780                 0x00000000);
3781    /* Memory management */
3782#if !defined(CONFIG_USER_ONLY)
3783    env->nb_tlb = 64;
3784    env->nb_ways = 1;
3785    env->id_tlbs = 0;
3786    env->tlb_type = TLB_EMB;
3787#endif
3788    init_excp_BookE(env);
3789    env->dcache_line_size = 32;
3790    env->icache_line_size = 32;
3791    ppc40x_irq_init(ppc_env_get_cpu(env));
3792
3793    SET_FIT_PERIOD(12, 16, 20, 24);
3794    SET_WDT_PERIOD(20, 24, 28, 32);
3795}
3796
3797POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
3798{
3799    DeviceClass *dc = DEVICE_CLASS(oc);
3800    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3801
3802    dc->desc = "PowerPC 440 EP";
3803    pcc->init_proc = init_proc_440EP;
3804    pcc->check_pow = check_pow_nocheck;
3805    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3806                       PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3807                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3808                       PPC_FLOAT_STFIWX |
3809                       PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3810                       PPC_CACHE | PPC_CACHE_ICBI |
3811                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3812                       PPC_MEM_TLBSYNC | PPC_MFTB |
3813                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3814                       PPC_440_SPEC;
3815    pcc->msr_mask = (1ull << MSR_POW) |
3816                    (1ull << MSR_CE) |
3817                    (1ull << MSR_EE) |
3818                    (1ull << MSR_PR) |
3819                    (1ull << MSR_FP) |
3820                    (1ull << MSR_ME) |
3821                    (1ull << MSR_FE0) |
3822                    (1ull << MSR_DWE) |
3823                    (1ull << MSR_DE) |
3824                    (1ull << MSR_FE1) |
3825                    (1ull << MSR_IR) |
3826                    (1ull << MSR_DR);
3827    pcc->mmu_model = POWERPC_MMU_BOOKE;
3828    pcc->excp_model = POWERPC_EXCP_BOOKE;
3829    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3830    pcc->bfd_mach = bfd_mach_ppc_403;
3831    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3832                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3833}
3834
3835static void init_proc_440GP(CPUPPCState *env)
3836{
3837    /* Time base */
3838    gen_tbl(env);
3839    gen_spr_BookE(env, 0x000000000000FFFFULL);
3840    gen_spr_440(env);
3841    gen_spr_usprgh(env);
3842    /* Processor identification */
3843    spr_register(env, SPR_BOOKE_PIR, "PIR",
3844                 SPR_NOACCESS, SPR_NOACCESS,
3845                 &spr_read_generic, &spr_write_pir,
3846                 0x00000000);
3847    /* XXX : not implemented */
3848    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3849                 SPR_NOACCESS, SPR_NOACCESS,
3850                 &spr_read_generic, &spr_write_generic,
3851                 0x00000000);
3852    /* XXX : not implemented */
3853    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3854                 SPR_NOACCESS, SPR_NOACCESS,
3855                 &spr_read_generic, &spr_write_generic,
3856                 0x00000000);
3857    /* XXX : not implemented */
3858    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3859                 SPR_NOACCESS, SPR_NOACCESS,
3860                 &spr_read_generic, &spr_write_generic,
3861                 0x00000000);
3862    /* XXX : not implemented */
3863    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3864                 SPR_NOACCESS, SPR_NOACCESS,
3865                 &spr_read_generic, &spr_write_generic,
3866                 0x00000000);
3867    /* Memory management */
3868#if !defined(CONFIG_USER_ONLY)
3869    env->nb_tlb = 64;
3870    env->nb_ways = 1;
3871    env->id_tlbs = 0;
3872    env->tlb_type = TLB_EMB;
3873#endif
3874    init_excp_BookE(env);
3875    env->dcache_line_size = 32;
3876    env->icache_line_size = 32;
3877    /* XXX: TODO: allocate internal IRQ controller */
3878
3879    SET_FIT_PERIOD(12, 16, 20, 24);
3880    SET_WDT_PERIOD(20, 24, 28, 32);
3881}
3882
3883POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
3884{
3885    DeviceClass *dc = DEVICE_CLASS(oc);
3886    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3887
3888    dc->desc = "PowerPC 440 GP";
3889    pcc->init_proc = init_proc_440GP;
3890    pcc->check_pow = check_pow_nocheck;
3891    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3892                       PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
3893                       PPC_CACHE | PPC_CACHE_ICBI |
3894                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3895                       PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
3896                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3897                       PPC_440_SPEC;
3898    pcc->msr_mask = (1ull << MSR_POW) |
3899                    (1ull << MSR_CE) |
3900                    (1ull << MSR_EE) |
3901                    (1ull << MSR_PR) |
3902                    (1ull << MSR_FP) |
3903                    (1ull << MSR_ME) |
3904                    (1ull << MSR_FE0) |
3905                    (1ull << MSR_DWE) |
3906                    (1ull << MSR_DE) |
3907                    (1ull << MSR_FE1) |
3908                    (1ull << MSR_IR) |
3909                    (1ull << MSR_DR);
3910    pcc->mmu_model = POWERPC_MMU_BOOKE;
3911    pcc->excp_model = POWERPC_EXCP_BOOKE;
3912    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3913    pcc->bfd_mach = bfd_mach_ppc_403;
3914    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3915                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3916}
3917
3918static void init_proc_440x4(CPUPPCState *env)
3919{
3920    /* Time base */
3921    gen_tbl(env);
3922    gen_spr_BookE(env, 0x000000000000FFFFULL);
3923    gen_spr_440(env);
3924    gen_spr_usprgh(env);
3925    /* Processor identification */
3926    spr_register(env, SPR_BOOKE_PIR, "PIR",
3927                 SPR_NOACCESS, SPR_NOACCESS,
3928                 &spr_read_generic, &spr_write_pir,
3929                 0x00000000);
3930    /* XXX : not implemented */
3931    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3932                 SPR_NOACCESS, SPR_NOACCESS,
3933                 &spr_read_generic, &spr_write_generic,
3934                 0x00000000);
3935    /* XXX : not implemented */
3936    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3937                 SPR_NOACCESS, SPR_NOACCESS,
3938                 &spr_read_generic, &spr_write_generic,
3939                 0x00000000);
3940    /* XXX : not implemented */
3941    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3942                 SPR_NOACCESS, SPR_NOACCESS,
3943                 &spr_read_generic, &spr_write_generic,
3944                 0x00000000);
3945    /* XXX : not implemented */
3946    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3947                 SPR_NOACCESS, SPR_NOACCESS,
3948                 &spr_read_generic, &spr_write_generic,
3949                 0x00000000);
3950    /* Memory management */
3951#if !defined(CONFIG_USER_ONLY)
3952    env->nb_tlb = 64;
3953    env->nb_ways = 1;
3954    env->id_tlbs = 0;
3955    env->tlb_type = TLB_EMB;
3956#endif
3957    init_excp_BookE(env);
3958    env->dcache_line_size = 32;
3959    env->icache_line_size = 32;
3960    /* XXX: TODO: allocate internal IRQ controller */
3961
3962    SET_FIT_PERIOD(12, 16, 20, 24);
3963    SET_WDT_PERIOD(20, 24, 28, 32);
3964}
3965
3966POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
3967{
3968    DeviceClass *dc = DEVICE_CLASS(oc);
3969    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3970
3971    dc->desc = "PowerPC 440x4";
3972    pcc->init_proc = init_proc_440x4;
3973    pcc->check_pow = check_pow_nocheck;
3974    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3975                       PPC_DCR | PPC_WRTEE |
3976                       PPC_CACHE | PPC_CACHE_ICBI |
3977                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3978                       PPC_MEM_TLBSYNC | PPC_MFTB |
3979                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3980                       PPC_440_SPEC;
3981    pcc->msr_mask = (1ull << MSR_POW) |
3982                    (1ull << MSR_CE) |
3983                    (1ull << MSR_EE) |
3984                    (1ull << MSR_PR) |
3985                    (1ull << MSR_FP) |
3986                    (1ull << MSR_ME) |
3987                    (1ull << MSR_FE0) |
3988                    (1ull << MSR_DWE) |
3989                    (1ull << MSR_DE) |
3990                    (1ull << MSR_FE1) |
3991                    (1ull << MSR_IR) |
3992                    (1ull << MSR_DR);
3993    pcc->mmu_model = POWERPC_MMU_BOOKE;
3994    pcc->excp_model = POWERPC_EXCP_BOOKE;
3995    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3996    pcc->bfd_mach = bfd_mach_ppc_403;
3997    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3998                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3999}
4000

4001static void init_proc_440x5(CPUPPCState *env)
4002{
4003    /* Time base */
4004    gen_tbl(env);
4005    gen_spr_BookE(env, 0x000000000000FFFFULL);
4006    gen_spr_440(env);
4007    gen_spr_usprgh(env);
4008    /* Processor identification */
4009    spr_register(env, SPR_BOOKE_PIR, "PIR",
4010                 SPR_NOACCESS, SPR_NOACCESS,
4011                 &spr_read_generic, &spr_write_pir,
4012                 0x00000000);
4013    /* XXX : not implemented */
4014    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4015                 SPR_NOACCESS, SPR_NOACCESS,
4016                 &spr_read_generic, &spr_write_generic,
4017                 0x00000000);
4018    /* XXX : not implemented */
4019    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4020                 SPR_NOACCESS, SPR_NOACCESS,
4021                 &spr_read_generic, &spr_write_generic,
4022                 0x00000000);
4023    /* XXX : not implemented */
4024    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4025                 SPR_NOACCESS, SPR_NOACCESS,
4026                 &spr_read_generic, &spr_write_generic,
4027                 0x00000000);
4028    /* XXX : not implemented */
4029    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4030                 SPR_NOACCESS, SPR_NOACCESS,
4031                 &spr_read_generic, &spr_write_generic,
4032                 0x00000000);
4033    /* XXX : not implemented */
4034    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4035                 SPR_NOACCESS, SPR_NOACCESS,
4036                 &spr_read_generic, &spr_write_generic,
4037                 0x00000000);
4038    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4039                 SPR_NOACCESS, SPR_NOACCESS,
4040                 &spr_read_generic, &spr_write_generic,
4041                 0x00000000);
4042    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4043                 SPR_NOACCESS, SPR_NOACCESS,
4044                 &spr_read_generic, &spr_write_generic,
4045                 0x00000000);
4046    /* XXX : not implemented */
4047    spr_register(env, SPR_440_CCR1, "CCR1",
4048                 SPR_NOACCESS, SPR_NOACCESS,
4049                 &spr_read_generic, &spr_write_generic,
4050                 0x00000000);
4051    /* Memory management */
4052#if !defined(CONFIG_USER_ONLY)
4053    env->nb_tlb = 64;
4054    env->nb_ways = 1;
4055    env->id_tlbs = 0;
4056    env->tlb_type = TLB_EMB;
4057#endif
4058    init_excp_BookE(env);
4059    env->dcache_line_size = 32;
4060    env->icache_line_size = 32;
4061    ppc40x_irq_init(ppc_env_get_cpu(env));
4062
4063    SET_FIT_PERIOD(12, 16, 20, 24);
4064    SET_WDT_PERIOD(20, 24, 28, 32);
4065}
4066
4067POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
4068{
4069    DeviceClass *dc = DEVICE_CLASS(oc);
4070    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4071
4072    dc->desc = "PowerPC 440x5";
4073    pcc->init_proc = init_proc_440x5;
4074    pcc->check_pow = check_pow_nocheck;
4075    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4076                       PPC_DCR | PPC_WRTEE | PPC_RFMCI |
4077                       PPC_CACHE | PPC_CACHE_ICBI |
4078                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4079                       PPC_MEM_TLBSYNC | PPC_MFTB |
4080                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4081                       PPC_440_SPEC;
4082    pcc->msr_mask = (1ull << MSR_POW) |
4083                    (1ull << MSR_CE) |
4084                    (1ull << MSR_EE) |
4085                    (1ull << MSR_PR) |
4086                    (1ull << MSR_FP) |
4087                    (1ull << MSR_ME) |
4088                    (1ull << MSR_FE0) |
4089                    (1ull << MSR_DWE) |
4090                    (1ull << MSR_DE) |
4091                    (1ull << MSR_FE1) |
4092                    (1ull << MSR_IR) |
4093                    (1ull << MSR_DR);
4094    pcc->mmu_model = POWERPC_MMU_BOOKE;
4095    pcc->excp_model = POWERPC_EXCP_BOOKE;
4096    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4097    pcc->bfd_mach = bfd_mach_ppc_403;
4098    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4099                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4100}
4101
4102POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
4103{
4104    DeviceClass *dc = DEVICE_CLASS(oc);
4105    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4106
4107    dc->desc = "PowerPC 440x5 with double precision FPU";
4108    pcc->init_proc = init_proc_440x5;
4109    pcc->check_pow = check_pow_nocheck;
4110    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4111                       PPC_FLOAT | PPC_FLOAT_FSQRT |
4112                       PPC_FLOAT_STFIWX |
4113                       PPC_DCR | PPC_WRTEE | PPC_RFMCI |
4114                       PPC_CACHE | PPC_CACHE_ICBI |
4115                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4116                       PPC_MEM_TLBSYNC | PPC_MFTB |
4117                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4118                       PPC_440_SPEC;
4119    pcc->insns_flags2 = PPC2_FP_CVT_S64;
4120    pcc->msr_mask = (1ull << MSR_POW) |
4121                    (1ull << MSR_CE) |
4122                    (1ull << MSR_EE) |
4123                    (1ull << MSR_PR) |
4124                    (1ull << MSR_FP) |
4125                    (1ull << MSR_ME) |
4126                    (1ull << MSR_FE0) |
4127                    (1ull << MSR_DWE) |
4128                    (1ull << MSR_DE) |
4129                    (1ull << MSR_FE1) |
4130                    (1ull << MSR_IR) |
4131                    (1ull << MSR_DR);
4132    pcc->mmu_model = POWERPC_MMU_BOOKE;
4133    pcc->excp_model = POWERPC_EXCP_BOOKE;
4134    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4135    pcc->bfd_mach = bfd_mach_ppc_403;
4136    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4137                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4138}
4139
4140static void init_proc_460 (CPUPPCState *env)
4141{
4142    /* Time base */
4143    gen_tbl(env);
4144    gen_spr_BookE(env, 0x000000000000FFFFULL);
4145    gen_spr_440(env);
4146    gen_spr_usprgh(env);
4147    /* Processor identification */
4148    spr_register(env, SPR_BOOKE_PIR, "PIR",
4149                 SPR_NOACCESS, SPR_NOACCESS,
4150                 &spr_read_generic, &spr_write_pir,
4151                 0x00000000);
4152    /* XXX : not implemented */
4153    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4154                 SPR_NOACCESS, SPR_NOACCESS,
4155                 &spr_read_generic, &spr_write_generic,
4156                 0x00000000);
4157    /* XXX : not implemented */
4158    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4159                 SPR_NOACCESS, SPR_NOACCESS,
4160                 &spr_read_generic, &spr_write_generic,
4161                 0x00000000);
4162    /* XXX : not implemented */
4163    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4164                 SPR_NOACCESS, SPR_NOACCESS,
4165                 &spr_read_generic, &spr_write_generic,
4166                 0x00000000);
4167    /* XXX : not implemented */
4168    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4169                 SPR_NOACCESS, SPR_NOACCESS,
4170                 &spr_read_generic, &spr_write_generic,
4171                 0x00000000);
4172    /* XXX : not implemented */
4173    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4174                 SPR_NOACCESS, SPR_NOACCESS,
4175                 &spr_read_generic, &spr_write_generic,
4176                 0x00000000);
4177    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4178                 SPR_NOACCESS, SPR_NOACCESS,
4179                 &spr_read_generic, &spr_write_generic,
4180                 0x00000000);
4181    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4182                 SPR_NOACCESS, SPR_NOACCESS,
4183                 &spr_read_generic, &spr_write_generic,
4184                 0x00000000);
4185    /* XXX : not implemented */
4186    spr_register(env, SPR_440_CCR1, "CCR1",
4187                 SPR_NOACCESS, SPR_NOACCESS,
4188                 &spr_read_generic, &spr_write_generic,
4189                 0x00000000);
4190    /* XXX : not implemented */
4191    spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
4192                 &spr_read_generic, &spr_write_generic,
4193                 &spr_read_generic, &spr_write_generic,
4194                 0x00000000);
4195    /* Memory management */
4196#if !defined(CONFIG_USER_ONLY)
4197    env->nb_tlb = 64;
4198    env->nb_ways = 1;
4199    env->id_tlbs = 0;
4200    env->tlb_type = TLB_EMB;
4201#endif
4202    init_excp_BookE(env);
4203    env->dcache_line_size = 32;
4204    env->icache_line_size = 32;
4205    /* XXX: TODO: allocate internal IRQ controller */
4206
4207    SET_FIT_PERIOD(12, 16, 20, 24);
4208    SET_WDT_PERIOD(20, 24, 28, 32);
4209}
4210
4211POWERPC_FAMILY(460)(ObjectClass *oc, void *data)
4212{
4213    DeviceClass *dc = DEVICE_CLASS(oc);
4214    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4215
4216    dc->desc = "PowerPC 460 (guessed)";
4217    pcc->init_proc = init_proc_460;
4218    pcc->check_pow = check_pow_nocheck;
4219    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4220                       PPC_DCR | PPC_DCRX  | PPC_DCRUX |
4221                       PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB |
4222                       PPC_CACHE | PPC_CACHE_ICBI |
4223                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4224                       PPC_MEM_TLBSYNC | PPC_TLBIVA |
4225                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4226                       PPC_440_SPEC;
4227    pcc->msr_mask = (1ull << MSR_POW) |
4228                    (1ull << MSR_CE) |
4229                    (1ull << MSR_EE) |
4230                    (1ull << MSR_PR) |
4231                    (1ull << MSR_FP) |
4232                    (1ull << MSR_ME) |
4233                    (1ull << MSR_FE0) |
4234                    (1ull << MSR_DWE) |
4235                    (1ull << MSR_DE) |
4236                    (1ull << MSR_FE1) |
4237                    (1ull << MSR_IR) |
4238                    (1ull << MSR_DR);
4239    pcc->mmu_model = POWERPC_MMU_BOOKE;
4240    pcc->excp_model = POWERPC_EXCP_BOOKE;
4241    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4242    pcc->bfd_mach = bfd_mach_ppc_403;
4243    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4244                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4245}
4246
4247static void init_proc_460F(CPUPPCState *env)
4248{
4249    /* Time base */
4250    gen_tbl(env);
4251    gen_spr_BookE(env, 0x000000000000FFFFULL);
4252    gen_spr_440(env);
4253    gen_spr_usprgh(env);
4254    /* Processor identification */
4255    spr_register(env, SPR_BOOKE_PIR, "PIR",
4256                 SPR_NOACCESS, SPR_NOACCESS,
4257                 &spr_read_generic, &spr_write_pir,
4258                 0x00000000);
4259    /* XXX : not implemented */
4260    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4261                 SPR_NOACCESS, SPR_NOACCESS,
4262                 &spr_read_generic, &spr_write_generic,
4263                 0x00000000);
4264    /* XXX : not implemented */
4265    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4266                 SPR_NOACCESS, SPR_NOACCESS,
4267                 &spr_read_generic, &spr_write_generic,
4268                 0x00000000);
4269    /* XXX : not implemented */
4270    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4271                 SPR_NOACCESS, SPR_NOACCESS,
4272                 &spr_read_generic, &spr_write_generic,
4273                 0x00000000);
4274    /* XXX : not implemented */
4275    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4276                 SPR_NOACCESS, SPR_NOACCESS,
4277                 &spr_read_generic, &spr_write_generic,
4278                 0x00000000);
4279    /* XXX : not implemented */
4280    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4281                 SPR_NOACCESS, SPR_NOACCESS,
4282                 &spr_read_generic, &spr_write_generic,
4283                 0x00000000);
4284    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4285                 SPR_NOACCESS, SPR_NOACCESS,
4286                 &spr_read_generic, &spr_write_generic,
4287                 0x00000000);
4288    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4289                 SPR_NOACCESS, SPR_NOACCESS,
4290                 &spr_read_generic, &spr_write_generic,
4291                 0x00000000);
4292    /* XXX : not implemented */
4293    spr_register(env, SPR_440_CCR1, "CCR1",
4294                 SPR_NOACCESS, SPR_NOACCESS,
4295                 &spr_read_generic, &spr_write_generic,
4296                 0x00000000);
4297    /* XXX : not implemented */
4298    spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
4299                 &spr_read_generic, &spr_write_generic,
4300                 &spr_read_generic, &spr_write_generic,
4301                 0x00000000);
4302    /* Memory management */
4303#if !defined(CONFIG_USER_ONLY)
4304    env->nb_tlb = 64;
4305    env->nb_ways = 1;
4306    env->id_tlbs = 0;
4307    env->tlb_type = TLB_EMB;
4308#endif
4309    init_excp_BookE(env);
4310    env->dcache_line_size = 32;
4311    env->icache_line_size = 32;
4312    /* XXX: TODO: allocate internal IRQ controller */
4313
4314    SET_FIT_PERIOD(12, 16, 20, 24);
4315    SET_WDT_PERIOD(20, 24, 28, 32);
4316}
4317
4318POWERPC_FAMILY(460F)(ObjectClass *oc, void *data)
4319{
4320    DeviceClass *dc = DEVICE_CLASS(oc);
4321    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4322
4323    dc->desc = "PowerPC 460F (guessed)";
4324    pcc->init_proc = init_proc_460F;
4325    pcc->check_pow = check_pow_nocheck;
4326    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4327                       PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
4328                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4329                       PPC_FLOAT_STFIWX | PPC_MFTB |
4330                       PPC_DCR | PPC_DCRX | PPC_DCRUX |
4331                       PPC_WRTEE | PPC_MFAPIDI |
4332                       PPC_CACHE | PPC_CACHE_ICBI |
4333                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4334                       PPC_MEM_TLBSYNC | PPC_TLBIVA |
4335                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4336                       PPC_440_SPEC;
4337    pcc->msr_mask = (1ull << MSR_POW) |
4338                    (1ull << MSR_CE) |
4339                    (1ull << MSR_EE) |
4340                    (1ull << MSR_PR) |
4341                    (1ull << MSR_FP) |
4342                    (1ull << MSR_ME) |
4343                    (1ull << MSR_FE0) |
4344                    (1ull << MSR_DWE) |
4345                    (1ull << MSR_DE) |
4346                    (1ull << MSR_FE1) |
4347                    (1ull << MSR_IR) |
4348                    (1ull << MSR_DR);
4349    pcc->mmu_model = POWERPC_MMU_BOOKE;
4350    pcc->excp_model = POWERPC_EXCP_BOOKE;
4351    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4352    pcc->bfd_mach = bfd_mach_ppc_403;
4353    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4354                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4355}
4356
4357static void init_proc_MPC5xx(CPUPPCState *env)
4358{
4359    /* Time base */
4360    gen_tbl(env);
4361    gen_spr_5xx_8xx(env);
4362    gen_spr_5xx(env);
4363    init_excp_MPC5xx(env);
4364    env->dcache_line_size = 32;
4365    env->icache_line_size = 32;
4366    /* XXX: TODO: allocate internal IRQ controller */
4367}
4368
4369POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
4370{
4371    DeviceClass *dc = DEVICE_CLASS(oc);
4372    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4373
4374    dc->desc = "Freescale 5xx cores (aka RCPU)";
4375    pcc->init_proc = init_proc_MPC5xx;
4376    pcc->check_pow = check_pow_none;
4377    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4378                       PPC_MEM_EIEIO | PPC_MEM_SYNC |
4379                       PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
4380                       PPC_MFTB;
4381    pcc->msr_mask = (1ull << MSR_ILE) |
4382                    (1ull << MSR_EE) |
4383                    (1ull << MSR_PR) |
4384                    (1ull << MSR_FP) |
4385                    (1ull << MSR_ME) |
4386                    (1ull << MSR_FE0) |
4387                    (1ull << MSR_SE) |
4388                    (1ull << MSR_DE) |
4389                    (1ull << MSR_FE1) |
4390                    (1ull << MSR_EP) |
4391                    (1ull << MSR_RI) |
4392                    (1ull << MSR_LE);
4393    pcc->mmu_model = POWERPC_MMU_REAL;
4394    pcc->excp_model = POWERPC_EXCP_603;
4395    pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4396    pcc->bfd_mach = bfd_mach_ppc_505;
4397    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4398                 POWERPC_FLAG_BUS_CLK;
4399}
4400
4401static void init_proc_MPC8xx(CPUPPCState *env)
4402{
4403    /* Time base */
4404    gen_tbl(env);
4405    gen_spr_5xx_8xx(env);
4406    gen_spr_8xx(env);
4407    init_excp_MPC8xx(env);
4408    env->dcache_line_size = 32;
4409    env->icache_line_size = 32;
4410    /* XXX: TODO: allocate internal IRQ controller */
4411}
4412
4413POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
4414{
4415    DeviceClass *dc = DEVICE_CLASS(oc);
4416    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4417
4418    dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
4419    pcc->init_proc = init_proc_MPC8xx;
4420    pcc->check_pow = check_pow_none;
4421    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING  |
4422                       PPC_MEM_EIEIO | PPC_MEM_SYNC |
4423                       PPC_CACHE_ICBI | PPC_MFTB;
4424    pcc->msr_mask = (1ull << MSR_ILE) |
4425                    (1ull << MSR_EE) |
4426                    (1ull << MSR_PR) |
4427                    (1ull << MSR_FP) |
4428                    (1ull << MSR_ME) |
4429                    (1ull << MSR_SE) |
4430                    (1ull << MSR_DE) |
4431                    (1ull << MSR_EP) |
4432                    (1ull << MSR_IR) |
4433                    (1ull << MSR_DR) |
4434                    (1ull << MSR_RI) |
4435                    (1ull << MSR_LE);
4436    pcc->mmu_model = POWERPC_MMU_MPC8xx;
4437    pcc->excp_model = POWERPC_EXCP_603;
4438    pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4439    pcc->bfd_mach = bfd_mach_ppc_860;
4440    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4441                 POWERPC_FLAG_BUS_CLK;
4442}
4443
4444/* Freescale 82xx cores (aka PowerQUICC-II)                                  */
4445
4446static void init_proc_G2(CPUPPCState *env)
4447{
4448    gen_spr_ne_601(env);
4449    gen_spr_sdr1(env);
4450    gen_spr_G2_755(env);
4451    gen_spr_G2(env);
4452    /* Time base */
4453    gen_tbl(env);
4454    /* External access control */
4455    /* XXX : not implemented */
4456    spr_register(env, SPR_EAR, "EAR",
4457                 SPR_NOACCESS, SPR_NOACCESS,
4458                 &spr_read_generic, &spr_write_generic,
4459                 0x00000000);
4460    /* Hardware implementation register */
4461    /* XXX : not implemented */
4462    spr_register(env, SPR_HID0, "HID0",
4463                 SPR_NOACCESS, SPR_NOACCESS,
4464                 &spr_read_generic, &spr_write_generic,
4465                 0x00000000);
4466    /* XXX : not implemented */
4467    spr_register(env, SPR_HID1, "HID1",
4468                 SPR_NOACCESS, SPR_NOACCESS,
4469                 &spr_read_generic, &spr_write_generic,
4470                 0x00000000);
4471    /* XXX : not implemented */
4472    spr_register(env, SPR_HID2, "HID2",
4473                 SPR_NOACCESS, SPR_NOACCESS,
4474                 &spr_read_generic, &spr_write_generic,
4475                 0x00000000);
4476    /* Memory management */
4477    gen_low_BATs(env);
4478    gen_high_BATs(env);
4479    gen_6xx_7xx_soft_tlb(env, 64, 2);
4480    init_excp_G2(env);
4481    env->dcache_line_size = 32;
4482    env->icache_line_size = 32;
4483    /* Allocate hardware IRQ controller */
4484    ppc6xx_irq_init(ppc_env_get_cpu(env));
4485}
4486
4487POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
4488{
4489    DeviceClass *dc = DEVICE_CLASS(oc);
4490    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4491
4492    dc->desc = "PowerPC G2";
4493    pcc->init_proc = init_proc_G2;
4494    pcc->check_pow = check_pow_hid0;
4495    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4496                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4497                       PPC_FLOAT_STFIWX |
4498                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4499                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
4500                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4501                       PPC_SEGMENT | PPC_EXTERN;
4502    pcc->msr_mask = (1ull << MSR_POW) |
4503                    (1ull << MSR_TGPR) |
4504                    (1ull << MSR_EE) |
4505                    (1ull << MSR_PR) |
4506                    (1ull << MSR_FP) |
4507                    (1ull << MSR_ME) |
4508                    (1ull << MSR_FE0) |
4509                    (1ull << MSR_SE) |
4510                    (1ull << MSR_DE) |
4511                    (1ull << MSR_FE1) |
4512                    (1ull << MSR_AL) |
4513                    (1ull << MSR_EP) |
4514                    (1ull << MSR_IR) |
4515                    (1ull << MSR_DR) |
4516                    (1ull << MSR_RI);
4517    pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4518    pcc->excp_model = POWERPC_EXCP_G2;
4519    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4520    pcc->bfd_mach = bfd_mach_ppc_ec603e;
4521    pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4522                 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4523}
4524
4525static void init_proc_G2LE(CPUPPCState *env)
4526{
4527    gen_spr_ne_601(env);
4528    gen_spr_sdr1(env);
4529    gen_spr_G2_755(env);
4530    gen_spr_G2(env);
4531    /* Time base */
4532    gen_tbl(env);
4533    /* External access control */
4534    /* XXX : not implemented */
4535    spr_register(env, SPR_EAR, "EAR",
4536                 SPR_NOACCESS, SPR_NOACCESS,
4537                 &spr_read_generic, &spr_write_generic,
4538                 0x00000000);
4539    /* Hardware implementation register */
4540    /* XXX : not implemented */
4541    spr_register(env, SPR_HID0, "HID0",
4542                 SPR_NOACCESS, SPR_NOACCESS,
4543                 &spr_read_generic, &spr_write_generic,
4544                 0x00000000);
4545    /* XXX : not implemented */
4546    spr_register(env, SPR_HID1, "HID1",
4547                 SPR_NOACCESS, SPR_NOACCESS,
4548                 &spr_read_generic, &spr_write_generic,
4549                 0x00000000);
4550    /* XXX : not implemented */
4551    spr_register(env, SPR_HID2, "HID2",
4552                 SPR_NOACCESS, SPR_NOACCESS,
4553                 &spr_read_generic, &spr_write_generic,
4554                 0x00000000);
4555
4556    /* Memory management */
4557    gen_low_BATs(env);
4558    gen_high_BATs(env);
4559    gen_6xx_7xx_soft_tlb(env, 64, 2);
4560    init_excp_G2(env);
4561    env->dcache_line_size = 32;
4562    env->icache_line_size = 32;
4563    /* Allocate hardware IRQ controller */
4564    ppc6xx_irq_init(ppc_env_get_cpu(env));
4565}
4566
4567POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
4568{
4569    DeviceClass *dc = DEVICE_CLASS(oc);
4570    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4571
4572    dc->desc = "PowerPC G2LE";
4573    pcc->init_proc = init_proc_G2LE;
4574    pcc->check_pow = check_pow_hid0;
4575    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4576                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4577                       PPC_FLOAT_STFIWX |
4578                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4579                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
4580                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4581                       PPC_SEGMENT | PPC_EXTERN;
4582    pcc->msr_mask = (1ull << MSR_POW) |
4583                    (1ull << MSR_TGPR) |
4584                    (1ull << MSR_ILE) |
4585                    (1ull << MSR_EE) |
4586                    (1ull << MSR_PR) |
4587                    (1ull << MSR_FP) |
4588                    (1ull << MSR_ME) |
4589                    (1ull << MSR_FE0) |
4590                    (1ull << MSR_SE) |
4591                    (1ull << MSR_DE) |
4592                    (1ull << MSR_FE1) |
4593                    (1ull << MSR_AL) |
4594                    (1ull << MSR_EP) |
4595                    (1ull << MSR_IR) |
4596                    (1ull << MSR_DR) |
4597                    (1ull << MSR_RI) |
4598                    (1ull << MSR_LE);
4599    pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4600    pcc->excp_model = POWERPC_EXCP_G2;
4601    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4602    pcc->bfd_mach = bfd_mach_ppc_ec603e;
4603    pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4604                 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4605}
4606
4607static void init_proc_e200(CPUPPCState *env)
4608{
4609    /* Time base */
4610    gen_tbl(env);
4611    gen_spr_BookE(env, 0x000000070000FFFFULL);
4612    /* XXX : not implemented */
4613    spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4614                 &spr_read_spefscr, &spr_write_spefscr,
4615                 &spr_read_spefscr, &spr_write_spefscr,
4616                 0x00000000);
4617    /* Memory management */
4618    gen_spr_BookE206(env, 0x0000005D, NULL);
4619    /* XXX : not implemented */
4620    spr_register(env, SPR_HID0, "HID0",
4621                 SPR_NOACCESS, SPR_NOACCESS,
4622                 &spr_read_generic, &spr_write_generic,
4623                 0x00000000);
4624    /* XXX : not implemented */
4625    spr_register(env, SPR_HID1, "HID1",
4626                 SPR_NOACCESS, SPR_NOACCESS,
4627                 &spr_read_generic, &spr_write_generic,
4628                 0x00000000);
4629    /* XXX : not implemented */
4630    spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4631                 SPR_NOACCESS, SPR_NOACCESS,
4632                 &spr_read_generic, &spr_write_generic,
4633                 0x00000000);
4634    /* XXX : not implemented */
4635    spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4636                 SPR_NOACCESS, SPR_NOACCESS,
4637                 &spr_read_generic, &spr_write_generic,
4638                 0x00000000);
4639    /* XXX : not implemented */
4640    spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4641                 SPR_NOACCESS, SPR_NOACCESS,
4642                 &spr_read_generic, &spr_write_generic,
4643                 0x00000000);
4644    /* XXX : not implemented */
4645    spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4646                 SPR_NOACCESS, SPR_NOACCESS,
4647                 &spr_read_generic, &spr_write_generic,
4648                 0x00000000);
4649    /* XXX : not implemented */
4650    spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4651                 SPR_NOACCESS, SPR_NOACCESS,
4652                 &spr_read_generic, &spr_write_generic,
4653                 0x00000000);
4654    /* XXX : not implemented */
4655    spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4656                 &spr_read_generic, SPR_NOACCESS,
4657                 &spr_read_generic, SPR_NOACCESS,
4658                 0x00000000);
4659    /* XXX : not implemented */
4660    spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4661                 SPR_NOACCESS, SPR_NOACCESS,
4662                 &spr_read_generic, &spr_write_generic,
4663                 0x00000000);
4664    /* XXX : not implemented */
4665    spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4666                 SPR_NOACCESS, SPR_NOACCESS,
4667                 &spr_read_generic, &spr_write_generic,
4668                 0x00000000);
4669    /* XXX : not implemented */
4670    spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4671                 SPR_NOACCESS, SPR_NOACCESS,
4672                 &spr_read_generic, &spr_write_generic,
4673                 0x00000000);
4674    /* XXX : not implemented */
4675    spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4676                 SPR_NOACCESS, SPR_NOACCESS,
4677                 &spr_read_generic, &spr_write_generic,
4678                 0x00000000);
4679    /* XXX : not implemented */
4680    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4681                 SPR_NOACCESS, SPR_NOACCESS,
4682                 &spr_read_generic, &spr_write_generic,
4683                 0x00000000);
4684    /* XXX : not implemented */
4685    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4686                 SPR_NOACCESS, SPR_NOACCESS,
4687                 &spr_read_generic, &spr_write_generic,
4688                 0x00000000);
4689    /* XXX : not implemented */
4690    spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4691                 SPR_NOACCESS, SPR_NOACCESS,
4692                 &spr_read_generic, &spr_write_generic,
4693                 0x00000000); /* TOFIX */
4694    spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4695                 SPR_NOACCESS, SPR_NOACCESS,
4696                 &spr_read_generic, &spr_write_generic,
4697                 0x00000000);
4698    spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4699                 SPR_NOACCESS, SPR_NOACCESS,
4700                 &spr_read_generic, &spr_write_generic,
4701                 0x00000000);
4702#if !defined(CONFIG_USER_ONLY)
4703    env->nb_tlb = 64;
4704    env->nb_ways = 1;
4705    env->id_tlbs = 0;
4706    env->tlb_type = TLB_EMB;
4707#endif
4708    init_excp_e200(env, 0xFFFF0000UL);
4709    env->dcache_line_size = 32;
4710    env->icache_line_size = 32;
4711    /* XXX: TODO: allocate internal IRQ controller */
4712}
4713
4714POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
4715{
4716    DeviceClass *dc = DEVICE_CLASS(oc);
4717    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4718
4719    dc->desc = "e200 core";
4720    pcc->init_proc = init_proc_e200;
4721    pcc->check_pow = check_pow_hid0;
4722    /* XXX: unimplemented instructions:
4723     * dcblc
4724     * dcbtlst
4725     * dcbtstls
4726     * icblc
4727     * icbtls
4728     * tlbivax
4729     * all SPE multiply-accumulate instructions
4730     */
4731    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4732                       PPC_SPE | PPC_SPE_SINGLE |
4733                       PPC_WRTEE | PPC_RFDI |
4734                       PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4735                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4736                       PPC_MEM_TLBSYNC | PPC_TLBIVAX |
4737                       PPC_BOOKE;
4738    pcc->msr_mask = (1ull << MSR_UCLE) |
4739                    (1ull << MSR_SPE) |
4740                    (1ull << MSR_POW) |
4741                    (1ull << MSR_CE) |
4742                    (1ull << MSR_EE) |
4743                    (1ull << MSR_PR) |
4744                    (1ull << MSR_FP) |
4745                    (1ull << MSR_ME) |
4746                    (1ull << MSR_FE0) |
4747                    (1ull << MSR_DWE) |
4748                    (1ull << MSR_DE) |
4749                    (1ull << MSR_FE1) |
4750                    (1ull << MSR_IR) |
4751                    (1ull << MSR_DR);
4752    pcc->mmu_model = POWERPC_MMU_BOOKE206;
4753    pcc->excp_model = POWERPC_EXCP_BOOKE;
4754    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4755    pcc->bfd_mach = bfd_mach_ppc_860;
4756    pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4757                 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4758                 POWERPC_FLAG_BUS_CLK;
4759}
4760
4761static void init_proc_e300(CPUPPCState *env)
4762{
4763    gen_spr_ne_601(env);
4764    gen_spr_sdr1(env);
4765    gen_spr_603(env);
4766    /* Time base */
4767    gen_tbl(env);
4768    /* hardware implementation registers */
4769    /* XXX : not implemented */
4770    spr_register(env, SPR_HID0, "HID0",
4771                 SPR_NOACCESS, SPR_NOACCESS,
4772                 &spr_read_generic, &spr_write_generic,
4773                 0x00000000);
4774    /* XXX : not implemented */
4775    spr_register(env, SPR_HID1, "HID1",
4776                 SPR_NOACCESS, SPR_NOACCESS,
4777                 &spr_read_generic, &spr_write_generic,
4778                 0x00000000);
4779    /* XXX : not implemented */
4780    spr_register(env, SPR_HID2, "HID2",
4781                 SPR_NOACCESS, SPR_NOACCESS,
4782                 &spr_read_generic, &spr_write_generic,
4783                 0x00000000);
4784    /* Breakpoints */
4785    /* XXX : not implemented */
4786    spr_register(env, SPR_DABR, "DABR",
4787                 SPR_NOACCESS, SPR_NOACCESS,
4788                 &spr_read_generic, &spr_write_generic,
4789                 0x00000000);
4790    /* XXX : not implemented */
4791    spr_register(env, SPR_DABR2, "DABR2",
4792                 SPR_NOACCESS, SPR_NOACCESS,
4793                 &spr_read_generic, &spr_write_generic,
4794                 0x00000000);
4795    /* XXX : not implemented */
4796    spr_register(env, SPR_IABR2, "IABR2",
4797                 SPR_NOACCESS, SPR_NOACCESS,
4798                 &spr_read_generic, &spr_write_generic,
4799                 0x00000000);
4800    /* XXX : not implemented */
4801    spr_register(env, SPR_IBCR, "IBCR",
4802                 SPR_NOACCESS, SPR_NOACCESS,
4803                 &spr_read_generic, &spr_write_generic,
4804                 0x00000000);
4805    /* XXX : not implemented */
4806    spr_register(env, SPR_DBCR, "DBCR",
4807                 SPR_NOACCESS, SPR_NOACCESS,
4808                 &spr_read_generic, &spr_write_generic,
4809                 0x00000000);
4810    /* Memory management */
4811    gen_low_BATs(env);
4812    gen_high_BATs(env);
4813    gen_6xx_7xx_soft_tlb(env, 64, 2);
4814    init_excp_603(env);
4815    env->dcache_line_size = 32;
4816    env->icache_line_size = 32;
4817    /* Allocate hardware IRQ controller */
4818    ppc6xx_irq_init(ppc_env_get_cpu(env));
4819}
4820
4821POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
4822{
4823    DeviceClass *dc = DEVICE_CLASS(oc);
4824    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4825
4826    dc->desc = "e300 core";
4827    pcc->init_proc = init_proc_e300;
4828    pcc->check_pow = check_pow_hid0;
4829    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4830                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4831                       PPC_FLOAT_STFIWX |
4832                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4833                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
4834                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4835                       PPC_SEGMENT | PPC_EXTERN;
4836    pcc->msr_mask = (1ull << MSR_POW) |
4837                    (1ull << MSR_TGPR) |
4838                    (1ull << MSR_ILE) |
4839                    (1ull << MSR_EE) |
4840                    (1ull << MSR_PR) |
4841                    (1ull << MSR_FP) |
4842                    (1ull << MSR_ME) |
4843                    (1ull << MSR_FE0) |
4844                    (1ull << MSR_SE) |
4845                    (1ull << MSR_DE) |
4846                    (1ull << MSR_FE1) |
4847                    (1ull << MSR_AL) |
4848                    (1ull << MSR_EP) |
4849                    (1ull << MSR_IR) |
4850                    (1ull << MSR_DR) |
4851                    (1ull << MSR_RI) |
4852                    (1ull << MSR_LE);
4853    pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4854    pcc->excp_model = POWERPC_EXCP_603;
4855    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4856    pcc->bfd_mach = bfd_mach_ppc_603;
4857    pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4858                 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4859}
4860
4861#if !defined(CONFIG_USER_ONLY)
4862static void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
4863{
4864    TCGv val = tcg_temp_new();
4865    tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
4866    gen_store_spr(SPR_BOOKE_MAS3, val);
4867    tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
4868    gen_store_spr(SPR_BOOKE_MAS7, val);
4869    tcg_temp_free(val);
4870}
4871
4872static void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
4873{
4874    TCGv mas7 = tcg_temp_new();
4875    TCGv mas3 = tcg_temp_new();
4876    gen_load_spr(mas7, SPR_BOOKE_MAS7);
4877    tcg_gen_shli_tl(mas7, mas7, 32);
4878    gen_load_spr(mas3, SPR_BOOKE_MAS3);
4879    tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
4880    tcg_temp_free(mas3);
4881    tcg_temp_free(mas7);
4882}
4883
4884#endif
4885
4886enum fsl_e500_version {
4887    fsl_e500v1,
4888    fsl_e500v2,
4889    fsl_e500mc,
4890    fsl_e5500,
4891};
4892
4893static void init_proc_e500(CPUPPCState *env, int version)
4894{
4895    PowerPCCPU *cpu = ppc_env_get_cpu(env);
4896    uint32_t tlbncfg[2];
4897    uint64_t ivor_mask;
4898    uint64_t ivpr_mask = 0xFFFF0000ULL;
4899    uint32_t l1cfg0 = 0x3800  /* 8 ways */
4900                    | 0x0020; /* 32 kb */
4901    uint32_t l1cfg1 = 0x3800  /* 8 ways */
4902                    | 0x0020; /* 32 kb */
4903#if !defined(CONFIG_USER_ONLY)
4904    int i;
4905#endif
4906
4907    /* Time base */
4908    gen_tbl(env);
4909    /*
4910     * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4911     *     complain when accessing them.
4912     * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4913     */
4914    switch (version) {
4915        case fsl_e500v1:
4916        case fsl_e500v2:
4917        default:
4918            ivor_mask = 0x0000000F0000FFFFULL;
4919            break;
4920        case fsl_e500mc:
4921        case fsl_e5500:
4922            ivor_mask = 0x000003FE0000FFFFULL;
4923            break;
4924    }
4925    gen_spr_BookE(env, ivor_mask);
4926    gen_spr_usprg3(env);
4927    /* Processor identification */
4928    spr_register(env, SPR_BOOKE_PIR, "PIR",
4929                 SPR_NOACCESS, SPR_NOACCESS,
4930                 &spr_read_generic, &spr_write_pir,
4931                 0x00000000);
4932    /* XXX : not implemented */
4933    spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4934                 &spr_read_spefscr, &spr_write_spefscr,
4935                 &spr_read_spefscr, &spr_write_spefscr,
4936                 0x00000000);
4937#if !defined(CONFIG_USER_ONLY)
4938    /* Memory management */
4939    env->nb_pids = 3;
4940    env->nb_ways = 2;
4941    env->id_tlbs = 0;
4942    switch (version) {
4943    case fsl_e500v1:
4944        tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4945        tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4946        break;
4947    case fsl_e500v2:
4948        tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4949        tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4950        break;
4951    case fsl_e500mc:
4952    case fsl_e5500:
4953        tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4954        tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4955        break;
4956    default:
4957        cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4958    }
4959#endif
4960    /* Cache sizes */
4961    switch (version) {
4962    case fsl_e500v1:
4963    case fsl_e500v2:
4964        env->dcache_line_size = 32;
4965        env->icache_line_size = 32;
4966        break;
4967    case fsl_e500mc:
4968    case fsl_e5500:
4969        env->dcache_line_size = 64;
4970        env->icache_line_size = 64;
4971        l1cfg0 |= 0x1000000; /* 64 byte cache block size */
4972        l1cfg1 |= 0x1000000; /* 64 byte cache block size */
4973        break;
4974    default:
4975        cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4976    }
4977    gen_spr_BookE206(env, 0x000000DF, tlbncfg);
4978    /* XXX : not implemented */
4979    spr_register(env, SPR_HID0, "HID0",
4980                 SPR_NOACCESS, SPR_NOACCESS,
4981                 &spr_read_generic, &spr_write_generic,
4982                 0x00000000);
4983    /* XXX : not implemented */
4984    spr_register(env, SPR_HID1, "HID1",
4985                 SPR_NOACCESS, SPR_NOACCESS,
4986                 &spr_read_generic, &spr_write_generic,
4987                 0x00000000);
4988    /* XXX : not implemented */
4989    spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4990                 SPR_NOACCESS, SPR_NOACCESS,
4991                 &spr_read_generic, &spr_write_generic,
4992                 0x00000000);
4993    /* XXX : not implemented */
4994    spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4995                 SPR_NOACCESS, SPR_NOACCESS,
4996                 &spr_read_generic, &spr_write_generic,
4997                 0x00000000);
4998    /* XXX : not implemented */
4999    spr_register(env, SPR_Exxx_MCAR, "MCAR",
5000                 SPR_NOACCESS, SPR_NOACCESS,

5001                 &spr_read_generic, &spr_write_generic,
5002                 0x00000000);
5003    /* XXX : not implemented */
5004    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
5005                 SPR_NOACCESS, SPR_NOACCESS,
5006                 &spr_read_generic, &spr_write_generic,
5007                 0x00000000);
5008    /* XXX : not implemented */
5009    spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
5010                 SPR_NOACCESS, SPR_NOACCESS,
5011                 &spr_read_generic, &spr_write_generic,
5012                 0x00000000);
5013    /* XXX : not implemented */
5014    spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
5015                 SPR_NOACCESS, SPR_NOACCESS,
5016                 &spr_read_generic, &spr_write_generic,
5017                 0x00000000);
5018    /* XXX : not implemented */
5019    spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
5020                 &spr_read_generic, SPR_NOACCESS,
5021                 &spr_read_generic, SPR_NOACCESS,
5022                 l1cfg0);
5023    spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
5024                 &spr_read_generic, SPR_NOACCESS,
5025                 &spr_read_generic, SPR_NOACCESS,
5026                 l1cfg1);
5027    spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
5028                 SPR_NOACCESS, SPR_NOACCESS,
5029                 &spr_read_generic, &spr_write_e500_l1csr0,
5030                 0x00000000);
5031    spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
5032                 SPR_NOACCESS, SPR_NOACCESS,
5033                 &spr_read_generic, &spr_write_e500_l1csr1,
5034                 0x00000000);
5035    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
5036                 SPR_NOACCESS, SPR_NOACCESS,
5037                 &spr_read_generic, &spr_write_generic,
5038                 0x00000000);
5039    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
5040                 SPR_NOACCESS, SPR_NOACCESS,
5041                 &spr_read_generic, &spr_write_generic,
5042                 0x00000000);
5043    spr_register(env, SPR_MMUCSR0, "MMUCSR0",
5044                 SPR_NOACCESS, SPR_NOACCESS,
5045                 &spr_read_generic, &spr_write_booke206_mmucsr0,
5046                 0x00000000);
5047    spr_register(env, SPR_BOOKE_EPR, "EPR",
5048                 SPR_NOACCESS, SPR_NOACCESS,
5049                 &spr_read_generic, SPR_NOACCESS,
5050                 0x00000000);
5051    /* XXX better abstract into Emb.xxx features */
5052    if (version == fsl_e5500) {
5053        spr_register(env, SPR_BOOKE_EPCR, "EPCR",
5054                     SPR_NOACCESS, SPR_NOACCESS,
5055                     &spr_read_generic, &spr_write_generic,
5056                     0x00000000);
5057        spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
5058                     SPR_NOACCESS, SPR_NOACCESS,
5059                     &spr_read_mas73, &spr_write_mas73,
5060                     0x00000000);
5061        ivpr_mask = (target_ulong)~0xFFFFULL;
5062    }
5063
5064#if !defined(CONFIG_USER_ONLY)
5065    env->nb_tlb = 0;
5066    env->tlb_type = TLB_MAS;
5067    for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
5068        env->nb_tlb += booke206_tlb_size(env, i);
5069    }
5070#endif
5071
5072    init_excp_e200(env, ivpr_mask);
5073    /* Allocate hardware IRQ controller */
5074    ppce500_irq_init(ppc_env_get_cpu(env));
5075}
5076
5077static void init_proc_e500v1(CPUPPCState *env)
5078{
5079    init_proc_e500(env, fsl_e500v1);
5080}
5081
5082POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
5083{
5084    DeviceClass *dc = DEVICE_CLASS(oc);
5085    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5086
5087    dc->desc = "e500v1 core";
5088    pcc->init_proc = init_proc_e500v1;
5089    pcc->check_pow = check_pow_hid0;
5090    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
5091                       PPC_SPE | PPC_SPE_SINGLE |
5092                       PPC_WRTEE | PPC_RFDI |
5093                       PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5094                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5095                       PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
5096    pcc->insns_flags2 = PPC2_BOOKE206;
5097    pcc->msr_mask = (1ull << MSR_UCLE) |
5098                    (1ull << MSR_SPE) |
5099                    (1ull << MSR_POW) |
5100                    (1ull << MSR_CE) |
5101                    (1ull << MSR_EE) |
5102                    (1ull << MSR_PR) |
5103                    (1ull << MSR_FP) |
5104                    (1ull << MSR_ME) |
5105                    (1ull << MSR_FE0) |
5106                    (1ull << MSR_DWE) |
5107                    (1ull << MSR_DE) |
5108                    (1ull << MSR_FE1) |
5109                    (1ull << MSR_IR) |
5110                    (1ull << MSR_DR);
5111    pcc->mmu_model = POWERPC_MMU_BOOKE206;
5112    pcc->excp_model = POWERPC_EXCP_BOOKE;
5113    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5114    pcc->bfd_mach = bfd_mach_ppc_860;
5115    pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
5116                 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
5117                 POWERPC_FLAG_BUS_CLK;
5118}
5119
5120static void init_proc_e500v2(CPUPPCState *env)
5121{
5122    init_proc_e500(env, fsl_e500v2);
5123}
5124
5125POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
5126{
5127    DeviceClass *dc = DEVICE_CLASS(oc);
5128    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5129
5130    dc->desc = "e500v2 core";
5131    pcc->init_proc = init_proc_e500v2;
5132    pcc->check_pow = check_pow_hid0;
5133    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
5134                       PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
5135                       PPC_WRTEE | PPC_RFDI |
5136                       PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5137                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5138                       PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
5139    pcc->insns_flags2 = PPC2_BOOKE206;
5140    pcc->msr_mask = (1ull << MSR_UCLE) |
5141                    (1ull << MSR_SPE) |
5142                    (1ull << MSR_POW) |
5143                    (1ull << MSR_CE) |
5144                    (1ull << MSR_EE) |
5145                    (1ull << MSR_PR) |
5146                    (1ull << MSR_FP) |
5147                    (1ull << MSR_ME) |
5148                    (1ull << MSR_FE0) |
5149                    (1ull << MSR_DWE) |
5150                    (1ull << MSR_DE) |
5151                    (1ull << MSR_FE1) |
5152                    (1ull << MSR_IR) |
5153                    (1ull << MSR_DR);
5154    pcc->mmu_model = POWERPC_MMU_BOOKE206;
5155    pcc->excp_model = POWERPC_EXCP_BOOKE;
5156    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5157    pcc->bfd_mach = bfd_mach_ppc_860;
5158    pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
5159                 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
5160                 POWERPC_FLAG_BUS_CLK;
5161}
5162
5163static void init_proc_e500mc(CPUPPCState *env)
5164{
5165    init_proc_e500(env, fsl_e500mc);
5166}
5167
5168POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
5169{
5170    DeviceClass *dc = DEVICE_CLASS(oc);
5171    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5172
5173    dc->desc = "e500mc core";
5174    pcc->init_proc = init_proc_e500mc;
5175    pcc->check_pow = check_pow_none;
5176    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
5177                       PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
5178                       PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5179                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5180                       PPC_FLOAT | PPC_FLOAT_FRES |
5181                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
5182                       PPC_FLOAT_STFIWX | PPC_WAIT |
5183                       PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
5184    pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
5185    pcc->msr_mask = (1ull << MSR_GS) |
5186                    (1ull << MSR_UCLE) |
5187                    (1ull << MSR_CE) |
5188                    (1ull << MSR_EE) |
5189                    (1ull << MSR_PR) |
5190                    (1ull << MSR_FP) |
5191                    (1ull << MSR_ME) |
5192                    (1ull << MSR_FE0) |
5193                    (1ull << MSR_DE) |
5194                    (1ull << MSR_FE1) |
5195                    (1ull << MSR_IR) |
5196                    (1ull << MSR_DR) |
5197                    (1ull << MSR_PX) |
5198                    (1ull << MSR_RI);
5199    pcc->mmu_model = POWERPC_MMU_BOOKE206;
5200    pcc->excp_model = POWERPC_EXCP_BOOKE;
5201    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5202    /* FIXME: figure out the correct flag for e500mc */
5203    pcc->bfd_mach = bfd_mach_ppc_e500;
5204    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
5205                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5206}
5207
5208#ifdef TARGET_PPC64
5209static void init_proc_e5500(CPUPPCState *env)
5210{
5211    init_proc_e500(env, fsl_e5500);
5212}
5213
5214POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
5215{
5216    DeviceClass *dc = DEVICE_CLASS(oc);
5217    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5218
5219    dc->desc = "e5500 core";
5220    pcc->init_proc = init_proc_e5500;
5221    pcc->check_pow = check_pow_none;
5222    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
5223                       PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
5224                       PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5225                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5226                       PPC_FLOAT | PPC_FLOAT_FRES |
5227                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
5228                       PPC_FLOAT_STFIWX | PPC_WAIT |
5229                       PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
5230                       PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
5231    pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | \
5232                        PPC2_FP_CVT_S64;
5233    pcc->msr_mask = (1ull << MSR_CM) |
5234                    (1ull << MSR_GS) |
5235                    (1ull << MSR_UCLE) |
5236                    (1ull << MSR_CE) |
5237                    (1ull << MSR_EE) |
5238                    (1ull << MSR_PR) |
5239                    (1ull << MSR_FP) |
5240                    (1ull << MSR_ME) |
5241                    (1ull << MSR_FE0) |
5242                    (1ull << MSR_DE) |
5243                    (1ull << MSR_FE1) |
5244                    (1ull << MSR_IR) |
5245                    (1ull << MSR_DR) |
5246                    (1ull << MSR_PX) |
5247                    (1ull << MSR_RI);
5248    pcc->mmu_model = POWERPC_MMU_BOOKE206;
5249    pcc->excp_model = POWERPC_EXCP_BOOKE;
5250    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5251    /* FIXME: figure out the correct flag for e5500 */
5252    pcc->bfd_mach = bfd_mach_ppc_e500;
5253    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
5254                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5255}
5256#endif
5257
5258/* Non-embedded PowerPC                                                      */
5259
5260#define POWERPC_MSRR_601     (0x0000000000001040ULL)
5261
5262static void init_proc_601(CPUPPCState *env)
5263{
5264    gen_spr_ne_601(env);
5265    gen_spr_sdr1(env);
5266    gen_spr_601(env);
5267    /* Hardware implementation registers */
5268    /* XXX : not implemented */
5269    spr_register(env, SPR_HID0, "HID0",
5270                 SPR_NOACCESS, SPR_NOACCESS,
5271                 &spr_read_generic, &spr_write_hid0_601,
5272                 0x80010080);
5273    /* XXX : not implemented */
5274    spr_register(env, SPR_HID1, "HID1",
5275                 SPR_NOACCESS, SPR_NOACCESS,
5276                 &spr_read_generic, &spr_write_generic,
5277                 0x00000000);
5278    /* XXX : not implemented */
5279    spr_register(env, SPR_601_HID2, "HID2",
5280                 SPR_NOACCESS, SPR_NOACCESS,
5281                 &spr_read_generic, &spr_write_generic,
5282                 0x00000000);
5283    /* XXX : not implemented */
5284    spr_register(env, SPR_601_HID5, "HID5",
5285                 SPR_NOACCESS, SPR_NOACCESS,
5286                 &spr_read_generic, &spr_write_generic,
5287                 0x00000000);
5288    /* Memory management */
5289    init_excp_601(env);
5290    /* XXX: beware that dcache line size is 64 
5291     *      but dcbz uses 32 bytes "sectors"
5292     * XXX: this breaks clcs instruction !
5293     */
5294    env->dcache_line_size = 32;
5295    env->icache_line_size = 64;
5296    /* Allocate hardware IRQ controller */
5297    ppc6xx_irq_init(ppc_env_get_cpu(env));
5298}
5299
5300POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
5301{
5302    DeviceClass *dc = DEVICE_CLASS(oc);
5303    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5304
5305    dc->desc = "PowerPC 601";
5306    pcc->init_proc = init_proc_601;
5307    pcc->check_pow = check_pow_none;
5308    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
5309                       PPC_FLOAT |
5310                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5311                       PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
5312                       PPC_SEGMENT | PPC_EXTERN;
5313    pcc->msr_mask = (1ull << MSR_EE) |
5314                    (1ull << MSR_PR) |
5315                    (1ull << MSR_FP) |
5316                    (1ull << MSR_ME) |
5317                    (1ull << MSR_FE0) |
5318                    (1ull << MSR_SE) |
5319                    (1ull << MSR_FE1) |
5320                    (1ull << MSR_EP) |
5321                    (1ull << MSR_IR) |
5322                    (1ull << MSR_DR);
5323    pcc->mmu_model = POWERPC_MMU_601;
5324#if defined(CONFIG_SOFTMMU)
5325    pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5326#endif
5327    pcc->excp_model = POWERPC_EXCP_601;
5328    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5329    pcc->bfd_mach = bfd_mach_ppc_601;
5330    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
5331}
5332
5333#define POWERPC_MSRR_601v    (0x0000000000001040ULL)
5334
5335static void init_proc_601v(CPUPPCState *env)
5336{
5337    init_proc_601(env);
5338    /* XXX : not implemented */
5339    spr_register(env, SPR_601_HID15, "HID15",
5340                 SPR_NOACCESS, SPR_NOACCESS,
5341                 &spr_read_generic, &spr_write_generic,
5342                 0x00000000);
5343}
5344
5345POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
5346{
5347    DeviceClass *dc = DEVICE_CLASS(oc);
5348    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5349
5350    dc->desc = "PowerPC 601v";
5351    pcc->init_proc = init_proc_601v;
5352    pcc->check_pow = check_pow_none;
5353    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
5354                       PPC_FLOAT |
5355                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5356                       PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
5357                       PPC_SEGMENT | PPC_EXTERN;
5358    pcc->msr_mask = (1ull << MSR_EE) |
5359                    (1ull << MSR_PR) |
5360                    (1ull << MSR_FP) |
5361                    (1ull << MSR_ME) |
5362                    (1ull << MSR_FE0) |
5363                    (1ull << MSR_SE) |
5364                    (1ull << MSR_FE1) |
5365                    (1ull << MSR_EP) |
5366                    (1ull << MSR_IR) |
5367                    (1ull << MSR_DR);
5368    pcc->mmu_model = POWERPC_MMU_601;
5369#if defined(CONFIG_SOFTMMU)
5370    pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5371#endif
5372    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5373    pcc->bfd_mach = bfd_mach_ppc_601;
5374    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
5375}
5376
5377static void init_proc_602(CPUPPCState *env)
5378{
5379    gen_spr_ne_601(env);
5380    gen_spr_sdr1(env);
5381    gen_spr_602(env);
5382    /* Time base */
5383    gen_tbl(env);
5384    /* hardware implementation registers */
5385    /* XXX : not implemented */
5386    spr_register(env, SPR_HID0, "HID0",
5387                 SPR_NOACCESS, SPR_NOACCESS,
5388                 &spr_read_generic, &spr_write_generic,
5389                 0x00000000);
5390    /* XXX : not implemented */
5391    spr_register(env, SPR_HID1, "HID1",
5392                 SPR_NOACCESS, SPR_NOACCESS,
5393                 &spr_read_generic, &spr_write_generic,
5394                 0x00000000);
5395    /* Memory management */
5396    gen_low_BATs(env);
5397    gen_6xx_7xx_soft_tlb(env, 64, 2);
5398    init_excp_602(env);
5399    env->dcache_line_size = 32;
5400    env->icache_line_size = 32;
5401    /* Allocate hardware IRQ controller */
5402    ppc6xx_irq_init(ppc_env_get_cpu(env));
5403}
5404
5405POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
5406{
5407    DeviceClass *dc = DEVICE_CLASS(oc);
5408    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5409
5410    dc->desc = "PowerPC 602";
5411    pcc->init_proc = init_proc_602;
5412    pcc->check_pow = check_pow_hid0;
5413    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5414                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5415                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5416                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5417                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
5418                       PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC |
5419                       PPC_SEGMENT | PPC_602_SPEC;
5420    pcc->msr_mask = (1ull << MSR_VSX) |
5421                    (1ull << MSR_SA) |
5422                    (1ull << MSR_POW) |
5423                    (1ull << MSR_TGPR) |
5424                    (1ull << MSR_ILE) |
5425                    (1ull << MSR_EE) |
5426                    (1ull << MSR_PR) |
5427                    (1ull << MSR_FP) |
5428                    (1ull << MSR_ME) |
5429                    (1ull << MSR_FE0) |
5430                    (1ull << MSR_SE) |
5431                    (1ull << MSR_DE) |
5432                    (1ull << MSR_FE1) |
5433                    (1ull << MSR_EP) |
5434                    (1ull << MSR_IR) |
5435                    (1ull << MSR_DR) |
5436                    (1ull << MSR_RI) |
5437                    (1ull << MSR_LE);
5438    /* XXX: 602 MMU is quite specific. Should add a special case */
5439    pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5440    pcc->excp_model = POWERPC_EXCP_602;
5441    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5442    pcc->bfd_mach = bfd_mach_ppc_602;
5443    pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5444                 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5445}
5446
5447static void init_proc_603(CPUPPCState *env)
5448{
5449    gen_spr_ne_601(env);
5450    gen_spr_sdr1(env);
5451    gen_spr_603(env);
5452    /* Time base */
5453    gen_tbl(env);
5454    /* hardware implementation registers */
5455    /* XXX : not implemented */
5456    spr_register(env, SPR_HID0, "HID0",
5457                 SPR_NOACCESS, SPR_NOACCESS,
5458                 &spr_read_generic, &spr_write_generic,
5459                 0x00000000);
5460    /* XXX : not implemented */
5461    spr_register(env, SPR_HID1, "HID1",
5462                 SPR_NOACCESS, SPR_NOACCESS,
5463                 &spr_read_generic, &spr_write_generic,
5464                 0x00000000);
5465    /* Memory management */
5466    gen_low_BATs(env);
5467    gen_6xx_7xx_soft_tlb(env, 64, 2);
5468    init_excp_603(env);
5469    env->dcache_line_size = 32;
5470    env->icache_line_size = 32;
5471    /* Allocate hardware IRQ controller */
5472    ppc6xx_irq_init(ppc_env_get_cpu(env));
5473}
5474
5475POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
5476{
5477    DeviceClass *dc = DEVICE_CLASS(oc);
5478    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5479
5480    dc->desc = "PowerPC 603";
5481    pcc->init_proc = init_proc_603;
5482    pcc->check_pow = check_pow_hid0;
5483    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5484                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5485                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5486                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5487                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
5488                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5489                       PPC_SEGMENT | PPC_EXTERN;
5490    pcc->msr_mask = (1ull << MSR_POW) |
5491                    (1ull << MSR_TGPR) |
5492                    (1ull << MSR_ILE) |
5493                    (1ull << MSR_EE) |
5494                    (1ull << MSR_PR) |
5495                    (1ull << MSR_FP) |
5496                    (1ull << MSR_ME) |
5497                    (1ull << MSR_FE0) |
5498                    (1ull << MSR_SE) |
5499                    (1ull << MSR_DE) |
5500                    (1ull << MSR_FE1) |
5501                    (1ull << MSR_EP) |
5502                    (1ull << MSR_IR) |
5503                    (1ull << MSR_DR) |
5504                    (1ull << MSR_RI) |
5505                    (1ull << MSR_LE);
5506    pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5507    pcc->excp_model = POWERPC_EXCP_603;
5508    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5509    pcc->bfd_mach = bfd_mach_ppc_603;
5510    pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5511                 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5512}
5513
5514static void init_proc_603E(CPUPPCState *env)
5515{
5516    gen_spr_ne_601(env);
5517    gen_spr_sdr1(env);
5518    gen_spr_603(env);
5519    /* Time base */
5520    gen_tbl(env);
5521    /* hardware implementation registers */
5522    /* XXX : not implemented */
5523    spr_register(env, SPR_HID0, "HID0",
5524                 SPR_NOACCESS, SPR_NOACCESS,
5525                 &spr_read_generic, &spr_write_generic,
5526                 0x00000000);
5527    /* XXX : not implemented */
5528    spr_register(env, SPR_HID1, "HID1",
5529                 SPR_NOACCESS, SPR_NOACCESS,
5530                 &spr_read_generic, &spr_write_generic,
5531                 0x00000000);
5532    /* Memory management */
5533    gen_low_BATs(env);
5534    gen_6xx_7xx_soft_tlb(env, 64, 2);
5535    init_excp_603(env);
5536    env->dcache_line_size = 32;
5537    env->icache_line_size = 32;
5538    /* Allocate hardware IRQ controller */
5539    ppc6xx_irq_init(ppc_env_get_cpu(env));
5540}
5541
5542POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
5543{
5544    DeviceClass *dc = DEVICE_CLASS(oc);
5545    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5546
5547    dc->desc = "PowerPC 603e";
5548    pcc->init_proc = init_proc_603E;
5549    pcc->check_pow = check_pow_hid0;
5550    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5551                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5552                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5553                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5554                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
5555                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5556                       PPC_SEGMENT | PPC_EXTERN;
5557    pcc->msr_mask = (1ull << MSR_POW) |
5558                    (1ull << MSR_TGPR) |
5559                    (1ull << MSR_ILE) |
5560                    (1ull << MSR_EE) |
5561                    (1ull << MSR_PR) |
5562                    (1ull << MSR_FP) |
5563                    (1ull << MSR_ME) |
5564                    (1ull << MSR_FE0) |
5565                    (1ull << MSR_SE) |
5566                    (1ull << MSR_DE) |
5567                    (1ull << MSR_FE1) |
5568                    (1ull << MSR_EP) |
5569                    (1ull << MSR_IR) |
5570                    (1ull << MSR_DR) |
5571                    (1ull << MSR_RI) |
5572                    (1ull << MSR_LE);
5573    pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5574    pcc->excp_model = POWERPC_EXCP_603E;
5575    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5576    pcc->bfd_mach = bfd_mach_ppc_ec603e;
5577    pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5578                 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5579}
5580
5581static void init_proc_604(CPUPPCState *env)
5582{
5583    gen_spr_ne_601(env);
5584    gen_spr_sdr1(env);
5585    gen_spr_604(env);
5586    /* Time base */
5587    gen_tbl(env);
5588    /* Hardware implementation registers */
5589    /* XXX : not implemented */
5590    spr_register(env, SPR_HID0, "HID0",
5591                 SPR_NOACCESS, SPR_NOACCESS,
5592                 &spr_read_generic, &spr_write_generic,
5593                 0x00000000);
5594    /* Memory management */
5595    gen_low_BATs(env);
5596    init_excp_604(env);
5597    env->dcache_line_size = 32;
5598    env->icache_line_size = 32;
5599    /* Allocate hardware IRQ controller */
5600    ppc6xx_irq_init(ppc_env_get_cpu(env));
5601}
5602
5603POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
5604{
5605    DeviceClass *dc = DEVICE_CLASS(oc);
5606    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5607
5608    dc->desc = "PowerPC 604";
5609    pcc->init_proc = init_proc_604;
5610    pcc->check_pow = check_pow_nocheck;
5611    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5612                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5613                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5614                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5615                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
5616                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5617                       PPC_SEGMENT | PPC_EXTERN;
5618    pcc->msr_mask = (1ull << MSR_POW) |
5619                    (1ull << MSR_ILE) |
5620                    (1ull << MSR_EE) |
5621                    (1ull << MSR_PR) |
5622                    (1ull << MSR_FP) |
5623                    (1ull << MSR_ME) |
5624                    (1ull << MSR_FE0) |
5625                    (1ull << MSR_SE) |
5626                    (1ull << MSR_DE) |
5627                    (1ull << MSR_FE1) |
5628                    (1ull << MSR_EP) |
5629                    (1ull << MSR_IR) |
5630                    (1ull << MSR_DR) |
5631                    (1ull << MSR_PMM) |
5632                    (1ull << MSR_RI) |
5633                    (1ull << MSR_LE);
5634    pcc->mmu_model = POWERPC_MMU_32B;
5635#if defined(CONFIG_SOFTMMU)
5636    pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5637#endif
5638    pcc->excp_model = POWERPC_EXCP_604;
5639    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5640    pcc->bfd_mach = bfd_mach_ppc_604;
5641    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5642                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5643}
5644
5645static void init_proc_604E(CPUPPCState *env)
5646{
5647    gen_spr_ne_601(env);
5648    gen_spr_sdr1(env);
5649    gen_spr_604(env);
5650    /* XXX : not implemented */
5651    spr_register(env, SPR_7XX_MMCR1, "MMCR1",
5652                 SPR_NOACCESS, SPR_NOACCESS,
5653                 &spr_read_generic, &spr_write_generic,
5654                 0x00000000);
5655    /* XXX : not implemented */
5656    spr_register(env, SPR_7XX_PMC3, "PMC3",
5657                 SPR_NOACCESS, SPR_NOACCESS,
5658                 &spr_read_generic, &spr_write_generic,
5659                 0x00000000);
5660    /* XXX : not implemented */
5661    spr_register(env, SPR_7XX_PMC4, "PMC4",
5662                 SPR_NOACCESS, SPR_NOACCESS,
5663                 &spr_read_generic, &spr_write_generic,
5664                 0x00000000);
5665    /* Time base */
5666    gen_tbl(env);
5667    /* Hardware implementation registers */
5668    /* XXX : not implemented */
5669    spr_register(env, SPR_HID0, "HID0",
5670                 SPR_NOACCESS, SPR_NOACCESS,
5671                 &spr_read_generic, &spr_write_generic,
5672                 0x00000000);
5673    /* XXX : not implemented */
5674    spr_register(env, SPR_HID1, "HID1",
5675                 SPR_NOACCESS, SPR_NOACCESS,
5676                 &spr_read_generic, &spr_write_generic,
5677                 0x00000000);
5678    /* Memory management */
5679    gen_low_BATs(env);
5680    init_excp_604(env);
5681    env->dcache_line_size = 32;
5682    env->icache_line_size = 32;
5683    /* Allocate hardware IRQ controller */
5684    ppc6xx_irq_init(ppc_env_get_cpu(env));
5685}
5686
5687POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
5688{
5689    DeviceClass *dc = DEVICE_CLASS(oc);
5690    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5691
5692    dc->desc = "PowerPC 604E";
5693    pcc->init_proc = init_proc_604E;
5694    pcc->check_pow = check_pow_nocheck;
5695    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5696                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5697                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5698                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5699                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
5700                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5701                       PPC_SEGMENT | PPC_EXTERN;
5702    pcc->msr_mask = (1ull << MSR_POW) |
5703                    (1ull << MSR_ILE) |
5704                    (1ull << MSR_EE) |
5705                    (1ull << MSR_PR) |
5706                    (1ull << MSR_FP) |
5707                    (1ull << MSR_ME) |
5708                    (1ull << MSR_FE0) |
5709                    (1ull << MSR_SE) |
5710                    (1ull << MSR_DE) |
5711                    (1ull << MSR_FE1) |
5712                    (1ull << MSR_EP) |
5713                    (1ull << MSR_IR) |
5714                    (1ull << MSR_DR) |
5715                    (1ull << MSR_PMM) |
5716                    (1ull << MSR_RI) |
5717                    (1ull << MSR_LE);
5718    pcc->mmu_model = POWERPC_MMU_32B;
5719#if defined(CONFIG_SOFTMMU)
5720    pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5721#endif
5722    pcc->excp_model = POWERPC_EXCP_604;
5723    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5724    pcc->bfd_mach = bfd_mach_ppc_604;
5725    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5726                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5727}
5728
5729static void init_proc_740(CPUPPCState *env)
5730{
5731    gen_spr_ne_601(env);
5732    gen_spr_sdr1(env);
5733    gen_spr_7xx(env);
5734    /* Time base */
5735    gen_tbl(env);
5736    /* Thermal management */
5737    gen_spr_thrm(env);
5738    /* Hardware implementation registers */
5739    /* XXX : not implemented */
5740    spr_register(env, SPR_HID0, "HID0",
5741                 SPR_NOACCESS, SPR_NOACCESS,
5742                 &spr_read_generic, &spr_write_generic,
5743                 0x00000000);
5744    /* XXX : not implemented */
5745    spr_register(env, SPR_HID1, "HID1",
5746                 SPR_NOACCESS, SPR_NOACCESS,
5747                 &spr_read_generic, &spr_write_generic,
5748                 0x00000000);
5749    /* Memory management */
5750    gen_low_BATs(env);
5751    init_excp_7x0(env);
5752    env->dcache_line_size = 32;
5753    env->icache_line_size = 32;
5754    /* Allocate hardware IRQ controller */
5755    ppc6xx_irq_init(ppc_env_get_cpu(env));
5756}
5757
5758POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
5759{
5760    DeviceClass *dc = DEVICE_CLASS(oc);
5761    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5762
5763    dc->desc = "PowerPC 740";
5764    pcc->init_proc = init_proc_740;
5765    pcc->check_pow = check_pow_hid0;
5766    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5767                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5768                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5769                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5770                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
5771                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5772                       PPC_SEGMENT | PPC_EXTERN;
5773    pcc->msr_mask = (1ull << MSR_POW) |
5774                    (1ull << MSR_ILE) |
5775                    (1ull << MSR_EE) |
5776                    (1ull << MSR_PR) |
5777                    (1ull << MSR_FP) |
5778                    (1ull << MSR_ME) |
5779                    (1ull << MSR_FE0) |
5780                    (1ull << MSR_SE) |
5781                    (1ull << MSR_DE) |
5782                    (1ull << MSR_FE1) |
5783                    (1ull << MSR_EP) |
5784                    (1ull << MSR_IR) |
5785                    (1ull << MSR_DR) |
5786                    (1ull << MSR_PMM) |
5787                    (1ull << MSR_RI) |
5788                    (1ull << MSR_LE);
5789    pcc->mmu_model = POWERPC_MMU_32B;
5790#if defined(CONFIG_SOFTMMU)
5791    pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5792#endif
5793    pcc->excp_model = POWERPC_EXCP_7x0;
5794    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5795    pcc->bfd_mach = bfd_mach_ppc_750;
5796    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5797                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5798}
5799
5800static void init_proc_750(CPUPPCState *env)
5801{
5802    gen_spr_ne_601(env);
5803    gen_spr_sdr1(env);
5804    gen_spr_7xx(env);
5805    /* XXX : not implemented */
5806    spr_register(env, SPR_L2CR, "L2CR",
5807                 SPR_NOACCESS, SPR_NOACCESS,
5808                 &spr_read_generic, spr_access_nop,
5809                 0x00000000);
5810    /* Time base */
5811    gen_tbl(env);
5812    /* Thermal management */
5813    gen_spr_thrm(env);
5814    /* Hardware implementation registers */
5815    /* XXX : not implemented */
5816    spr_register(env, SPR_HID0, "HID0",
5817                 SPR_NOACCESS, SPR_NOACCESS,
5818                 &spr_read_generic, &spr_write_generic,
5819                 0x00000000);
5820    /* XXX : not implemented */
5821    spr_register(env, SPR_HID1, "HID1",
5822                 SPR_NOACCESS, SPR_NOACCESS,
5823                 &spr_read_generic, &spr_write_generic,
5824                 0x00000000);
5825    /* Memory management */
5826    gen_low_BATs(env);
5827    /* XXX: high BATs are also present but are known to be bugged on
5828     *      die version 1.x
5829     */
5830    init_excp_7x0(env);
5831    env->dcache_line_size = 32;
5832    env->icache_line_size = 32;
5833    /* Allocate hardware IRQ controller */
5834    ppc6xx_irq_init(ppc_env_get_cpu(env));
5835}
5836
5837POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
5838{
5839    DeviceClass *dc = DEVICE_CLASS(oc);
5840    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5841
5842    dc->desc = "PowerPC 750";
5843    pcc->init_proc = init_proc_750;
5844    pcc->check_pow = check_pow_hid0;
5845    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5846                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5847                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5848                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5849                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
5850                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5851                       PPC_SEGMENT | PPC_EXTERN;
5852    pcc->msr_mask = (1ull << MSR_POW) |
5853                    (1ull << MSR_ILE) |
5854                    (1ull << MSR_EE) |
5855                    (1ull << MSR_PR) |
5856                    (1ull << MSR_FP) |
5857                    (1ull << MSR_ME) |
5858                    (1ull << MSR_FE0) |
5859                    (1ull << MSR_SE) |
5860                    (1ull << MSR_DE) |
5861                    (1ull << MSR_FE1) |
5862                    (1ull << MSR_EP) |
5863                    (1ull << MSR_IR) |
5864                    (1ull << MSR_DR) |
5865                    (1ull << MSR_PMM) |
5866                    (1ull << MSR_RI) |
5867                    (1ull << MSR_LE);
5868    pcc->mmu_model = POWERPC_MMU_32B;
5869#if defined(CONFIG_SOFTMMU)
5870    pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5871#endif
5872    pcc->excp_model = POWERPC_EXCP_7x0;
5873    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5874    pcc->bfd_mach = bfd_mach_ppc_750;
5875    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5876                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5877}
5878
5879static void init_proc_750cl(CPUPPCState *env)
5880{
5881    gen_spr_ne_601(env);
5882    gen_spr_sdr1(env);
5883    gen_spr_7xx(env);
5884    /* XXX : not implemented */
5885    spr_register(env, SPR_L2CR, "L2CR",
5886                 SPR_NOACCESS, SPR_NOACCESS,
5887                 &spr_read_generic, spr_access_nop,
5888                 0x00000000);
5889    /* Time base */
5890    gen_tbl(env);
5891    /* Thermal management */
5892    /* Those registers are fake on 750CL */
5893    spr_register(env, SPR_THRM1, "THRM1",
5894                 SPR_NOACCESS, SPR_NOACCESS,
5895                 &spr_read_generic, &spr_write_generic,
5896                 0x00000000);
5897    spr_register(env, SPR_THRM2, "THRM2",
5898                 SPR_NOACCESS, SPR_NOACCESS,
5899                 &spr_read_generic, &spr_write_generic,
5900                 0x00000000);
5901    spr_register(env, SPR_THRM3, "THRM3",
5902                 SPR_NOACCESS, SPR_NOACCESS,
5903                 &spr_read_generic, &spr_write_generic,
5904                 0x00000000);
5905    /* XXX: not implemented */
5906    spr_register(env, SPR_750_TDCL, "TDCL",
5907                 SPR_NOACCESS, SPR_NOACCESS,
5908                 &spr_read_generic, &spr_write_generic,
5909                 0x00000000);
5910    spr_register(env, SPR_750_TDCH, "TDCH",
5911                 SPR_NOACCESS, SPR_NOACCESS,
5912                 &spr_read_generic, &spr_write_generic,
5913                 0x00000000);
5914    /* DMA */
5915    /* XXX : not implemented */
5916    spr_register(env, SPR_750_WPAR, "WPAR",
5917                 SPR_NOACCESS, SPR_NOACCESS,
5918                 &spr_read_generic, &spr_write_generic,
5919                 0x00000000);
5920    spr_register(env, SPR_750_DMAL, "DMAL",
5921                 SPR_NOACCESS, SPR_NOACCESS,
5922                 &spr_read_generic, &spr_write_generic,
5923                 0x00000000);
5924    spr_register(env, SPR_750_DMAU, "DMAU",
5925                 SPR_NOACCESS, SPR_NOACCESS,
5926                 &spr_read_generic, &spr_write_generic,
5927                 0x00000000);
5928    /* Hardware implementation registers */
5929    /* XXX : not implemented */
5930    spr_register(env, SPR_HID0, "HID0",
5931                 SPR_NOACCESS, SPR_NOACCESS,
5932                 &spr_read_generic, &spr_write_generic,
5933                 0x00000000);
5934    /* XXX : not implemented */
5935    spr_register(env, SPR_HID1, "HID1",
5936                 SPR_NOACCESS, SPR_NOACCESS,
5937                 &spr_read_generic, &spr_write_generic,
5938                 0x00000000);
5939    /* XXX : not implemented */
5940    spr_register(env, SPR_750CL_HID2, "HID2",
5941                 SPR_NOACCESS, SPR_NOACCESS,
5942                 &spr_read_generic, &spr_write_generic,
5943                 0x00000000);
5944    /* XXX : not implemented */
5945    spr_register(env, SPR_750CL_HID4, "HID4",
5946                 SPR_NOACCESS, SPR_NOACCESS,
5947                 &spr_read_generic, &spr_write_generic,
5948                 0x00000000);
5949    /* Quantization registers */
5950    /* XXX : not implemented */
5951    spr_register(env, SPR_750_GQR0, "GQR0",
5952                 SPR_NOACCESS, SPR_NOACCESS,
5953                 &spr_read_generic, &spr_write_generic,
5954                 0x00000000);
5955    /* XXX : not implemented */
5956    spr_register(env, SPR_750_GQR1, "GQR1",
5957                 SPR_NOACCESS, SPR_NOACCESS,
5958                 &spr_read_generic, &spr_write_generic,
5959                 0x00000000);
5960    /* XXX : not implemented */
5961    spr_register(env, SPR_750_GQR2, "GQR2",
5962                 SPR_NOACCESS, SPR_NOACCESS,
5963                 &spr_read_generic, &spr_write_generic,
5964                 0x00000000);
5965    /* XXX : not implemented */
5966    spr_register(env, SPR_750_GQR3, "GQR3",
5967                 SPR_NOACCESS, SPR_NOACCESS,
5968                 &spr_read_generic, &spr_write_generic,
5969                 0x00000000);
5970    /* XXX : not implemented */
5971    spr_register(env, SPR_750_GQR4, "GQR4",
5972                 SPR_NOACCESS, SPR_NOACCESS,
5973                 &spr_read_generic, &spr_write_generic,
5974                 0x00000000);
5975    /* XXX : not implemented */
5976    spr_register(env, SPR_750_GQR5, "GQR5",
5977                 SPR_NOACCESS, SPR_NOACCESS,
5978                 &spr_read_generic, &spr_write_generic,
5979                 0x00000000);
5980    /* XXX : not implemented */
5981    spr_register(env, SPR_750_GQR6, "GQR6",
5982                 SPR_NOACCESS, SPR_NOACCESS,
5983                 &spr_read_generic, &spr_write_generic,
5984                 0x00000000);
5985    /* XXX : not implemented */
5986    spr_register(env, SPR_750_GQR7, "GQR7",
5987                 SPR_NOACCESS, SPR_NOACCESS,
5988                 &spr_read_generic, &spr_write_generic,
5989                 0x00000000);
5990    /* Memory management */
5991    gen_low_BATs(env);
5992    /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5993    gen_high_BATs(env);
5994    init_excp_750cl(env);
5995    env->dcache_line_size = 32;
5996    env->icache_line_size = 32;
5997    /* Allocate hardware IRQ controller */
5998    ppc6xx_irq_init(ppc_env_get_cpu(env));
5999}
6000

6001POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
6002{
6003    DeviceClass *dc = DEVICE_CLASS(oc);
6004    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6005
6006    dc->desc = "PowerPC 750 CL";
6007    pcc->init_proc = init_proc_750cl;
6008    pcc->check_pow = check_pow_hid0;
6009    /* XXX: not implemented:
6010     * cache lock instructions:
6011     * dcbz_l
6012     * floating point paired instructions
6013     * psq_lux
6014     * psq_lx
6015     * psq_stux
6016     * psq_stx
6017     * ps_abs
6018     * ps_add
6019     * ps_cmpo0
6020     * ps_cmpo1
6021     * ps_cmpu0
6022     * ps_cmpu1
6023     * ps_div
6024     * ps_madd
6025     * ps_madds0
6026     * ps_madds1
6027     * ps_merge00
6028     * ps_merge01
6029     * ps_merge10
6030     * ps_merge11
6031     * ps_mr
6032     * ps_msub
6033     * ps_mul
6034     * ps_muls0
6035     * ps_muls1
6036     * ps_nabs
6037     * ps_neg
6038     * ps_nmadd
6039     * ps_nmsub
6040     * ps_res
6041     * ps_rsqrte
6042     * ps_sel
6043     * ps_sub
6044     * ps_sum0
6045     * ps_sum1
6046     */
6047    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6048                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6049                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6050                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6051                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
6052                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6053                       PPC_SEGMENT | PPC_EXTERN;
6054    pcc->msr_mask = (1ull << MSR_POW) |
6055                    (1ull << MSR_ILE) |
6056                    (1ull << MSR_EE) |
6057                    (1ull << MSR_PR) |
6058                    (1ull << MSR_FP) |
6059                    (1ull << MSR_ME) |
6060                    (1ull << MSR_FE0) |
6061                    (1ull << MSR_SE) |
6062                    (1ull << MSR_DE) |
6063                    (1ull << MSR_FE1) |
6064                    (1ull << MSR_EP) |
6065                    (1ull << MSR_IR) |
6066                    (1ull << MSR_DR) |
6067                    (1ull << MSR_PMM) |
6068                    (1ull << MSR_RI) |
6069                    (1ull << MSR_LE);
6070    pcc->mmu_model = POWERPC_MMU_32B;
6071#if defined(CONFIG_SOFTMMU)
6072    pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6073#endif
6074    pcc->excp_model = POWERPC_EXCP_7x0;
6075    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6076    pcc->bfd_mach = bfd_mach_ppc_750;
6077    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6078                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6079}
6080
6081static void init_proc_750cx(CPUPPCState *env)
6082{
6083    gen_spr_ne_601(env);
6084    gen_spr_sdr1(env);
6085    gen_spr_7xx(env);
6086    /* XXX : not implemented */
6087    spr_register(env, SPR_L2CR, "L2CR",
6088                 SPR_NOACCESS, SPR_NOACCESS,
6089                 &spr_read_generic, spr_access_nop,
6090                 0x00000000);
6091    /* Time base */
6092    gen_tbl(env);
6093    /* Thermal management */
6094    gen_spr_thrm(env);
6095    /* This register is not implemented but is present for compatibility */
6096    spr_register(env, SPR_SDA, "SDA",
6097                 SPR_NOACCESS, SPR_NOACCESS,
6098                 &spr_read_generic, &spr_write_generic,
6099                 0x00000000);
6100    /* Hardware implementation registers */
6101    /* XXX : not implemented */
6102    spr_register(env, SPR_HID0, "HID0",
6103                 SPR_NOACCESS, SPR_NOACCESS,
6104                 &spr_read_generic, &spr_write_generic,
6105                 0x00000000);
6106    /* XXX : not implemented */
6107    spr_register(env, SPR_HID1, "HID1",
6108                 SPR_NOACCESS, SPR_NOACCESS,
6109                 &spr_read_generic, &spr_write_generic,
6110                 0x00000000);
6111    /* Memory management */
6112    gen_low_BATs(env);
6113    /* PowerPC 750cx has 8 DBATs and 8 IBATs */
6114    gen_high_BATs(env);
6115    init_excp_750cx(env);
6116    env->dcache_line_size = 32;
6117    env->icache_line_size = 32;
6118    /* Allocate hardware IRQ controller */
6119    ppc6xx_irq_init(ppc_env_get_cpu(env));
6120}
6121
6122POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
6123{
6124    DeviceClass *dc = DEVICE_CLASS(oc);
6125    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6126
6127    dc->desc = "PowerPC 750CX";
6128    pcc->init_proc = init_proc_750cx;
6129    pcc->check_pow = check_pow_hid0;
6130    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6131                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6132                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6133                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6134                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
6135                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6136                       PPC_SEGMENT | PPC_EXTERN;
6137    pcc->msr_mask = (1ull << MSR_POW) |
6138                    (1ull << MSR_ILE) |
6139                    (1ull << MSR_EE) |
6140                    (1ull << MSR_PR) |
6141                    (1ull << MSR_FP) |
6142                    (1ull << MSR_ME) |
6143                    (1ull << MSR_FE0) |
6144                    (1ull << MSR_SE) |
6145                    (1ull << MSR_DE) |
6146                    (1ull << MSR_FE1) |
6147                    (1ull << MSR_EP) |
6148                    (1ull << MSR_IR) |
6149                    (1ull << MSR_DR) |
6150                    (1ull << MSR_PMM) |
6151                    (1ull << MSR_RI) |
6152                    (1ull << MSR_LE);
6153    pcc->mmu_model = POWERPC_MMU_32B;
6154#if defined(CONFIG_SOFTMMU)
6155    pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6156#endif
6157    pcc->excp_model = POWERPC_EXCP_7x0;
6158    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6159    pcc->bfd_mach = bfd_mach_ppc_750;
6160    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6161                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6162}
6163
6164static void init_proc_750fx(CPUPPCState *env)
6165{
6166    gen_spr_ne_601(env);
6167    gen_spr_sdr1(env);
6168    gen_spr_7xx(env);
6169    /* XXX : not implemented */
6170    spr_register(env, SPR_L2CR, "L2CR",
6171                 SPR_NOACCESS, SPR_NOACCESS,
6172                 &spr_read_generic, spr_access_nop,
6173                 0x00000000);
6174    /* Time base */
6175    gen_tbl(env);
6176    /* Thermal management */
6177    gen_spr_thrm(env);
6178    /* XXX : not implemented */
6179    spr_register(env, SPR_750_THRM4, "THRM4",
6180                 SPR_NOACCESS, SPR_NOACCESS,
6181                 &spr_read_generic, &spr_write_generic,
6182                 0x00000000);
6183    /* Hardware implementation registers */
6184    /* XXX : not implemented */
6185    spr_register(env, SPR_HID0, "HID0",
6186                 SPR_NOACCESS, SPR_NOACCESS,
6187                 &spr_read_generic, &spr_write_generic,
6188                 0x00000000);
6189    /* XXX : not implemented */
6190    spr_register(env, SPR_HID1, "HID1",
6191                 SPR_NOACCESS, SPR_NOACCESS,
6192                 &spr_read_generic, &spr_write_generic,
6193                 0x00000000);
6194    /* XXX : not implemented */
6195    spr_register(env, SPR_750FX_HID2, "HID2",
6196                 SPR_NOACCESS, SPR_NOACCESS,
6197                 &spr_read_generic, &spr_write_generic,
6198                 0x00000000);
6199    /* Memory management */
6200    gen_low_BATs(env);
6201    /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
6202    gen_high_BATs(env);
6203    init_excp_7x0(env);
6204    env->dcache_line_size = 32;
6205    env->icache_line_size = 32;
6206    /* Allocate hardware IRQ controller */
6207    ppc6xx_irq_init(ppc_env_get_cpu(env));
6208}
6209
6210POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
6211{
6212    DeviceClass *dc = DEVICE_CLASS(oc);
6213    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6214
6215    dc->desc = "PowerPC 750FX";
6216    pcc->init_proc = init_proc_750fx;
6217    pcc->check_pow = check_pow_hid0;
6218    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6219                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6220                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6221                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6222                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
6223                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6224                       PPC_SEGMENT | PPC_EXTERN;
6225    pcc->msr_mask = (1ull << MSR_POW) |
6226                    (1ull << MSR_ILE) |
6227                    (1ull << MSR_EE) |
6228                    (1ull << MSR_PR) |
6229                    (1ull << MSR_FP) |
6230                    (1ull << MSR_ME) |
6231                    (1ull << MSR_FE0) |
6232                    (1ull << MSR_SE) |
6233                    (1ull << MSR_DE) |
6234                    (1ull << MSR_FE1) |
6235                    (1ull << MSR_EP) |
6236                    (1ull << MSR_IR) |
6237                    (1ull << MSR_DR) |
6238                    (1ull << MSR_PMM) |
6239                    (1ull << MSR_RI) |
6240                    (1ull << MSR_LE);
6241    pcc->mmu_model = POWERPC_MMU_32B;
6242#if defined(CONFIG_SOFTMMU)
6243    pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6244#endif
6245    pcc->excp_model = POWERPC_EXCP_7x0;
6246    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6247    pcc->bfd_mach = bfd_mach_ppc_750;
6248    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6249                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6250}
6251
6252static void init_proc_750gx(CPUPPCState *env)
6253{
6254    gen_spr_ne_601(env);
6255    gen_spr_sdr1(env);
6256    gen_spr_7xx(env);
6257    /* XXX : not implemented (XXX: different from 750fx) */
6258    spr_register(env, SPR_L2CR, "L2CR",
6259                 SPR_NOACCESS, SPR_NOACCESS,
6260                 &spr_read_generic, spr_access_nop,
6261                 0x00000000);
6262    /* Time base */
6263    gen_tbl(env);
6264    /* Thermal management */
6265    gen_spr_thrm(env);
6266    /* XXX : not implemented */
6267    spr_register(env, SPR_750_THRM4, "THRM4",
6268                 SPR_NOACCESS, SPR_NOACCESS,
6269                 &spr_read_generic, &spr_write_generic,
6270                 0x00000000);
6271    /* Hardware implementation registers */
6272    /* XXX : not implemented (XXX: different from 750fx) */
6273    spr_register(env, SPR_HID0, "HID0",
6274                 SPR_NOACCESS, SPR_NOACCESS,
6275                 &spr_read_generic, &spr_write_generic,
6276                 0x00000000);
6277    /* XXX : not implemented */
6278    spr_register(env, SPR_HID1, "HID1",
6279                 SPR_NOACCESS, SPR_NOACCESS,
6280                 &spr_read_generic, &spr_write_generic,
6281                 0x00000000);
6282    /* XXX : not implemented (XXX: different from 750fx) */
6283    spr_register(env, SPR_750FX_HID2, "HID2",
6284                 SPR_NOACCESS, SPR_NOACCESS,
6285                 &spr_read_generic, &spr_write_generic,
6286                 0x00000000);
6287    /* Memory management */
6288    gen_low_BATs(env);
6289    /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
6290    gen_high_BATs(env);
6291    init_excp_7x0(env);
6292    env->dcache_line_size = 32;
6293    env->icache_line_size = 32;
6294    /* Allocate hardware IRQ controller */
6295    ppc6xx_irq_init(ppc_env_get_cpu(env));
6296}
6297
6298POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
6299{
6300    DeviceClass *dc = DEVICE_CLASS(oc);
6301    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6302
6303    dc->desc = "PowerPC 750GX";
6304    pcc->init_proc = init_proc_750gx;
6305    pcc->check_pow = check_pow_hid0;
6306    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6307                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6308                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6309                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6310                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
6311                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6312                       PPC_SEGMENT | PPC_EXTERN;
6313    pcc->msr_mask = (1ull << MSR_POW) |
6314                    (1ull << MSR_ILE) |
6315                    (1ull << MSR_EE) |
6316                    (1ull << MSR_PR) |
6317                    (1ull << MSR_FP) |
6318                    (1ull << MSR_ME) |
6319                    (1ull << MSR_FE0) |
6320                    (1ull << MSR_SE) |
6321                    (1ull << MSR_DE) |
6322                    (1ull << MSR_FE1) |
6323                    (1ull << MSR_EP) |
6324                    (1ull << MSR_IR) |
6325                    (1ull << MSR_DR) |
6326                    (1ull << MSR_PMM) |
6327                    (1ull << MSR_RI) |
6328                    (1ull << MSR_LE);
6329    pcc->mmu_model = POWERPC_MMU_32B;
6330#if defined(CONFIG_SOFTMMU)
6331    pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6332#endif
6333    pcc->excp_model = POWERPC_EXCP_7x0;
6334    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6335    pcc->bfd_mach = bfd_mach_ppc_750;
6336    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6337                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6338}
6339
6340static void init_proc_745(CPUPPCState *env)
6341{
6342    gen_spr_ne_601(env);
6343    gen_spr_sdr1(env);
6344    gen_spr_7xx(env);
6345    gen_spr_G2_755(env);
6346    /* Time base */
6347    gen_tbl(env);
6348    /* Thermal management */
6349    gen_spr_thrm(env);
6350    /* Hardware implementation registers */
6351    /* XXX : not implemented */
6352    spr_register(env, SPR_HID0, "HID0",
6353                 SPR_NOACCESS, SPR_NOACCESS,
6354                 &spr_read_generic, &spr_write_generic,
6355                 0x00000000);
6356    /* XXX : not implemented */
6357    spr_register(env, SPR_HID1, "HID1",
6358                 SPR_NOACCESS, SPR_NOACCESS,
6359                 &spr_read_generic, &spr_write_generic,
6360                 0x00000000);
6361    /* XXX : not implemented */
6362    spr_register(env, SPR_HID2, "HID2",
6363                 SPR_NOACCESS, SPR_NOACCESS,
6364                 &spr_read_generic, &spr_write_generic,
6365                 0x00000000);
6366    /* Memory management */
6367    gen_low_BATs(env);
6368    gen_high_BATs(env);
6369    gen_6xx_7xx_soft_tlb(env, 64, 2);
6370    init_excp_7x5(env);
6371    env->dcache_line_size = 32;
6372    env->icache_line_size = 32;
6373    /* Allocate hardware IRQ controller */
6374    ppc6xx_irq_init(ppc_env_get_cpu(env));
6375}
6376
6377POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
6378{
6379    DeviceClass *dc = DEVICE_CLASS(oc);
6380    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6381
6382    dc->desc = "PowerPC 745";
6383    pcc->init_proc = init_proc_745;
6384    pcc->check_pow = check_pow_hid0;
6385    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6386                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6387                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6388                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6389                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
6390                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
6391                       PPC_SEGMENT | PPC_EXTERN;
6392    pcc->msr_mask = (1ull << MSR_POW) |
6393                    (1ull << MSR_ILE) |
6394                    (1ull << MSR_EE) |
6395                    (1ull << MSR_PR) |
6396                    (1ull << MSR_FP) |
6397                    (1ull << MSR_ME) |
6398                    (1ull << MSR_FE0) |
6399                    (1ull << MSR_SE) |
6400                    (1ull << MSR_DE) |
6401                    (1ull << MSR_FE1) |
6402                    (1ull << MSR_EP) |
6403                    (1ull << MSR_IR) |
6404                    (1ull << MSR_DR) |
6405                    (1ull << MSR_PMM) |
6406                    (1ull << MSR_RI) |
6407                    (1ull << MSR_LE);
6408    pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
6409    pcc->excp_model = POWERPC_EXCP_7x5;
6410    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6411    pcc->bfd_mach = bfd_mach_ppc_750;
6412    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6413                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6414}
6415
6416static void init_proc_755(CPUPPCState *env)
6417{
6418    gen_spr_ne_601(env);
6419    gen_spr_sdr1(env);
6420    gen_spr_7xx(env);
6421    gen_spr_G2_755(env);
6422    /* Time base */
6423    gen_tbl(env);
6424    /* L2 cache control */
6425    /* XXX : not implemented */
6426    spr_register(env, SPR_L2CR, "L2CR",
6427                 SPR_NOACCESS, SPR_NOACCESS,
6428                 &spr_read_generic, spr_access_nop,
6429                 0x00000000);
6430    /* XXX : not implemented */
6431    spr_register(env, SPR_L2PMCR, "L2PMCR",
6432                 SPR_NOACCESS, SPR_NOACCESS,
6433                 &spr_read_generic, &spr_write_generic,
6434                 0x00000000);
6435    /* Thermal management */
6436    gen_spr_thrm(env);
6437    /* Hardware implementation registers */
6438    /* XXX : not implemented */
6439    spr_register(env, SPR_HID0, "HID0",
6440                 SPR_NOACCESS, SPR_NOACCESS,
6441                 &spr_read_generic, &spr_write_generic,
6442                 0x00000000);
6443    /* XXX : not implemented */
6444    spr_register(env, SPR_HID1, "HID1",
6445                 SPR_NOACCESS, SPR_NOACCESS,
6446                 &spr_read_generic, &spr_write_generic,
6447                 0x00000000);
6448    /* XXX : not implemented */
6449    spr_register(env, SPR_HID2, "HID2",
6450                 SPR_NOACCESS, SPR_NOACCESS,
6451                 &spr_read_generic, &spr_write_generic,
6452                 0x00000000);
6453    /* Memory management */
6454    gen_low_BATs(env);
6455    gen_high_BATs(env);
6456    gen_6xx_7xx_soft_tlb(env, 64, 2);
6457    init_excp_7x5(env);
6458    env->dcache_line_size = 32;
6459    env->icache_line_size = 32;
6460    /* Allocate hardware IRQ controller */
6461    ppc6xx_irq_init(ppc_env_get_cpu(env));
6462}
6463
6464POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
6465{
6466    DeviceClass *dc = DEVICE_CLASS(oc);
6467    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6468
6469    dc->desc = "PowerPC 755";
6470    pcc->init_proc = init_proc_755;
6471    pcc->check_pow = check_pow_hid0;
6472    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6473                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6474                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6475                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6476                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
6477                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
6478                       PPC_SEGMENT | PPC_EXTERN;
6479    pcc->msr_mask = (1ull << MSR_POW) |
6480                    (1ull << MSR_ILE) |
6481                    (1ull << MSR_EE) |
6482                    (1ull << MSR_PR) |
6483                    (1ull << MSR_FP) |
6484                    (1ull << MSR_ME) |
6485                    (1ull << MSR_FE0) |
6486                    (1ull << MSR_SE) |
6487                    (1ull << MSR_DE) |
6488                    (1ull << MSR_FE1) |
6489                    (1ull << MSR_EP) |
6490                    (1ull << MSR_IR) |
6491                    (1ull << MSR_DR) |
6492                    (1ull << MSR_PMM) |
6493                    (1ull << MSR_RI) |
6494                    (1ull << MSR_LE);
6495    pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
6496    pcc->excp_model = POWERPC_EXCP_7x5;
6497    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6498    pcc->bfd_mach = bfd_mach_ppc_750;
6499    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6500                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6501}
6502
6503static void init_proc_7400(CPUPPCState *env)
6504{
6505    gen_spr_ne_601(env);
6506    gen_spr_sdr1(env);
6507    gen_spr_7xx(env);
6508    /* Time base */
6509    gen_tbl(env);
6510    /* 74xx specific SPR */
6511    gen_spr_74xx(env);
6512    /* XXX : not implemented */
6513    spr_register(env, SPR_UBAMR, "UBAMR",
6514                 &spr_read_ureg, SPR_NOACCESS,
6515                 &spr_read_ureg, SPR_NOACCESS,
6516                 0x00000000);
6517    /* XXX: this seems not implemented on all revisions. */
6518    /* XXX : not implemented */
6519    spr_register(env, SPR_MSSCR1, "MSSCR1",
6520                 SPR_NOACCESS, SPR_NOACCESS,
6521                 &spr_read_generic, &spr_write_generic,
6522                 0x00000000);
6523    /* Thermal management */
6524    gen_spr_thrm(env);
6525    /* Memory management */
6526    gen_low_BATs(env);
6527    init_excp_7400(env);
6528    env->dcache_line_size = 32;
6529    env->icache_line_size = 32;
6530    /* Allocate hardware IRQ controller */
6531    ppc6xx_irq_init(ppc_env_get_cpu(env));
6532}
6533
6534POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
6535{
6536    DeviceClass *dc = DEVICE_CLASS(oc);
6537    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6538
6539    dc->desc = "PowerPC 7400 (aka G4)";
6540    pcc->init_proc = init_proc_7400;
6541    pcc->check_pow = check_pow_hid0;
6542    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6543                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6544                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6545                       PPC_FLOAT_STFIWX |
6546                       PPC_CACHE | PPC_CACHE_ICBI |
6547                       PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6548                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
6549                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6550                       PPC_MEM_TLBIA |
6551                       PPC_SEGMENT | PPC_EXTERN |
6552                       PPC_ALTIVEC;
6553    pcc->msr_mask = (1ull << MSR_VR) |
6554                    (1ull << MSR_POW) |
6555                    (1ull << MSR_ILE) |
6556                    (1ull << MSR_EE) |
6557                    (1ull << MSR_PR) |
6558                    (1ull << MSR_FP) |
6559                    (1ull << MSR_ME) |
6560                    (1ull << MSR_FE0) |
6561                    (1ull << MSR_SE) |
6562                    (1ull << MSR_DE) |
6563                    (1ull << MSR_FE1) |
6564                    (1ull << MSR_EP) |
6565                    (1ull << MSR_IR) |
6566                    (1ull << MSR_DR) |
6567                    (1ull << MSR_PMM) |
6568                    (1ull << MSR_RI) |
6569                    (1ull << MSR_LE);
6570    pcc->mmu_model = POWERPC_MMU_32B;
6571#if defined(CONFIG_SOFTMMU)
6572    pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6573#endif
6574    pcc->excp_model = POWERPC_EXCP_74xx;
6575    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6576    pcc->bfd_mach = bfd_mach_ppc_7400;
6577    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6578                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6579                 POWERPC_FLAG_BUS_CLK;
6580}
6581
6582static void init_proc_7410(CPUPPCState *env)
6583{
6584    gen_spr_ne_601(env);
6585    gen_spr_sdr1(env);
6586    gen_spr_7xx(env);
6587    /* Time base */
6588    gen_tbl(env);
6589    /* 74xx specific SPR */
6590    gen_spr_74xx(env);
6591    /* XXX : not implemented */
6592    spr_register(env, SPR_UBAMR, "UBAMR",
6593                 &spr_read_ureg, SPR_NOACCESS,
6594                 &spr_read_ureg, SPR_NOACCESS,
6595                 0x00000000);
6596    /* Thermal management */
6597    gen_spr_thrm(env);
6598    /* L2PMCR */
6599    /* XXX : not implemented */
6600    spr_register(env, SPR_L2PMCR, "L2PMCR",
6601                 SPR_NOACCESS, SPR_NOACCESS,
6602                 &spr_read_generic, &spr_write_generic,
6603                 0x00000000);
6604    /* LDSTDB */
6605    /* XXX : not implemented */
6606    spr_register(env, SPR_LDSTDB, "LDSTDB",
6607                 SPR_NOACCESS, SPR_NOACCESS,
6608                 &spr_read_generic, &spr_write_generic,
6609                 0x00000000);
6610    /* Memory management */
6611    gen_low_BATs(env);
6612    init_excp_7400(env);
6613    env->dcache_line_size = 32;
6614    env->icache_line_size = 32;
6615    /* Allocate hardware IRQ controller */
6616    ppc6xx_irq_init(ppc_env_get_cpu(env));
6617}
6618
6619POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
6620{
6621    DeviceClass *dc = DEVICE_CLASS(oc);
6622    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6623
6624    dc->desc = "PowerPC 7410 (aka G4)";
6625    pcc->init_proc = init_proc_7410;
6626    pcc->check_pow = check_pow_hid0;
6627    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6628                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6629                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6630                       PPC_FLOAT_STFIWX |
6631                       PPC_CACHE | PPC_CACHE_ICBI |
6632                       PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6633                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
6634                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6635                       PPC_MEM_TLBIA |
6636                       PPC_SEGMENT | PPC_EXTERN |
6637                       PPC_ALTIVEC;
6638    pcc->msr_mask = (1ull << MSR_VR) |
6639                    (1ull << MSR_POW) |
6640                    (1ull << MSR_ILE) |
6641                    (1ull << MSR_EE) |
6642                    (1ull << MSR_PR) |
6643                    (1ull << MSR_FP) |
6644                    (1ull << MSR_ME) |
6645                    (1ull << MSR_FE0) |
6646                    (1ull << MSR_SE) |
6647                    (1ull << MSR_DE) |
6648                    (1ull << MSR_FE1) |
6649                    (1ull << MSR_EP) |
6650                    (1ull << MSR_IR) |
6651                    (1ull << MSR_DR) |
6652                    (1ull << MSR_PMM) |
6653                    (1ull << MSR_RI) |
6654                    (1ull << MSR_LE);
6655    pcc->mmu_model = POWERPC_MMU_32B;
6656#if defined(CONFIG_SOFTMMU)
6657    pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6658#endif
6659    pcc->excp_model = POWERPC_EXCP_74xx;
6660    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6661    pcc->bfd_mach = bfd_mach_ppc_7400;
6662    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6663                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6664                 POWERPC_FLAG_BUS_CLK;
6665}
6666
6667static void init_proc_7440(CPUPPCState *env)
6668{
6669    gen_spr_ne_601(env);
6670    gen_spr_sdr1(env);
6671    gen_spr_7xx(env);
6672    /* Time base */
6673    gen_tbl(env);
6674    /* 74xx specific SPR */
6675    gen_spr_74xx(env);
6676    /* XXX : not implemented */
6677    spr_register(env, SPR_UBAMR, "UBAMR",
6678                 &spr_read_ureg, SPR_NOACCESS,
6679                 &spr_read_ureg, SPR_NOACCESS,
6680                 0x00000000);
6681    /* LDSTCR */
6682    /* XXX : not implemented */
6683    spr_register(env, SPR_LDSTCR, "LDSTCR",
6684                 SPR_NOACCESS, SPR_NOACCESS,
6685                 &spr_read_generic, &spr_write_generic,
6686                 0x00000000);
6687    /* ICTRL */
6688    /* XXX : not implemented */
6689    spr_register(env, SPR_ICTRL, "ICTRL",
6690                 SPR_NOACCESS, SPR_NOACCESS,
6691                 &spr_read_generic, &spr_write_generic,
6692                 0x00000000);
6693    /* MSSSR0 */
6694    /* XXX : not implemented */
6695    spr_register(env, SPR_MSSSR0, "MSSSR0",
6696                 SPR_NOACCESS, SPR_NOACCESS,
6697                 &spr_read_generic, &spr_write_generic,
6698                 0x00000000);
6699    /* PMC */
6700    /* XXX : not implemented */
6701    spr_register(env, SPR_7XX_PMC5, "PMC5",
6702                 SPR_NOACCESS, SPR_NOACCESS,
6703                 &spr_read_generic, &spr_write_generic,
6704                 0x00000000);
6705    /* XXX : not implemented */
6706    spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6707                 &spr_read_ureg, SPR_NOACCESS,
6708                 &spr_read_ureg, SPR_NOACCESS,
6709                 0x00000000);
6710    /* XXX : not implemented */
6711    spr_register(env, SPR_7XX_PMC6, "PMC6",
6712                 SPR_NOACCESS, SPR_NOACCESS,
6713                 &spr_read_generic, &spr_write_generic,
6714                 0x00000000);
6715    /* XXX : not implemented */
6716    spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6717                 &spr_read_ureg, SPR_NOACCESS,
6718                 &spr_read_ureg, SPR_NOACCESS,
6719                 0x00000000);
6720    /* Memory management */
6721    gen_low_BATs(env);
6722    gen_74xx_soft_tlb(env, 128, 2);
6723    init_excp_7450(env);
6724    env->dcache_line_size = 32;
6725    env->icache_line_size = 32;
6726    /* Allocate hardware IRQ controller */
6727    ppc6xx_irq_init(ppc_env_get_cpu(env));
6728}
6729
6730POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
6731{
6732    DeviceClass *dc = DEVICE_CLASS(oc);
6733    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6734
6735    dc->desc = "PowerPC 7440 (aka G4)";
6736    pcc->init_proc = init_proc_7440;
6737    pcc->check_pow = check_pow_hid0_74xx;
6738    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6739                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6740                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6741                       PPC_FLOAT_STFIWX |
6742                       PPC_CACHE | PPC_CACHE_ICBI |
6743                       PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6744                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
6745                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6746                       PPC_MEM_TLBIA | PPC_74xx_TLB |
6747                       PPC_SEGMENT | PPC_EXTERN |
6748                       PPC_ALTIVEC;
6749    pcc->msr_mask = (1ull << MSR_VR) |
6750                    (1ull << MSR_POW) |
6751                    (1ull << MSR_ILE) |
6752                    (1ull << MSR_EE) |
6753                    (1ull << MSR_PR) |
6754                    (1ull << MSR_FP) |
6755                    (1ull << MSR_ME) |
6756                    (1ull << MSR_FE0) |
6757                    (1ull << MSR_SE) |
6758                    (1ull << MSR_DE) |
6759                    (1ull << MSR_FE1) |
6760                    (1ull << MSR_EP) |
6761                    (1ull << MSR_IR) |
6762                    (1ull << MSR_DR) |
6763                    (1ull << MSR_PMM) |
6764                    (1ull << MSR_RI) |
6765                    (1ull << MSR_LE);
6766    pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6767    pcc->excp_model = POWERPC_EXCP_74xx;
6768    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6769    pcc->bfd_mach = bfd_mach_ppc_7400;
6770    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6771                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6772                 POWERPC_FLAG_BUS_CLK;
6773}
6774
6775static void init_proc_7450(CPUPPCState *env)
6776{
6777    gen_spr_ne_601(env);
6778    gen_spr_sdr1(env);
6779    gen_spr_7xx(env);
6780    /* Time base */
6781    gen_tbl(env);
6782    /* 74xx specific SPR */
6783    gen_spr_74xx(env);
6784    /* Level 3 cache control */
6785    gen_l3_ctrl(env);
6786    /* L3ITCR1 */
6787    /* XXX : not implemented */
6788    spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6789                 SPR_NOACCESS, SPR_NOACCESS,
6790                 &spr_read_generic, &spr_write_generic,
6791                 0x00000000);
6792    /* L3ITCR2 */
6793    /* XXX : not implemented */
6794    spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6795                 SPR_NOACCESS, SPR_NOACCESS,
6796                 &spr_read_generic, &spr_write_generic,
6797                 0x00000000);
6798    /* L3ITCR3 */
6799    /* XXX : not implemented */
6800    spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6801                 SPR_NOACCESS, SPR_NOACCESS,
6802                 &spr_read_generic, &spr_write_generic,
6803                 0x00000000);
6804    /* L3OHCR */
6805    /* XXX : not implemented */
6806    spr_register(env, SPR_L3OHCR, "L3OHCR",
6807                 SPR_NOACCESS, SPR_NOACCESS,
6808                 &spr_read_generic, &spr_write_generic,
6809                 0x00000000);
6810    /* XXX : not implemented */
6811    spr_register(env, SPR_UBAMR, "UBAMR",
6812                 &spr_read_ureg, SPR_NOACCESS,
6813                 &spr_read_ureg, SPR_NOACCESS,
6814                 0x00000000);
6815    /* LDSTCR */
6816    /* XXX : not implemented */
6817    spr_register(env, SPR_LDSTCR, "LDSTCR",
6818                 SPR_NOACCESS, SPR_NOACCESS,
6819                 &spr_read_generic, &spr_write_generic,
6820                 0x00000000);
6821    /* ICTRL */
6822    /* XXX : not implemented */
6823    spr_register(env, SPR_ICTRL, "ICTRL",
6824                 SPR_NOACCESS, SPR_NOACCESS,
6825                 &spr_read_generic, &spr_write_generic,
6826                 0x00000000);
6827    /* MSSSR0 */
6828    /* XXX : not implemented */
6829    spr_register(env, SPR_MSSSR0, "MSSSR0",
6830                 SPR_NOACCESS, SPR_NOACCESS,
6831                 &spr_read_generic, &spr_write_generic,
6832                 0x00000000);
6833    /* PMC */
6834    /* XXX : not implemented */
6835    spr_register(env, SPR_7XX_PMC5, "PMC5",
6836                 SPR_NOACCESS, SPR_NOACCESS,
6837                 &spr_read_generic, &spr_write_generic,
6838                 0x00000000);
6839    /* XXX : not implemented */
6840    spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6841                 &spr_read_ureg, SPR_NOACCESS,
6842                 &spr_read_ureg, SPR_NOACCESS,
6843                 0x00000000);
6844    /* XXX : not implemented */
6845    spr_register(env, SPR_7XX_PMC6, "PMC6",
6846                 SPR_NOACCESS, SPR_NOACCESS,
6847                 &spr_read_generic, &spr_write_generic,
6848                 0x00000000);
6849    /* XXX : not implemented */
6850    spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6851                 &spr_read_ureg, SPR_NOACCESS,
6852                 &spr_read_ureg, SPR_NOACCESS,
6853                 0x00000000);
6854    /* Memory management */
6855    gen_low_BATs(env);
6856    gen_74xx_soft_tlb(env, 128, 2);
6857    init_excp_7450(env);
6858    env->dcache_line_size = 32;
6859    env->icache_line_size = 32;
6860    /* Allocate hardware IRQ controller */
6861    ppc6xx_irq_init(ppc_env_get_cpu(env));
6862}
6863
6864POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
6865{
6866    DeviceClass *dc = DEVICE_CLASS(oc);
6867    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6868
6869    dc->desc = "PowerPC 7450 (aka G4)";
6870    pcc->init_proc = init_proc_7450;
6871    pcc->check_pow = check_pow_hid0_74xx;
6872    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6873                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6874                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6875                       PPC_FLOAT_STFIWX |
6876                       PPC_CACHE | PPC_CACHE_ICBI |
6877                       PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6878                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
6879                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6880                       PPC_MEM_TLBIA | PPC_74xx_TLB |
6881                       PPC_SEGMENT | PPC_EXTERN |
6882                       PPC_ALTIVEC;
6883    pcc->msr_mask = (1ull << MSR_VR) |
6884                    (1ull << MSR_POW) |
6885                    (1ull << MSR_ILE) |
6886                    (1ull << MSR_EE) |
6887                    (1ull << MSR_PR) |
6888                    (1ull << MSR_FP) |
6889                    (1ull << MSR_ME) |
6890                    (1ull << MSR_FE0) |
6891                    (1ull << MSR_SE) |
6892                    (1ull << MSR_DE) |
6893                    (1ull << MSR_FE1) |
6894                    (1ull << MSR_EP) |
6895                    (1ull << MSR_IR) |
6896                    (1ull << MSR_DR) |
6897                    (1ull << MSR_PMM) |
6898                    (1ull << MSR_RI) |
6899                    (1ull << MSR_LE);
6900    pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6901    pcc->excp_model = POWERPC_EXCP_74xx;
6902    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6903    pcc->bfd_mach = bfd_mach_ppc_7400;
6904    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6905                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6906                 POWERPC_FLAG_BUS_CLK;
6907}
6908
6909static void init_proc_7445(CPUPPCState *env)
6910{
6911    gen_spr_ne_601(env);
6912    gen_spr_sdr1(env);
6913    gen_spr_7xx(env);
6914    /* Time base */
6915    gen_tbl(env);
6916    /* 74xx specific SPR */
6917    gen_spr_74xx(env);
6918    /* LDSTCR */
6919    /* XXX : not implemented */
6920    spr_register(env, SPR_LDSTCR, "LDSTCR",
6921                 SPR_NOACCESS, SPR_NOACCESS,
6922                 &spr_read_generic, &spr_write_generic,
6923                 0x00000000);
6924    /* ICTRL */
6925    /* XXX : not implemented */
6926    spr_register(env, SPR_ICTRL, "ICTRL",
6927                 SPR_NOACCESS, SPR_NOACCESS,
6928                 &spr_read_generic, &spr_write_generic,
6929                 0x00000000);
6930    /* MSSSR0 */
6931    /* XXX : not implemented */
6932    spr_register(env, SPR_MSSSR0, "MSSSR0",
6933                 SPR_NOACCESS, SPR_NOACCESS,
6934                 &spr_read_generic, &spr_write_generic,
6935                 0x00000000);
6936    /* PMC */
6937    /* XXX : not implemented */
6938    spr_register(env, SPR_7XX_PMC5, "PMC5",
6939                 SPR_NOACCESS, SPR_NOACCESS,
6940                 &spr_read_generic, &spr_write_generic,
6941                 0x00000000);
6942    /* XXX : not implemented */
6943    spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6944                 &spr_read_ureg, SPR_NOACCESS,
6945                 &spr_read_ureg, SPR_NOACCESS,
6946                 0x00000000);
6947    /* XXX : not implemented */
6948    spr_register(env, SPR_7XX_PMC6, "PMC6",
6949                 SPR_NOACCESS, SPR_NOACCESS,
6950                 &spr_read_generic, &spr_write_generic,
6951                 0x00000000);
6952    /* XXX : not implemented */
6953    spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6954                 &spr_read_ureg, SPR_NOACCESS,
6955                 &spr_read_ureg, SPR_NOACCESS,
6956                 0x00000000);
6957    /* SPRGs */
6958    spr_register(env, SPR_SPRG4, "SPRG4",
6959                 SPR_NOACCESS, SPR_NOACCESS,
6960                 &spr_read_generic, &spr_write_generic,
6961                 0x00000000);
6962    spr_register(env, SPR_USPRG4, "USPRG4",
6963                 &spr_read_ureg, SPR_NOACCESS,
6964                 &spr_read_ureg, SPR_NOACCESS,
6965                 0x00000000);
6966    spr_register(env, SPR_SPRG5, "SPRG5",
6967                 SPR_NOACCESS, SPR_NOACCESS,
6968                 &spr_read_generic, &spr_write_generic,
6969                 0x00000000);
6970    spr_register(env, SPR_USPRG5, "USPRG5",
6971                 &spr_read_ureg, SPR_NOACCESS,
6972                 &spr_read_ureg, SPR_NOACCESS,
6973                 0x00000000);
6974    spr_register(env, SPR_SPRG6, "SPRG6",
6975                 SPR_NOACCESS, SPR_NOACCESS,
6976                 &spr_read_generic, &spr_write_generic,
6977                 0x00000000);
6978    spr_register(env, SPR_USPRG6, "USPRG6",
6979                 &spr_read_ureg, SPR_NOACCESS,
6980                 &spr_read_ureg, SPR_NOACCESS,
6981                 0x00000000);
6982    spr_register(env, SPR_SPRG7, "SPRG7",
6983                 SPR_NOACCESS, SPR_NOACCESS,
6984                 &spr_read_generic, &spr_write_generic,
6985                 0x00000000);
6986    spr_register(env, SPR_USPRG7, "USPRG7",
6987                 &spr_read_ureg, SPR_NOACCESS,
6988                 &spr_read_ureg, SPR_NOACCESS,
6989                 0x00000000);
6990    /* Memory management */
6991    gen_low_BATs(env);
6992    gen_high_BATs(env);
6993    gen_74xx_soft_tlb(env, 128, 2);
6994    init_excp_7450(env);
6995    env->dcache_line_size = 32;
6996    env->icache_line_size = 32;
6997    /* Allocate hardware IRQ controller */
6998    ppc6xx_irq_init(ppc_env_get_cpu(env));
6999}
7000

7001POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
7002{
7003    DeviceClass *dc = DEVICE_CLASS(oc);
7004    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7005
7006    dc->desc = "PowerPC 7445 (aka G4)";
7007    pcc->init_proc = init_proc_7445;
7008    pcc->check_pow = check_pow_hid0_74xx;
7009    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7010                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7011                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7012                       PPC_FLOAT_STFIWX |
7013                       PPC_CACHE | PPC_CACHE_ICBI |
7014                       PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7015                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
7016                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7017                       PPC_MEM_TLBIA | PPC_74xx_TLB |
7018                       PPC_SEGMENT | PPC_EXTERN |
7019                       PPC_ALTIVEC;
7020    pcc->msr_mask = (1ull << MSR_VR) |
7021                    (1ull << MSR_POW) |
7022                    (1ull << MSR_ILE) |
7023                    (1ull << MSR_EE) |
7024                    (1ull << MSR_PR) |
7025                    (1ull << MSR_FP) |
7026                    (1ull << MSR_ME) |
7027                    (1ull << MSR_FE0) |
7028                    (1ull << MSR_SE) |
7029                    (1ull << MSR_DE) |
7030                    (1ull << MSR_FE1) |
7031                    (1ull << MSR_EP) |
7032                    (1ull << MSR_IR) |
7033                    (1ull << MSR_DR) |
7034                    (1ull << MSR_PMM) |
7035                    (1ull << MSR_RI) |
7036                    (1ull << MSR_LE);
7037    pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
7038    pcc->excp_model = POWERPC_EXCP_74xx;
7039    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7040    pcc->bfd_mach = bfd_mach_ppc_7400;
7041    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7042                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7043                 POWERPC_FLAG_BUS_CLK;
7044}
7045
7046static void init_proc_7455(CPUPPCState *env)
7047{
7048    gen_spr_ne_601(env);
7049    gen_spr_sdr1(env);
7050    gen_spr_7xx(env);
7051    /* Time base */
7052    gen_tbl(env);
7053    /* 74xx specific SPR */
7054    gen_spr_74xx(env);
7055    /* Level 3 cache control */
7056    gen_l3_ctrl(env);
7057    /* LDSTCR */
7058    /* XXX : not implemented */
7059    spr_register(env, SPR_LDSTCR, "LDSTCR",
7060                 SPR_NOACCESS, SPR_NOACCESS,
7061                 &spr_read_generic, &spr_write_generic,
7062                 0x00000000);
7063    /* ICTRL */
7064    /* XXX : not implemented */
7065    spr_register(env, SPR_ICTRL, "ICTRL",
7066                 SPR_NOACCESS, SPR_NOACCESS,
7067                 &spr_read_generic, &spr_write_generic,
7068                 0x00000000);
7069    /* MSSSR0 */
7070    /* XXX : not implemented */
7071    spr_register(env, SPR_MSSSR0, "MSSSR0",
7072                 SPR_NOACCESS, SPR_NOACCESS,
7073                 &spr_read_generic, &spr_write_generic,
7074                 0x00000000);
7075    /* PMC */
7076    /* XXX : not implemented */
7077    spr_register(env, SPR_7XX_PMC5, "PMC5",
7078                 SPR_NOACCESS, SPR_NOACCESS,
7079                 &spr_read_generic, &spr_write_generic,
7080                 0x00000000);
7081    /* XXX : not implemented */
7082    spr_register(env, SPR_7XX_UPMC5, "UPMC5",
7083                 &spr_read_ureg, SPR_NOACCESS,
7084                 &spr_read_ureg, SPR_NOACCESS,
7085                 0x00000000);
7086    /* XXX : not implemented */
7087    spr_register(env, SPR_7XX_PMC6, "PMC6",
7088                 SPR_NOACCESS, SPR_NOACCESS,
7089                 &spr_read_generic, &spr_write_generic,
7090                 0x00000000);
7091    /* XXX : not implemented */
7092    spr_register(env, SPR_7XX_UPMC6, "UPMC6",
7093                 &spr_read_ureg, SPR_NOACCESS,
7094                 &spr_read_ureg, SPR_NOACCESS,
7095                 0x00000000);
7096    /* SPRGs */
7097    spr_register(env, SPR_SPRG4, "SPRG4",
7098                 SPR_NOACCESS, SPR_NOACCESS,
7099                 &spr_read_generic, &spr_write_generic,
7100                 0x00000000);
7101    spr_register(env, SPR_USPRG4, "USPRG4",
7102                 &spr_read_ureg, SPR_NOACCESS,
7103                 &spr_read_ureg, SPR_NOACCESS,
7104                 0x00000000);
7105    spr_register(env, SPR_SPRG5, "SPRG5",
7106                 SPR_NOACCESS, SPR_NOACCESS,
7107                 &spr_read_generic, &spr_write_generic,
7108                 0x00000000);
7109    spr_register(env, SPR_USPRG5, "USPRG5",
7110                 &spr_read_ureg, SPR_NOACCESS,
7111                 &spr_read_ureg, SPR_NOACCESS,
7112                 0x00000000);
7113    spr_register(env, SPR_SPRG6, "SPRG6",
7114                 SPR_NOACCESS, SPR_NOACCESS,
7115                 &spr_read_generic, &spr_write_generic,
7116                 0x00000000);
7117    spr_register(env, SPR_USPRG6, "USPRG6",
7118                 &spr_read_ureg, SPR_NOACCESS,
7119                 &spr_read_ureg, SPR_NOACCESS,
7120                 0x00000000);
7121    spr_register(env, SPR_SPRG7, "SPRG7",
7122                 SPR_NOACCESS, SPR_NOACCESS,
7123                 &spr_read_generic, &spr_write_generic,
7124                 0x00000000);
7125    spr_register(env, SPR_USPRG7, "USPRG7",
7126                 &spr_read_ureg, SPR_NOACCESS,
7127                 &spr_read_ureg, SPR_NOACCESS,
7128                 0x00000000);
7129    /* Memory management */
7130    gen_low_BATs(env);
7131    gen_high_BATs(env);
7132    gen_74xx_soft_tlb(env, 128, 2);
7133    init_excp_7450(env);
7134    env->dcache_line_size = 32;
7135    env->icache_line_size = 32;
7136    /* Allocate hardware IRQ controller */
7137    ppc6xx_irq_init(ppc_env_get_cpu(env));
7138}
7139
7140POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
7141{
7142    DeviceClass *dc = DEVICE_CLASS(oc);
7143    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7144
7145    dc->desc = "PowerPC 7455 (aka G4)";
7146    pcc->init_proc = init_proc_7455;
7147    pcc->check_pow = check_pow_hid0_74xx;
7148    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7149                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7150                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7151                       PPC_FLOAT_STFIWX |
7152                       PPC_CACHE | PPC_CACHE_ICBI |
7153                       PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7154                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
7155                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7156                       PPC_MEM_TLBIA | PPC_74xx_TLB |
7157                       PPC_SEGMENT | PPC_EXTERN |
7158                       PPC_ALTIVEC;
7159    pcc->msr_mask = (1ull << MSR_VR) |
7160                    (1ull << MSR_POW) |
7161                    (1ull << MSR_ILE) |
7162                    (1ull << MSR_EE) |
7163                    (1ull << MSR_PR) |
7164                    (1ull << MSR_FP) |
7165                    (1ull << MSR_ME) |
7166                    (1ull << MSR_FE0) |
7167                    (1ull << MSR_SE) |
7168                    (1ull << MSR_DE) |
7169                    (1ull << MSR_FE1) |
7170                    (1ull << MSR_EP) |
7171                    (1ull << MSR_IR) |
7172                    (1ull << MSR_DR) |
7173                    (1ull << MSR_PMM) |
7174                    (1ull << MSR_RI) |
7175                    (1ull << MSR_LE);
7176    pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
7177    pcc->excp_model = POWERPC_EXCP_74xx;
7178    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7179    pcc->bfd_mach = bfd_mach_ppc_7400;
7180    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7181                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7182                 POWERPC_FLAG_BUS_CLK;
7183}
7184
7185static void init_proc_7457(CPUPPCState *env)
7186{
7187    gen_spr_ne_601(env);
7188    gen_spr_sdr1(env);
7189    gen_spr_7xx(env);
7190    /* Time base */
7191    gen_tbl(env);
7192    /* 74xx specific SPR */
7193    gen_spr_74xx(env);
7194    /* Level 3 cache control */
7195    gen_l3_ctrl(env);
7196    /* L3ITCR1 */
7197    /* XXX : not implemented */
7198    spr_register(env, SPR_L3ITCR1, "L3ITCR1",
7199                 SPR_NOACCESS, SPR_NOACCESS,
7200                 &spr_read_generic, &spr_write_generic,
7201                 0x00000000);
7202    /* L3ITCR2 */
7203    /* XXX : not implemented */
7204    spr_register(env, SPR_L3ITCR2, "L3ITCR2",
7205                 SPR_NOACCESS, SPR_NOACCESS,
7206                 &spr_read_generic, &spr_write_generic,
7207                 0x00000000);
7208    /* L3ITCR3 */
7209    /* XXX : not implemented */
7210    spr_register(env, SPR_L3ITCR3, "L3ITCR3",
7211                 SPR_NOACCESS, SPR_NOACCESS,
7212                 &spr_read_generic, &spr_write_generic,
7213                 0x00000000);
7214    /* L3OHCR */
7215    /* XXX : not implemented */
7216    spr_register(env, SPR_L3OHCR, "L3OHCR",
7217                 SPR_NOACCESS, SPR_NOACCESS,
7218                 &spr_read_generic, &spr_write_generic,
7219                 0x00000000);
7220    /* LDSTCR */
7221    /* XXX : not implemented */
7222    spr_register(env, SPR_LDSTCR, "LDSTCR",
7223                 SPR_NOACCESS, SPR_NOACCESS,
7224                 &spr_read_generic, &spr_write_generic,
7225                 0x00000000);
7226    /* ICTRL */
7227    /* XXX : not implemented */
7228    spr_register(env, SPR_ICTRL, "ICTRL",
7229                 SPR_NOACCESS, SPR_NOACCESS,
7230                 &spr_read_generic, &spr_write_generic,
7231                 0x00000000);
7232    /* MSSSR0 */
7233    /* XXX : not implemented */
7234    spr_register(env, SPR_MSSSR0, "MSSSR0",
7235                 SPR_NOACCESS, SPR_NOACCESS,
7236                 &spr_read_generic, &spr_write_generic,
7237                 0x00000000);
7238    /* PMC */
7239    /* XXX : not implemented */
7240    spr_register(env, SPR_7XX_PMC5, "PMC5",
7241                 SPR_NOACCESS, SPR_NOACCESS,
7242                 &spr_read_generic, &spr_write_generic,
7243                 0x00000000);
7244    /* XXX : not implemented */
7245    spr_register(env, SPR_7XX_UPMC5, "UPMC5",
7246                 &spr_read_ureg, SPR_NOACCESS,
7247                 &spr_read_ureg, SPR_NOACCESS,
7248                 0x00000000);
7249    /* XXX : not implemented */
7250    spr_register(env, SPR_7XX_PMC6, "PMC6",
7251                 SPR_NOACCESS, SPR_NOACCESS,
7252                 &spr_read_generic, &spr_write_generic,
7253                 0x00000000);
7254    /* XXX : not implemented */
7255    spr_register(env, SPR_7XX_UPMC6, "UPMC6",
7256                 &spr_read_ureg, SPR_NOACCESS,
7257                 &spr_read_ureg, SPR_NOACCESS,
7258                 0x00000000);
7259    /* SPRGs */
7260    spr_register(env, SPR_SPRG4, "SPRG4",
7261                 SPR_NOACCESS, SPR_NOACCESS,
7262                 &spr_read_generic, &spr_write_generic,
7263                 0x00000000);
7264    spr_register(env, SPR_USPRG4, "USPRG4",
7265                 &spr_read_ureg, SPR_NOACCESS,
7266                 &spr_read_ureg, SPR_NOACCESS,
7267                 0x00000000);
7268    spr_register(env, SPR_SPRG5, "SPRG5",
7269                 SPR_NOACCESS, SPR_NOACCESS,
7270                 &spr_read_generic, &spr_write_generic,
7271                 0x00000000);
7272    spr_register(env, SPR_USPRG5, "USPRG5",
7273                 &spr_read_ureg, SPR_NOACCESS,
7274                 &spr_read_ureg, SPR_NOACCESS,
7275                 0x00000000);
7276    spr_register(env, SPR_SPRG6, "SPRG6",
7277                 SPR_NOACCESS, SPR_NOACCESS,
7278                 &spr_read_generic, &spr_write_generic,
7279                 0x00000000);
7280    spr_register(env, SPR_USPRG6, "USPRG6",
7281                 &spr_read_ureg, SPR_NOACCESS,
7282                 &spr_read_ureg, SPR_NOACCESS,
7283                 0x00000000);
7284    spr_register(env, SPR_SPRG7, "SPRG7",
7285                 SPR_NOACCESS, SPR_NOACCESS,
7286                 &spr_read_generic, &spr_write_generic,
7287                 0x00000000);
7288    spr_register(env, SPR_USPRG7, "USPRG7",
7289                 &spr_read_ureg, SPR_NOACCESS,
7290                 &spr_read_ureg, SPR_NOACCESS,
7291                 0x00000000);
7292    /* Memory management */
7293    gen_low_BATs(env);
7294    gen_high_BATs(env);
7295    gen_74xx_soft_tlb(env, 128, 2);
7296    init_excp_7450(env);
7297    env->dcache_line_size = 32;
7298    env->icache_line_size = 32;
7299    /* Allocate hardware IRQ controller */
7300    ppc6xx_irq_init(ppc_env_get_cpu(env));
7301}
7302
7303POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
7304{
7305    DeviceClass *dc = DEVICE_CLASS(oc);
7306    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7307
7308    dc->desc = "PowerPC 7457 (aka G4)";
7309    pcc->init_proc = init_proc_7457;
7310    pcc->check_pow = check_pow_hid0_74xx;
7311    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7312                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7313                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7314                       PPC_FLOAT_STFIWX |
7315                       PPC_CACHE | PPC_CACHE_ICBI |
7316                       PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7317                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
7318                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7319                       PPC_MEM_TLBIA | PPC_74xx_TLB |
7320                       PPC_SEGMENT | PPC_EXTERN |
7321                       PPC_ALTIVEC;
7322    pcc->msr_mask = (1ull << MSR_VR) |
7323                    (1ull << MSR_POW) |
7324                    (1ull << MSR_ILE) |
7325                    (1ull << MSR_EE) |
7326                    (1ull << MSR_PR) |
7327                    (1ull << MSR_FP) |
7328                    (1ull << MSR_ME) |
7329                    (1ull << MSR_FE0) |
7330                    (1ull << MSR_SE) |
7331                    (1ull << MSR_DE) |
7332                    (1ull << MSR_FE1) |
7333                    (1ull << MSR_EP) |
7334                    (1ull << MSR_IR) |
7335                    (1ull << MSR_DR) |
7336                    (1ull << MSR_PMM) |
7337                    (1ull << MSR_RI) |
7338                    (1ull << MSR_LE);
7339    pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
7340    pcc->excp_model = POWERPC_EXCP_74xx;
7341    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7342    pcc->bfd_mach = bfd_mach_ppc_7400;
7343    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7344                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7345                 POWERPC_FLAG_BUS_CLK;
7346}
7347
7348static void init_proc_e600(CPUPPCState *env)
7349{
7350    gen_spr_ne_601(env);
7351    gen_spr_sdr1(env);
7352    gen_spr_7xx(env);
7353    /* Time base */
7354    gen_tbl(env);
7355    /* 74xx specific SPR */
7356    gen_spr_74xx(env);
7357    /* XXX : not implemented */
7358    spr_register(env, SPR_UBAMR, "UBAMR",
7359                 &spr_read_ureg, SPR_NOACCESS,
7360                 &spr_read_ureg, SPR_NOACCESS,
7361                 0x00000000);
7362    /* XXX : not implemented */
7363    spr_register(env, SPR_LDSTCR, "LDSTCR",
7364                 SPR_NOACCESS, SPR_NOACCESS,
7365                 &spr_read_generic, &spr_write_generic,
7366                 0x00000000);
7367    /* XXX : not implemented */
7368    spr_register(env, SPR_ICTRL, "ICTRL",
7369                 SPR_NOACCESS, SPR_NOACCESS,
7370                 &spr_read_generic, &spr_write_generic,
7371                 0x00000000);
7372    /* XXX : not implemented */
7373    spr_register(env, SPR_MSSSR0, "MSSSR0",
7374                 SPR_NOACCESS, SPR_NOACCESS,
7375                 &spr_read_generic, &spr_write_generic,
7376                 0x00000000);
7377    /* XXX : not implemented */
7378    spr_register(env, SPR_7XX_PMC5, "PMC5",
7379                 SPR_NOACCESS, SPR_NOACCESS,
7380                 &spr_read_generic, &spr_write_generic,
7381                 0x00000000);
7382    /* XXX : not implemented */
7383    spr_register(env, SPR_7XX_UPMC5, "UPMC5",
7384                 &spr_read_ureg, SPR_NOACCESS,
7385                 &spr_read_ureg, SPR_NOACCESS,
7386                 0x00000000);
7387    /* XXX : not implemented */
7388    spr_register(env, SPR_7XX_PMC6, "PMC6",
7389                 SPR_NOACCESS, SPR_NOACCESS,
7390                 &spr_read_generic, &spr_write_generic,
7391                 0x00000000);
7392    /* XXX : not implemented */
7393    spr_register(env, SPR_7XX_UPMC6, "UPMC6",
7394                 &spr_read_ureg, SPR_NOACCESS,
7395                 &spr_read_ureg, SPR_NOACCESS,
7396                 0x00000000);
7397    /* SPRGs */
7398    spr_register(env, SPR_SPRG4, "SPRG4",
7399                 SPR_NOACCESS, SPR_NOACCESS,
7400                 &spr_read_generic, &spr_write_generic,
7401                 0x00000000);
7402    spr_register(env, SPR_USPRG4, "USPRG4",
7403                 &spr_read_ureg, SPR_NOACCESS,
7404                 &spr_read_ureg, SPR_NOACCESS,
7405                 0x00000000);
7406    spr_register(env, SPR_SPRG5, "SPRG5",
7407                 SPR_NOACCESS, SPR_NOACCESS,
7408                 &spr_read_generic, &spr_write_generic,
7409                 0x00000000);
7410    spr_register(env, SPR_USPRG5, "USPRG5",
7411                 &spr_read_ureg, SPR_NOACCESS,
7412                 &spr_read_ureg, SPR_NOACCESS,
7413                 0x00000000);
7414    spr_register(env, SPR_SPRG6, "SPRG6",
7415                 SPR_NOACCESS, SPR_NOACCESS,
7416                 &spr_read_generic, &spr_write_generic,
7417                 0x00000000);
7418    spr_register(env, SPR_USPRG6, "USPRG6",
7419                 &spr_read_ureg, SPR_NOACCESS,
7420                 &spr_read_ureg, SPR_NOACCESS,
7421                 0x00000000);
7422    spr_register(env, SPR_SPRG7, "SPRG7",
7423                 SPR_NOACCESS, SPR_NOACCESS,
7424                 &spr_read_generic, &spr_write_generic,
7425                 0x00000000);
7426    spr_register(env, SPR_USPRG7, "USPRG7",
7427                 &spr_read_ureg, SPR_NOACCESS,
7428                 &spr_read_ureg, SPR_NOACCESS,
7429                 0x00000000);
7430    /* Memory management */
7431    gen_low_BATs(env);
7432    gen_high_BATs(env);
7433    gen_74xx_soft_tlb(env, 128, 2);
7434    init_excp_7450(env);
7435    env->dcache_line_size = 32;
7436    env->icache_line_size = 32;
7437    /* Allocate hardware IRQ controller */
7438    ppc6xx_irq_init(ppc_env_get_cpu(env));
7439}
7440
7441POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
7442{
7443    DeviceClass *dc = DEVICE_CLASS(oc);
7444    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7445
7446    dc->desc = "PowerPC e600";
7447    pcc->init_proc = init_proc_e600;
7448    pcc->check_pow = check_pow_hid0_74xx;
7449    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7450                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7451                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7452                       PPC_FLOAT_STFIWX |
7453                       PPC_CACHE | PPC_CACHE_ICBI |
7454                       PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7455                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
7456                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7457                       PPC_MEM_TLBIA | PPC_74xx_TLB |
7458                       PPC_SEGMENT | PPC_EXTERN |
7459                       PPC_ALTIVEC;
7460    pcc->insns_flags2 = PPC_NONE;
7461    pcc->msr_mask = (1ull << MSR_VR) |
7462                    (1ull << MSR_POW) |
7463                    (1ull << MSR_ILE) |
7464                    (1ull << MSR_EE) |
7465                    (1ull << MSR_PR) |
7466                    (1ull << MSR_FP) |
7467                    (1ull << MSR_ME) |
7468                    (1ull << MSR_FE0) |
7469                    (1ull << MSR_SE) |
7470                    (1ull << MSR_DE) |
7471                    (1ull << MSR_FE1) |
7472                    (1ull << MSR_EP) |
7473                    (1ull << MSR_IR) |
7474                    (1ull << MSR_DR) |
7475                    (1ull << MSR_PMM) |
7476                    (1ull << MSR_RI) |
7477                    (1ull << MSR_LE);
7478    pcc->mmu_model = POWERPC_MMU_32B;
7479#if defined(CONFIG_SOFTMMU)
7480    pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
7481#endif
7482    pcc->excp_model = POWERPC_EXCP_74xx;
7483    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7484    pcc->bfd_mach = bfd_mach_ppc_7400;
7485    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7486                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7487                 POWERPC_FLAG_BUS_CLK;
7488}
7489
7490#if defined(TARGET_PPC64)
7491#if defined(CONFIG_USER_ONLY)
7492#define POWERPC970_HID5_INIT 0x00000080
7493#else
7494#define POWERPC970_HID5_INIT 0x00000000
7495#endif
7496
7497static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
7498                                    int bit, int sprn, int cause)
7499{
7500    TCGv_i32 t1 = tcg_const_i32(bit);
7501    TCGv_i32 t2 = tcg_const_i32(sprn);
7502    TCGv_i32 t3 = tcg_const_i32(cause);
7503
7504    gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
7505
7506    tcg_temp_free_i32(t3);
7507    tcg_temp_free_i32(t2);
7508    tcg_temp_free_i32(t1);
7509}
7510
7511static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
7512                                   int bit, int sprn, int cause)
7513{
7514    TCGv_i32 t1 = tcg_const_i32(bit);
7515    TCGv_i32 t2 = tcg_const_i32(sprn);
7516    TCGv_i32 t3 = tcg_const_i32(cause);
7517
7518    gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
7519
7520    tcg_temp_free_i32(t3);
7521    tcg_temp_free_i32(t2);
7522    tcg_temp_free_i32(t1);
7523}
7524
7525static void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
7526{
7527    TCGv spr_up = tcg_temp_new();
7528    TCGv spr = tcg_temp_new();
7529
7530    gen_load_spr(spr, sprn - 1);
7531    tcg_gen_shri_tl(spr_up, spr, 32);
7532    tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up);
7533
7534    tcg_temp_free(spr);
7535    tcg_temp_free(spr_up);
7536}
7537
7538static void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
7539{
7540    TCGv spr = tcg_temp_new();
7541
7542    gen_load_spr(spr, sprn - 1);
7543    tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32);
7544    gen_store_spr(sprn - 1, spr);
7545
7546    tcg_temp_free(spr);
7547}
7548
7549static int check_pow_970(CPUPPCState *env)
7550{
7551    if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
7552        return 1;
7553    }
7554
7555    return 0;
7556}
7557
7558static void gen_spr_970_hid(CPUPPCState *env)
7559{
7560    /* Hardware implementation registers */
7561    /* XXX : not implemented */
7562    spr_register(env, SPR_HID0, "HID0",
7563                 SPR_NOACCESS, SPR_NOACCESS,
7564                 &spr_read_generic, &spr_write_clear,
7565                 0x60000000);
7566    spr_register(env, SPR_HID1, "HID1",
7567                 SPR_NOACCESS, SPR_NOACCESS,
7568                 &spr_read_generic, &spr_write_generic,
7569                 0x00000000);
7570    spr_register(env, SPR_970_HID5, "HID5",
7571                 SPR_NOACCESS, SPR_NOACCESS,
7572                 &spr_read_generic, &spr_write_generic,
7573                 POWERPC970_HID5_INIT);
7574}
7575
7576static void gen_spr_970_hior(CPUPPCState *env)
7577{
7578    spr_register(env, SPR_HIOR, "SPR_HIOR",
7579                 SPR_NOACCESS, SPR_NOACCESS,
7580                 &spr_read_hior, &spr_write_hior,
7581                 0x00000000);
7582}
7583
7584static void gen_spr_book3s_ctrl(CPUPPCState *env)
7585{
7586    spr_register(env, SPR_CTRL, "SPR_CTRL",
7587                 SPR_NOACCESS, SPR_NOACCESS,
7588                 SPR_NOACCESS, &spr_write_generic,
7589                 0x00000000);
7590    spr_register(env, SPR_UCTRL, "SPR_UCTRL",
7591                 &spr_read_ureg, SPR_NOACCESS,
7592                 &spr_read_ureg, SPR_NOACCESS,
7593                 0x00000000);
7594}
7595
7596static void gen_spr_book3s_altivec(CPUPPCState *env)
7597{
7598    if (!(env->insns_flags & PPC_ALTIVEC)) {
7599        return;
7600    }
7601
7602    spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
7603                     &spr_read_generic, &spr_write_generic,
7604                     &spr_read_generic, &spr_write_generic,
7605                     KVM_REG_PPC_VRSAVE, 0x00000000);
7606
7607    /* Can't find information on what this should be on reset.  This
7608     * value is the one used by 74xx processors. */
7609    vscr_init(env, 0x00010000);
7610}
7611
7612static void gen_spr_book3s_dbg(CPUPPCState *env)
7613{
7614    /*
7615     * TODO: different specs define different scopes for these,
7616     * will have to address this:
7617     * 970: super/write and super/read
7618     * powerisa 2.03..2.04: hypv/write and super/read.
7619     * powerisa 2.05 and newer: hypv/write and hypv/read.
7620     */
7621    spr_register_kvm(env, SPR_DABR, "DABR",
7622                     SPR_NOACCESS, SPR_NOACCESS,
7623                     &spr_read_generic, &spr_write_generic,
7624                     KVM_REG_PPC_DABR, 0x00000000);
7625    spr_register_kvm(env, SPR_DABRX, "DABRX",
7626                     SPR_NOACCESS, SPR_NOACCESS,
7627                     &spr_read_generic, &spr_write_generic,
7628                     KVM_REG_PPC_DABRX, 0x00000000);
7629}
7630
7631static void gen_spr_book3s_207_dbg(CPUPPCState *env)
7632{
7633    spr_register_kvm_hv(env, SPR_DAWR, "DAWR",
7634                        SPR_NOACCESS, SPR_NOACCESS,
7635                        SPR_NOACCESS, SPR_NOACCESS,
7636                        &spr_read_generic, &spr_write_generic,
7637                        KVM_REG_PPC_DAWR, 0x00000000);
7638    spr_register_kvm_hv(env, SPR_DAWRX, "DAWRX",
7639                        SPR_NOACCESS, SPR_NOACCESS,
7640                        SPR_NOACCESS, SPR_NOACCESS,
7641                        &spr_read_generic, &spr_write_generic,
7642                        KVM_REG_PPC_DAWRX, 0x00000000);
7643    spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
7644                        SPR_NOACCESS, SPR_NOACCESS,
7645                        SPR_NOACCESS, SPR_NOACCESS,
7646                        &spr_read_generic, &spr_write_generic,
7647                        KVM_REG_PPC_CIABR, 0x00000000);
7648}
7649
7650static void gen_spr_970_dbg(CPUPPCState *env)
7651{
7652    /* Breakpoints */
7653    spr_register(env, SPR_IABR, "IABR",
7654                 SPR_NOACCESS, SPR_NOACCESS,
7655                 &spr_read_generic, &spr_write_generic,
7656                 0x00000000);
7657}
7658
7659static void gen_spr_book3s_pmu_sup(CPUPPCState *env)
7660{
7661    spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
7662                     SPR_NOACCESS, SPR_NOACCESS,
7663                     &spr_read_generic, &spr_write_generic,
7664                     KVM_REG_PPC_MMCR0, 0x00000000);
7665    spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
7666                     SPR_NOACCESS, SPR_NOACCESS,
7667                     &spr_read_generic, &spr_write_generic,
7668                     KVM_REG_PPC_MMCR1, 0x00000000);
7669    spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
7670                     SPR_NOACCESS, SPR_NOACCESS,
7671                     &spr_read_generic, &spr_write_generic,
7672                     KVM_REG_PPC_MMCRA, 0x00000000);
7673    spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
7674                     SPR_NOACCESS, SPR_NOACCESS,
7675                     &spr_read_generic, &spr_write_generic,
7676                     KVM_REG_PPC_PMC1, 0x00000000);
7677    spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
7678                     SPR_NOACCESS, SPR_NOACCESS,
7679                     &spr_read_generic, &spr_write_generic,
7680                     KVM_REG_PPC_PMC2, 0x00000000);
7681    spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
7682                     SPR_NOACCESS, SPR_NOACCESS,
7683                     &spr_read_generic, &spr_write_generic,
7684                     KVM_REG_PPC_PMC3, 0x00000000);
7685    spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
7686                     SPR_NOACCESS, SPR_NOACCESS,
7687                     &spr_read_generic, &spr_write_generic,
7688                     KVM_REG_PPC_PMC4, 0x00000000);
7689    spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
7690                     SPR_NOACCESS, SPR_NOACCESS,
7691                     &spr_read_generic, &spr_write_generic,
7692                     KVM_REG_PPC_PMC5, 0x00000000);
7693    spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
7694                     SPR_NOACCESS, SPR_NOACCESS,
7695                     &spr_read_generic, &spr_write_generic,
7696                     KVM_REG_PPC_PMC6, 0x00000000);
7697    spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
7698                     SPR_NOACCESS, SPR_NOACCESS,
7699                     &spr_read_generic, &spr_write_generic,
7700                     KVM_REG_PPC_SIAR, 0x00000000);
7701    spr_register_kvm(env, SPR_POWER_SDAR, "SDAR",
7702                     SPR_NOACCESS, SPR_NOACCESS,
7703                     &spr_read_generic, &spr_write_generic,
7704                     KVM_REG_PPC_SDAR, 0x00000000);
7705}
7706
7707static void gen_spr_book3s_pmu_user(CPUPPCState *env)
7708{
7709    spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
7710                 &spr_read_ureg, SPR_NOACCESS,
7711                 &spr_read_ureg, &spr_write_ureg,
7712                 0x00000000);
7713    spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
7714                 &spr_read_ureg, SPR_NOACCESS,
7715                 &spr_read_ureg, &spr_write_ureg,
7716                 0x00000000);
7717    spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
7718                 &spr_read_ureg, SPR_NOACCESS,
7719                 &spr_read_ureg, &spr_write_ureg,
7720                 0x00000000);
7721    spr_register(env, SPR_POWER_UPMC1, "UPMC1",
7722                 &spr_read_ureg, SPR_NOACCESS,
7723                 &spr_read_ureg, &spr_write_ureg,
7724                 0x00000000);
7725    spr_register(env, SPR_POWER_UPMC2, "UPMC2",
7726                 &spr_read_ureg, SPR_NOACCESS,
7727                 &spr_read_ureg, &spr_write_ureg,
7728                 0x00000000);
7729    spr_register(env, SPR_POWER_UPMC3, "UPMC3",
7730                 &spr_read_ureg, SPR_NOACCESS,
7731                 &spr_read_ureg, &spr_write_ureg,
7732                 0x00000000);
7733    spr_register(env, SPR_POWER_UPMC4, "UPMC4",
7734                 &spr_read_ureg, SPR_NOACCESS,
7735                 &spr_read_ureg, &spr_write_ureg,
7736                 0x00000000);
7737    spr_register(env, SPR_POWER_UPMC5, "UPMC5",
7738                 &spr_read_ureg, SPR_NOACCESS,
7739                 &spr_read_ureg, &spr_write_ureg,
7740                 0x00000000);
7741    spr_register(env, SPR_POWER_UPMC6, "UPMC6",
7742                 &spr_read_ureg, SPR_NOACCESS,
7743                 &spr_read_ureg, &spr_write_ureg,
7744                 0x00000000);
7745    spr_register(env, SPR_POWER_USIAR, "USIAR",
7746                 &spr_read_ureg, SPR_NOACCESS,
7747                 &spr_read_ureg, &spr_write_ureg,
7748                 0x00000000);
7749    spr_register(env, SPR_POWER_USDAR, "USDAR",
7750                 &spr_read_ureg, SPR_NOACCESS,
7751                 &spr_read_ureg, &spr_write_ureg,
7752                 0x00000000);
7753}
7754
7755static void gen_spr_970_pmu_sup(CPUPPCState *env)
7756{
7757    spr_register_kvm(env, SPR_970_PMC7, "PMC7",
7758                     SPR_NOACCESS, SPR_NOACCESS,
7759                     &spr_read_generic, &spr_write_generic,
7760                     KVM_REG_PPC_PMC7, 0x00000000);
7761    spr_register_kvm(env, SPR_970_PMC8, "PMC8",
7762                     SPR_NOACCESS, SPR_NOACCESS,
7763                     &spr_read_generic, &spr_write_generic,
7764                     KVM_REG_PPC_PMC8, 0x00000000);
7765}
7766
7767static void gen_spr_970_pmu_user(CPUPPCState *env)
7768{
7769    spr_register(env, SPR_970_UPMC7, "UPMC7",
7770                 &spr_read_ureg, SPR_NOACCESS,
7771                 &spr_read_ureg, &spr_write_ureg,
7772                 0x00000000);
7773    spr_register(env, SPR_970_UPMC8, "UPMC8",
7774                 &spr_read_ureg, SPR_NOACCESS,
7775                 &spr_read_ureg, &spr_write_ureg,
7776                 0x00000000);
7777}
7778
7779static void gen_spr_power8_pmu_sup(CPUPPCState *env)
7780{
7781    spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
7782                     SPR_NOACCESS, SPR_NOACCESS,
7783                     &spr_read_generic, &spr_write_generic,
7784                     KVM_REG_PPC_MMCR2, 0x00000000);
7785    spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
7786                     SPR_NOACCESS, SPR_NOACCESS,
7787                     &spr_read_generic, &spr_write_generic,
7788                     KVM_REG_PPC_MMCRS, 0x00000000);
7789    spr_register_kvm(env, SPR_POWER_SIER, "SIER",
7790                     SPR_NOACCESS, SPR_NOACCESS,
7791                     &spr_read_generic, &spr_write_generic,
7792                     KVM_REG_PPC_SIER, 0x00000000);
7793    spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1",
7794                     SPR_NOACCESS, SPR_NOACCESS,
7795                     &spr_read_generic, &spr_write_generic,
7796                     KVM_REG_PPC_SPMC1, 0x00000000);
7797    spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2",
7798                     SPR_NOACCESS, SPR_NOACCESS,
7799                     &spr_read_generic, &spr_write_generic,
7800                     KVM_REG_PPC_SPMC2, 0x00000000);
7801    spr_register_kvm(env, SPR_TACR, "TACR",
7802                     SPR_NOACCESS, SPR_NOACCESS,
7803                     &spr_read_generic, &spr_write_generic,
7804                     KVM_REG_PPC_TACR, 0x00000000);
7805    spr_register_kvm(env, SPR_TCSCR, "TCSCR",
7806                     SPR_NOACCESS, SPR_NOACCESS,
7807                     &spr_read_generic, &spr_write_generic,
7808                     KVM_REG_PPC_TCSCR, 0x00000000);
7809    spr_register_kvm(env, SPR_CSIGR, "CSIGR",
7810                     SPR_NOACCESS, SPR_NOACCESS,
7811                     &spr_read_generic, &spr_write_generic,
7812                     KVM_REG_PPC_CSIGR, 0x00000000);
7813}
7814
7815static void gen_spr_power8_pmu_user(CPUPPCState *env)
7816{
7817    spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
7818                 &spr_read_ureg, SPR_NOACCESS,
7819                 &spr_read_ureg, &spr_write_ureg,
7820                 0x00000000);
7821    spr_register(env, SPR_POWER_USIER, "USIER",
7822                 &spr_read_generic, SPR_NOACCESS,
7823                 &spr_read_generic, &spr_write_generic,
7824                 0x00000000);
7825}
7826
7827static void gen_spr_power5p_ear(CPUPPCState *env)
7828{
7829    /* External access control */
7830    spr_register(env, SPR_EAR, "EAR",
7831                 SPR_NOACCESS, SPR_NOACCESS,
7832                 &spr_read_generic, &spr_write_generic,
7833                 0x00000000);
7834}
7835
7836#if !defined(CONFIG_USER_ONLY)
7837static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn)
7838{
7839    TCGv hmer = tcg_temp_new();
7840
7841    gen_load_spr(hmer, sprn);
7842    tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer);
7843    gen_store_spr(sprn, hmer);
7844    spr_store_dump_spr(sprn);
7845    tcg_temp_free(hmer);
7846}
7847
7848static void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn)
7849{
7850    gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
7851}
7852
7853static void spr_write_970_hid4(DisasContext *ctx, int sprn, int gprn)
7854{
7855#if defined(TARGET_PPC64)
7856    spr_write_generic(ctx, sprn, gprn);
7857    gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
7858#endif
7859}
7860
7861#endif /* !defined(CONFIG_USER_ONLY) */
7862
7863static void gen_spr_970_lpar(CPUPPCState *env)
7864{
7865#if !defined(CONFIG_USER_ONLY)
7866    /* Logical partitionning */
7867    /* PPC970: HID4 is effectively the LPCR */
7868    spr_register(env, SPR_970_HID4, "HID4",
7869                 SPR_NOACCESS, SPR_NOACCESS,
7870                 &spr_read_generic, &spr_write_970_hid4,
7871                 0x00000000);
7872#endif
7873}
7874
7875static void gen_spr_power5p_lpar(CPUPPCState *env)
7876{
7877#if !defined(CONFIG_USER_ONLY)
7878    /* Logical partitionning */
7879    spr_register_kvm_hv(env, SPR_LPCR, "LPCR",
7880                        SPR_NOACCESS, SPR_NOACCESS,
7881                        SPR_NOACCESS, SPR_NOACCESS,
7882                        &spr_read_generic, &spr_write_lpcr,
7883                        KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
7884    spr_register_hv(env, SPR_HDEC, "HDEC",
7885                    SPR_NOACCESS, SPR_NOACCESS,
7886                    SPR_NOACCESS, SPR_NOACCESS,
7887                    &spr_read_hdecr, &spr_write_hdecr, 0);
7888#endif
7889}
7890
7891static void gen_spr_book3s_ids(CPUPPCState *env)
7892{
7893    /* FIXME: Will need to deal with thread vs core only SPRs */
7894
7895    /* Processor identification */
7896    spr_register_hv(env, SPR_PIR, "PIR",
7897                 SPR_NOACCESS, SPR_NOACCESS,
7898                 SPR_NOACCESS, SPR_NOACCESS,
7899                 &spr_read_generic, NULL,
7900                 0x00000000);
7901    spr_register_hv(env, SPR_HID0, "HID0",
7902                 SPR_NOACCESS, SPR_NOACCESS,
7903                 SPR_NOACCESS, SPR_NOACCESS,
7904                 &spr_read_generic, &spr_write_generic,
7905                 0x00000000);
7906    spr_register_hv(env, SPR_TSCR, "TSCR",
7907                 SPR_NOACCESS, SPR_NOACCESS,
7908                 SPR_NOACCESS, SPR_NOACCESS,
7909                 &spr_read_generic, &spr_write_generic,
7910                 0x00000000);
7911    spr_register_hv(env, SPR_HMER, "HMER",
7912                 SPR_NOACCESS, SPR_NOACCESS,
7913                 SPR_NOACCESS, SPR_NOACCESS,
7914                 &spr_read_generic, &spr_write_hmer,
7915                 0x00000000);
7916    spr_register_hv(env, SPR_HMEER, "HMEER",
7917                 SPR_NOACCESS, SPR_NOACCESS,
7918                 SPR_NOACCESS, SPR_NOACCESS,
7919                 &spr_read_generic, &spr_write_generic,
7920                 0x00000000);
7921    spr_register_hv(env, SPR_TFMR, "TFMR",
7922                 SPR_NOACCESS, SPR_NOACCESS,
7923                 SPR_NOACCESS, SPR_NOACCESS,
7924                 &spr_read_generic, &spr_write_generic,
7925                 0x00000000);
7926    spr_register_hv(env, SPR_LPIDR, "LPIDR",
7927                 SPR_NOACCESS, SPR_NOACCESS,
7928                 SPR_NOACCESS, SPR_NOACCESS,
7929                 &spr_read_generic, &spr_write_generic,
7930                 0x00000000);
7931    spr_register_hv(env, SPR_HFSCR, "HFSCR",
7932                 SPR_NOACCESS, SPR_NOACCESS,
7933                 SPR_NOACCESS, SPR_NOACCESS,
7934                 &spr_read_generic, &spr_write_generic,
7935                 0x00000000);
7936    spr_register_hv(env, SPR_MMCRC, "MMCRC",
7937                 SPR_NOACCESS, SPR_NOACCESS,
7938                 SPR_NOACCESS, SPR_NOACCESS,
7939                 &spr_read_generic, &spr_write_generic,
7940                 0x00000000);
7941    spr_register_hv(env, SPR_MMCRH, "MMCRH",
7942                 SPR_NOACCESS, SPR_NOACCESS,
7943                 SPR_NOACCESS, SPR_NOACCESS,
7944                 &spr_read_generic, &spr_write_generic,
7945                 0x00000000);
7946    spr_register_hv(env, SPR_HSPRG0, "HSPRG0",
7947                 SPR_NOACCESS, SPR_NOACCESS,
7948                 SPR_NOACCESS, SPR_NOACCESS,
7949                 &spr_read_generic, &spr_write_generic,
7950                 0x00000000);
7951    spr_register_hv(env, SPR_HSPRG1, "HSPRG1",
7952                 SPR_NOACCESS, SPR_NOACCESS,
7953                 SPR_NOACCESS, SPR_NOACCESS,
7954                 &spr_read_generic, &spr_write_generic,
7955                 0x00000000);
7956    spr_register_hv(env, SPR_HSRR0, "HSRR0",
7957                 SPR_NOACCESS, SPR_NOACCESS,
7958                 SPR_NOACCESS, SPR_NOACCESS,
7959                 &spr_read_generic, &spr_write_generic,
7960                 0x00000000);
7961    spr_register_hv(env, SPR_HSRR1, "HSRR1",
7962                 SPR_NOACCESS, SPR_NOACCESS,
7963                 SPR_NOACCESS, SPR_NOACCESS,
7964                 &spr_read_generic, &spr_write_generic,
7965                 0x00000000);
7966    spr_register_hv(env, SPR_HDAR, "HDAR",
7967                 SPR_NOACCESS, SPR_NOACCESS,
7968                 SPR_NOACCESS, SPR_NOACCESS,
7969                 &spr_read_generic, &spr_write_generic,
7970                 0x00000000);
7971    spr_register_hv(env, SPR_HDSISR, "HDSISR",
7972                 SPR_NOACCESS, SPR_NOACCESS,
7973                 SPR_NOACCESS, SPR_NOACCESS,
7974                 &spr_read_generic, &spr_write_generic,
7975                 0x00000000);
7976    spr_register_hv(env, SPR_RMOR, "RMOR",
7977                 SPR_NOACCESS, SPR_NOACCESS,
7978                 SPR_NOACCESS, SPR_NOACCESS,
7979                 &spr_read_generic, &spr_write_generic,
7980                 0x00000000);
7981    spr_register_hv(env, SPR_HRMOR, "HRMOR",
7982                 SPR_NOACCESS, SPR_NOACCESS,
7983                 SPR_NOACCESS, SPR_NOACCESS,
7984                 &spr_read_generic, &spr_write_generic,
7985                 0x00000000);
7986}
7987
7988static void gen_spr_power8_ids(CPUPPCState *env)
7989{
7990    /* Thread identification */
7991    spr_register(env, SPR_TIR, "TIR",
7992                 SPR_NOACCESS, SPR_NOACCESS,
7993                 &spr_read_generic, SPR_NOACCESS,
7994                 0x00000000);
7995}
7996
7997static void gen_spr_book3s_purr(CPUPPCState *env)
7998{
7999#if !defined(CONFIG_USER_ONLY)
8000    /* PURR & SPURR: Hack - treat these as aliases for the TB for now */

8001    spr_register_kvm(env, SPR_PURR,   "PURR",
8002                     &spr_read_purr, SPR_NOACCESS,
8003                     &spr_read_purr, SPR_NOACCESS,
8004                     KVM_REG_PPC_PURR, 0x00000000);
8005    spr_register_kvm(env, SPR_SPURR,   "SPURR",
8006                     &spr_read_purr, SPR_NOACCESS,
8007                     &spr_read_purr, SPR_NOACCESS,
8008                     KVM_REG_PPC_SPURR, 0x00000000);
8009#endif
8010}
8011
8012static void gen_spr_power6_dbg(CPUPPCState *env)
8013{
8014#if !defined(CONFIG_USER_ONLY)
8015    spr_register(env, SPR_CFAR, "SPR_CFAR",
8016                 SPR_NOACCESS, SPR_NOACCESS,
8017                 &spr_read_cfar, &spr_write_cfar,
8018                 0x00000000);
8019#endif
8020}
8021
8022static void gen_spr_power5p_common(CPUPPCState *env)
8023{
8024    spr_register_kvm(env, SPR_PPR, "PPR",
8025                     &spr_read_generic, &spr_write_generic,
8026                     &spr_read_generic, &spr_write_generic,
8027                     KVM_REG_PPC_PPR, 0x00000000);
8028}
8029
8030static void gen_spr_power6_common(CPUPPCState *env)
8031{
8032#if !defined(CONFIG_USER_ONLY)
8033    spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
8034                     SPR_NOACCESS, SPR_NOACCESS,
8035                     &spr_read_generic, &spr_write_generic,
8036                     KVM_REG_PPC_DSCR, 0x00000000);
8037#endif
8038    /*
8039     * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
8040     * POWERPC_EXCP_INVAL_SPR.
8041     */
8042    spr_register(env, SPR_PCR, "PCR",
8043                 SPR_NOACCESS, SPR_NOACCESS,
8044                 SPR_NOACCESS, SPR_NOACCESS,
8045                 0x00000000);
8046}
8047
8048static void spr_read_tar(DisasContext *ctx, int gprn, int sprn)
8049{
8050    gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
8051    spr_read_generic(ctx, gprn, sprn);
8052}
8053
8054static void spr_write_tar(DisasContext *ctx, int sprn, int gprn)
8055{
8056    gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
8057    spr_write_generic(ctx, sprn, gprn);
8058}
8059
8060static void gen_spr_power8_tce_address_control(CPUPPCState *env)
8061{
8062    spr_register_kvm(env, SPR_TAR, "TAR",
8063                     &spr_read_tar, &spr_write_tar,
8064                     &spr_read_generic, &spr_write_generic,
8065                     KVM_REG_PPC_TAR, 0x00000000);
8066}
8067
8068static void spr_read_tm(DisasContext *ctx, int gprn, int sprn)
8069{
8070    gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
8071    spr_read_generic(ctx, gprn, sprn);
8072}
8073
8074static void spr_write_tm(DisasContext *ctx, int sprn, int gprn)
8075{
8076    gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
8077    spr_write_generic(ctx, sprn, gprn);
8078}
8079
8080static void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn)
8081{
8082    gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
8083    spr_read_prev_upper32(ctx, gprn, sprn);
8084}
8085
8086static void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn)
8087{
8088    gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
8089    spr_write_prev_upper32(ctx, sprn, gprn);
8090}
8091
8092static void gen_spr_power8_tm(CPUPPCState *env)
8093{
8094    spr_register_kvm(env, SPR_TFHAR, "TFHAR",
8095                     &spr_read_tm, &spr_write_tm,
8096                     &spr_read_tm, &spr_write_tm,
8097                     KVM_REG_PPC_TFHAR, 0x00000000);
8098    spr_register_kvm(env, SPR_TFIAR, "TFIAR",
8099                     &spr_read_tm, &spr_write_tm,
8100                     &spr_read_tm, &spr_write_tm,
8101                     KVM_REG_PPC_TFIAR, 0x00000000);
8102    spr_register_kvm(env, SPR_TEXASR, "TEXASR",
8103                     &spr_read_tm, &spr_write_tm,
8104                     &spr_read_tm, &spr_write_tm,
8105                     KVM_REG_PPC_TEXASR, 0x00000000);
8106    spr_register(env, SPR_TEXASRU, "TEXASRU",
8107                 &spr_read_tm_upper32, &spr_write_tm_upper32,
8108                 &spr_read_tm_upper32, &spr_write_tm_upper32,
8109                 0x00000000);
8110}
8111
8112static void spr_read_ebb(DisasContext *ctx, int gprn, int sprn)
8113{
8114    gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
8115    spr_read_generic(ctx, gprn, sprn);
8116}
8117
8118static void spr_write_ebb(DisasContext *ctx, int sprn, int gprn)
8119{
8120    gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
8121    spr_write_generic(ctx, sprn, gprn);
8122}
8123
8124static void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn)
8125{
8126    gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
8127    spr_read_prev_upper32(ctx, gprn, sprn);
8128}
8129
8130static void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn)
8131{
8132    gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
8133    spr_write_prev_upper32(ctx, sprn, gprn);
8134}
8135
8136static void gen_spr_power8_ebb(CPUPPCState *env)
8137{
8138    spr_register(env, SPR_BESCRS, "BESCRS",
8139                 &spr_read_ebb, &spr_write_ebb,
8140                 &spr_read_generic, &spr_write_generic,
8141                 0x00000000);
8142    spr_register(env, SPR_BESCRSU, "BESCRSU",
8143                 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
8144                 &spr_read_prev_upper32, &spr_write_prev_upper32,
8145                 0x00000000);
8146    spr_register(env, SPR_BESCRR, "BESCRR",
8147                 &spr_read_ebb, &spr_write_ebb,
8148                 &spr_read_generic, &spr_write_generic,
8149                 0x00000000);
8150    spr_register(env, SPR_BESCRRU, "BESCRRU",
8151                 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
8152                 &spr_read_prev_upper32, &spr_write_prev_upper32,
8153                 0x00000000);
8154    spr_register_kvm(env, SPR_EBBHR, "EBBHR",
8155                     &spr_read_ebb, &spr_write_ebb,
8156                     &spr_read_generic, &spr_write_generic,
8157                     KVM_REG_PPC_EBBHR, 0x00000000);
8158    spr_register_kvm(env, SPR_EBBRR, "EBBRR",
8159                     &spr_read_ebb, &spr_write_ebb,
8160                     &spr_read_generic, &spr_write_generic,
8161                     KVM_REG_PPC_EBBRR, 0x00000000);
8162    spr_register_kvm(env, SPR_BESCR, "BESCR",
8163                     &spr_read_ebb, &spr_write_ebb,
8164                     &spr_read_generic, &spr_write_generic,
8165                     KVM_REG_PPC_BESCR, 0x00000000);
8166}
8167
8168/* Virtual Time Base */
8169static void gen_spr_vtb(CPUPPCState *env)
8170{
8171    spr_register(env, SPR_VTB, "VTB",
8172                 SPR_NOACCESS, SPR_NOACCESS,
8173                 &spr_read_tbl, SPR_NOACCESS,
8174                 0x00000000);
8175}
8176
8177static void gen_spr_power8_fscr(CPUPPCState *env)
8178{
8179#if defined(CONFIG_USER_ONLY)
8180    target_ulong initval = 1ULL << FSCR_TAR;
8181#else
8182    target_ulong initval = 0;
8183#endif
8184    spr_register_kvm(env, SPR_FSCR, "FSCR",
8185                     SPR_NOACCESS, SPR_NOACCESS,
8186                     &spr_read_generic, &spr_write_generic,
8187                     KVM_REG_PPC_FSCR, initval);
8188}
8189
8190static void gen_spr_power8_pspb(CPUPPCState *env)
8191{
8192    spr_register_kvm(env, SPR_PSPB, "PSPB",
8193                     SPR_NOACCESS, SPR_NOACCESS,
8194                     &spr_read_generic, &spr_write_generic32,
8195                     KVM_REG_PPC_PSPB, 0);
8196}
8197
8198static void gen_spr_power8_ic(CPUPPCState *env)
8199{
8200#if !defined(CONFIG_USER_ONLY)
8201    spr_register_hv(env, SPR_IC, "IC",
8202                    SPR_NOACCESS, SPR_NOACCESS,
8203                    &spr_read_generic, SPR_NOACCESS,
8204                    &spr_read_generic, &spr_write_generic,
8205                    0);
8206#endif
8207}
8208
8209static void gen_spr_power8_book4(CPUPPCState *env)
8210{
8211    /* Add a number of P8 book4 registers */
8212#if !defined(CONFIG_USER_ONLY)
8213    spr_register_kvm(env, SPR_ACOP, "ACOP",
8214                     SPR_NOACCESS, SPR_NOACCESS,
8215                     &spr_read_generic, &spr_write_generic,
8216                     KVM_REG_PPC_ACOP, 0);
8217    spr_register_kvm(env, SPR_BOOKS_PID, "PID",
8218                     SPR_NOACCESS, SPR_NOACCESS,
8219                     &spr_read_generic, &spr_write_pidr,
8220                     KVM_REG_PPC_PID, 0);
8221    spr_register_kvm(env, SPR_WORT, "WORT",
8222                     SPR_NOACCESS, SPR_NOACCESS,
8223                     &spr_read_generic, &spr_write_generic,
8224                     KVM_REG_PPC_WORT, 0);
8225#endif
8226}
8227
8228static void gen_spr_power7_book4(CPUPPCState *env)
8229{
8230    /* Add a number of P7 book4 registers */
8231#if !defined(CONFIG_USER_ONLY)
8232    spr_register_kvm(env, SPR_ACOP, "ACOP",
8233                     SPR_NOACCESS, SPR_NOACCESS,
8234                     &spr_read_generic, &spr_write_generic,
8235                     KVM_REG_PPC_ACOP, 0);
8236    spr_register_kvm(env, SPR_BOOKS_PID, "PID",
8237                     SPR_NOACCESS, SPR_NOACCESS,
8238                     &spr_read_generic, &spr_write_generic,
8239                     KVM_REG_PPC_PID, 0);
8240#endif
8241}
8242
8243static void gen_spr_power8_rpr(CPUPPCState *env)
8244{
8245#if !defined(CONFIG_USER_ONLY)
8246    spr_register_hv(env, SPR_RPR, "RPR",
8247                    SPR_NOACCESS, SPR_NOACCESS,
8248                    SPR_NOACCESS, SPR_NOACCESS,
8249                    &spr_read_generic, &spr_write_generic,
8250                    0x00000103070F1F3F);
8251#endif
8252}
8253
8254static void init_proc_book3s_common(CPUPPCState *env)
8255{
8256    gen_spr_ne_601(env);
8257    gen_tbl(env);
8258    gen_spr_usprg3(env);
8259    gen_spr_book3s_altivec(env);
8260    gen_spr_book3s_pmu_sup(env);
8261    gen_spr_book3s_pmu_user(env);
8262    gen_spr_book3s_ctrl(env);
8263}
8264
8265static void init_proc_970(CPUPPCState *env)
8266{
8267    /* Common Registers */
8268    init_proc_book3s_common(env);
8269    gen_spr_sdr1(env);
8270    gen_spr_book3s_dbg(env);
8271
8272    /* 970 Specific Registers */
8273    gen_spr_970_hid(env);
8274    gen_spr_970_hior(env);
8275    gen_low_BATs(env);
8276    gen_spr_970_pmu_sup(env);
8277    gen_spr_970_pmu_user(env);
8278    gen_spr_970_lpar(env);
8279    gen_spr_970_dbg(env);
8280
8281    /* env variables */
8282#if !defined(CONFIG_USER_ONLY)
8283    env->slb_nr = 64;
8284#endif
8285    env->dcache_line_size = 128;
8286    env->icache_line_size = 128;
8287
8288    /* Allocate hardware IRQ controller */
8289    init_excp_970(env);
8290    ppc970_irq_init(ppc_env_get_cpu(env));
8291}
8292
8293POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
8294{
8295    DeviceClass *dc = DEVICE_CLASS(oc);
8296    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8297
8298    dc->desc = "PowerPC 970";
8299    pcc->init_proc = init_proc_970;
8300    pcc->check_pow = check_pow_970;
8301    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
8302                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8303                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8304                       PPC_FLOAT_STFIWX |
8305                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8306                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
8307                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8308                       PPC_64B | PPC_ALTIVEC |
8309                       PPC_SEGMENT_64B | PPC_SLBI;
8310    pcc->insns_flags2 = PPC2_FP_CVT_S64;
8311    pcc->msr_mask = (1ull << MSR_SF) |
8312                    (1ull << MSR_VR) |
8313                    (1ull << MSR_POW) |
8314                    (1ull << MSR_EE) |
8315                    (1ull << MSR_PR) |
8316                    (1ull << MSR_FP) |
8317                    (1ull << MSR_ME) |
8318                    (1ull << MSR_FE0) |
8319                    (1ull << MSR_SE) |
8320                    (1ull << MSR_DE) |
8321                    (1ull << MSR_FE1) |
8322                    (1ull << MSR_IR) |
8323                    (1ull << MSR_DR) |
8324                    (1ull << MSR_PMM) |
8325                    (1ull << MSR_RI);
8326    pcc->mmu_model = POWERPC_MMU_64B;
8327#if defined(CONFIG_SOFTMMU)
8328    pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8329#endif
8330    pcc->excp_model = POWERPC_EXCP_970;
8331    pcc->bus_model = PPC_FLAGS_INPUT_970;
8332    pcc->bfd_mach = bfd_mach_ppc64;
8333    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8334                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8335                 POWERPC_FLAG_BUS_CLK;
8336    pcc->l1_dcache_size = 0x8000;
8337    pcc->l1_icache_size = 0x10000;
8338}
8339
8340static void init_proc_power5plus(CPUPPCState *env)
8341{
8342    /* Common Registers */
8343    init_proc_book3s_common(env);
8344    gen_spr_sdr1(env);
8345    gen_spr_book3s_dbg(env);
8346
8347    /* POWER5+ Specific Registers */
8348    gen_spr_970_hid(env);
8349    gen_spr_970_hior(env);
8350    gen_low_BATs(env);
8351    gen_spr_970_pmu_sup(env);
8352    gen_spr_970_pmu_user(env);
8353    gen_spr_power5p_common(env);
8354    gen_spr_power5p_lpar(env);
8355    gen_spr_power5p_ear(env);
8356
8357    /* env variables */
8358#if !defined(CONFIG_USER_ONLY)
8359    env->slb_nr = 64;
8360#endif
8361    env->dcache_line_size = 128;
8362    env->icache_line_size = 128;
8363
8364    /* Allocate hardware IRQ controller */
8365    init_excp_970(env);
8366    ppc970_irq_init(ppc_env_get_cpu(env));
8367}
8368
8369POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
8370{
8371    DeviceClass *dc = DEVICE_CLASS(oc);
8372    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8373
8374    dc->fw_name = "PowerPC,POWER5";
8375    dc->desc = "POWER5+";
8376    pcc->init_proc = init_proc_power5plus;
8377    pcc->check_pow = check_pow_970;
8378    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
8379                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8380                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8381                       PPC_FLOAT_STFIWX |
8382                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8383                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
8384                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8385                       PPC_64B |
8386                       PPC_SEGMENT_64B | PPC_SLBI;
8387    pcc->insns_flags2 = PPC2_FP_CVT_S64;
8388    pcc->msr_mask = (1ull << MSR_SF) |
8389                    (1ull << MSR_VR) |
8390                    (1ull << MSR_POW) |
8391                    (1ull << MSR_EE) |
8392                    (1ull << MSR_PR) |
8393                    (1ull << MSR_FP) |
8394                    (1ull << MSR_ME) |
8395                    (1ull << MSR_FE0) |
8396                    (1ull << MSR_SE) |
8397                    (1ull << MSR_DE) |
8398                    (1ull << MSR_FE1) |
8399                    (1ull << MSR_IR) |
8400                    (1ull << MSR_DR) |
8401                    (1ull << MSR_PMM) |
8402                    (1ull << MSR_RI);
8403    pcc->mmu_model = POWERPC_MMU_2_03;
8404#if defined(CONFIG_SOFTMMU)
8405    pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8406#endif
8407    pcc->excp_model = POWERPC_EXCP_970;
8408    pcc->bus_model = PPC_FLAGS_INPUT_970;
8409    pcc->bfd_mach = bfd_mach_ppc64;
8410    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8411                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8412                 POWERPC_FLAG_BUS_CLK;
8413    pcc->l1_dcache_size = 0x8000;
8414    pcc->l1_icache_size = 0x10000;
8415}
8416
8417/*
8418 * The CPU used to have a "compat" property which set the
8419 * compatibility mode PVR.  However, this was conceptually broken - it
8420 * only makes sense on the pseries machine type (otherwise the guest
8421 * owns the PCR and can control the compatibility mode itself).  It's
8422 * been replaced with the 'max-cpu-compat' property on the pseries
8423 * machine type.  For backwards compatibility, pseries specially
8424 * parses the -cpu parameter and converts old compat= parameters into
8425 * the appropriate machine parameters.  This stub implementation of
8426 * the parameter catches any uses on explicitly created CPUs.
8427 */
8428static void getset_compat_deprecated(Object *obj, Visitor *v, const char *name,
8429                                     void *opaque, Error **errp)
8430{
8431    QNull *null = NULL;
8432
8433    if (!qtest_enabled()) {
8434        error_report("CPU 'compat' property is deprecated and has no effect; "
8435                     "use max-cpu-compat machine property instead");
8436    }
8437    visit_type_null(v, name, &null, NULL);
8438    QDECREF(null);
8439}
8440
8441static const PropertyInfo ppc_compat_deprecated_propinfo = {
8442    .name = "str",
8443    .description = "compatibility mode (deprecated)",
8444    .get = getset_compat_deprecated,
8445    .set = getset_compat_deprecated,
8446};
8447static Property powerpc_servercpu_properties[] = {
8448    {
8449        .name = "compat",
8450        .info = &ppc_compat_deprecated_propinfo,
8451    },
8452    DEFINE_PROP_END_OF_LIST(),
8453};
8454
8455#ifdef CONFIG_SOFTMMU
8456static const struct ppc_segment_page_sizes POWER7_POWER8_sps = {
8457    .sps = {
8458        {
8459            .page_shift = 12, /* 4K */
8460            .slb_enc = 0,
8461            .enc = { { .page_shift = 12, .pte_enc = 0 },
8462                     { .page_shift = 16, .pte_enc = 0x7 },
8463                     { .page_shift = 24, .pte_enc = 0x38 }, },
8464        },
8465        {
8466            .page_shift = 16, /* 64K */
8467            .slb_enc = SLB_VSID_64K,
8468            .enc = { { .page_shift = 16, .pte_enc = 0x1 },
8469                     { .page_shift = 24, .pte_enc = 0x8 }, },
8470        },
8471        {
8472            .page_shift = 24, /* 16M */
8473            .slb_enc = SLB_VSID_16M,
8474            .enc = { { .page_shift = 24, .pte_enc = 0 }, },
8475        },
8476        {
8477            .page_shift = 34, /* 16G */
8478            .slb_enc = SLB_VSID_16G,
8479            .enc = { { .page_shift = 34, .pte_enc = 0x3 }, },
8480        },
8481    }
8482};
8483#endif /* CONFIG_SOFTMMU */
8484
8485static void init_proc_POWER7(CPUPPCState *env)
8486{
8487    /* Common Registers */
8488    init_proc_book3s_common(env);
8489    gen_spr_sdr1(env);
8490    gen_spr_book3s_dbg(env);
8491
8492    /* POWER7 Specific Registers */
8493    gen_spr_book3s_ids(env);
8494    gen_spr_amr(env);
8495    gen_spr_book3s_purr(env);
8496    gen_spr_power5p_common(env);
8497    gen_spr_power5p_lpar(env);
8498    gen_spr_power5p_ear(env);
8499    gen_spr_power6_common(env);
8500    gen_spr_power6_dbg(env);
8501    gen_spr_power7_book4(env);
8502
8503    /* env variables */
8504#if !defined(CONFIG_USER_ONLY)
8505    env->slb_nr = 32;
8506#endif
8507    env->ci_large_pages = true;
8508    env->dcache_line_size = 128;
8509    env->icache_line_size = 128;
8510
8511    /* Allocate hardware IRQ controller */
8512    init_excp_POWER7(env);
8513    ppcPOWER7_irq_init(ppc_env_get_cpu(env));
8514}
8515
8516static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr)
8517{
8518    if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) {
8519        return true;
8520    }
8521    if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) {
8522        return true;
8523    }
8524    return false;
8525}
8526
8527static bool cpu_has_work_POWER7(CPUState *cs)
8528{
8529    PowerPCCPU *cpu = POWERPC_CPU(cs);
8530    CPUPPCState *env = &cpu->env;
8531
8532    if (cs->halted) {
8533        if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
8534            return false;
8535        }
8536        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
8537            (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) {
8538            return true;
8539        }
8540        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
8541            (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) {
8542            return true;
8543        }
8544        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
8545            (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
8546            return true;
8547        }
8548        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
8549            (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
8550            return true;
8551        }
8552        if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
8553            return true;
8554        }
8555        return false;
8556    } else {
8557        return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
8558    }
8559}
8560
8561POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
8562{
8563    DeviceClass *dc = DEVICE_CLASS(oc);
8564    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8565    CPUClass *cc = CPU_CLASS(oc);
8566
8567    dc->fw_name = "PowerPC,POWER7";
8568    dc->desc = "POWER7";
8569    dc->props = powerpc_servercpu_properties;
8570    pcc->pvr_match = ppc_pvr_match_power7;
8571    pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05;
8572    pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
8573    pcc->init_proc = init_proc_POWER7;
8574    pcc->check_pow = check_pow_nocheck;
8575    cc->has_work = cpu_has_work_POWER7;
8576    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8577                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8578                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8579                       PPC_FLOAT_FRSQRTES |
8580                       PPC_FLOAT_STFIWX |
8581                       PPC_FLOAT_EXT |
8582                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8583                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
8584                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8585                       PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
8586                       PPC_SEGMENT_64B | PPC_SLBI |
8587                       PPC_POPCNTB | PPC_POPCNTWD |
8588                       PPC_CILDST;
8589    pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
8590                        PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8591                        PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8592                        PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 |
8593                        PPC2_PM_ISA206;
8594    pcc->msr_mask = (1ull << MSR_SF) |
8595                    (1ull << MSR_VR) |
8596                    (1ull << MSR_VSX) |
8597                    (1ull << MSR_EE) |
8598                    (1ull << MSR_PR) |
8599                    (1ull << MSR_FP) |
8600                    (1ull << MSR_ME) |
8601                    (1ull << MSR_FE0) |
8602                    (1ull << MSR_SE) |
8603                    (1ull << MSR_DE) |
8604                    (1ull << MSR_FE1) |
8605                    (1ull << MSR_IR) |
8606                    (1ull << MSR_DR) |
8607                    (1ull << MSR_PMM) |
8608                    (1ull << MSR_RI) |
8609                    (1ull << MSR_LE);
8610    pcc->mmu_model = POWERPC_MMU_2_06;
8611#if defined(CONFIG_SOFTMMU)
8612    pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8613    pcc->sps = &POWER7_POWER8_sps;
8614#endif
8615    pcc->excp_model = POWERPC_EXCP_POWER7;
8616    pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
8617    pcc->bfd_mach = bfd_mach_ppc64;
8618    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8619                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8620                 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8621                 POWERPC_FLAG_VSX;
8622    pcc->l1_dcache_size = 0x8000;
8623    pcc->l1_icache_size = 0x8000;
8624    pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
8625}
8626
8627static void init_proc_POWER8(CPUPPCState *env)
8628{
8629    /* Common Registers */
8630    init_proc_book3s_common(env);
8631    gen_spr_sdr1(env);
8632    gen_spr_book3s_207_dbg(env);
8633
8634    /* POWER8 Specific Registers */
8635    gen_spr_book3s_ids(env);
8636    gen_spr_amr(env);
8637    gen_spr_iamr(env);
8638    gen_spr_book3s_purr(env);
8639    gen_spr_power5p_common(env);
8640    gen_spr_power5p_lpar(env);
8641    gen_spr_power5p_ear(env);
8642    gen_spr_power6_common(env);
8643    gen_spr_power6_dbg(env);
8644    gen_spr_power8_tce_address_control(env);
8645    gen_spr_power8_ids(env);
8646    gen_spr_power8_ebb(env);
8647    gen_spr_power8_fscr(env);
8648    gen_spr_power8_pmu_sup(env);
8649    gen_spr_power8_pmu_user(env);
8650    gen_spr_power8_tm(env);
8651    gen_spr_power8_pspb(env);
8652    gen_spr_vtb(env);
8653    gen_spr_power8_ic(env);
8654    gen_spr_power8_book4(env);
8655    gen_spr_power8_rpr(env);
8656
8657    /* env variables */
8658#if !defined(CONFIG_USER_ONLY)
8659    env->slb_nr = 32;
8660#endif
8661    env->ci_large_pages = true;
8662    env->dcache_line_size = 128;
8663    env->icache_line_size = 128;
8664
8665    /* Allocate hardware IRQ controller */
8666    init_excp_POWER8(env);
8667    ppcPOWER7_irq_init(ppc_env_get_cpu(env));
8668}
8669
8670static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr)
8671{
8672    if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) {
8673        return true;
8674    }
8675    if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) {
8676        return true;
8677    }
8678    if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) {
8679        return true;
8680    }
8681    return false;
8682}
8683
8684static bool cpu_has_work_POWER8(CPUState *cs)
8685{
8686    PowerPCCPU *cpu = POWERPC_CPU(cs);
8687    CPUPPCState *env = &cpu->env;
8688
8689    if (cs->halted) {
8690        if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
8691            return false;
8692        }
8693        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
8694            (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) {
8695            return true;
8696        }
8697        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
8698            (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) {
8699            return true;
8700        }
8701        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
8702            (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
8703            return true;
8704        }
8705        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
8706            (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
8707            return true;
8708        }
8709        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
8710            (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) {
8711            return true;
8712        }
8713        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
8714            (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) {
8715            return true;
8716        }
8717        if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
8718            return true;
8719        }
8720        return false;
8721    } else {
8722        return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
8723    }
8724}
8725
8726POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
8727{
8728    DeviceClass *dc = DEVICE_CLASS(oc);
8729    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8730    CPUClass *cc = CPU_CLASS(oc);
8731
8732    dc->fw_name = "PowerPC,POWER8";
8733    dc->desc = "POWER8";
8734    dc->props = powerpc_servercpu_properties;
8735    pcc->pvr_match = ppc_pvr_match_power8;
8736    pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
8737    pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
8738    pcc->init_proc = init_proc_POWER8;
8739    pcc->check_pow = check_pow_nocheck;
8740    cc->has_work = cpu_has_work_POWER8;
8741    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8742                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8743                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8744                       PPC_FLOAT_FRSQRTES |
8745                       PPC_FLOAT_STFIWX |
8746                       PPC_FLOAT_EXT |
8747                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8748                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
8749                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8750                       PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
8751                       PPC_SEGMENT_64B | PPC_SLBI |
8752                       PPC_POPCNTB | PPC_POPCNTWD |
8753                       PPC_CILDST;
8754    pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
8755                        PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8756                        PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8757                        PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
8758                        PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
8759                        PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
8760                        PPC2_TM | PPC2_PM_ISA206;
8761    pcc->msr_mask = (1ull << MSR_SF) |
8762                    (1ull << MSR_SHV) |
8763                    (1ull << MSR_TM) |
8764                    (1ull << MSR_VR) |
8765                    (1ull << MSR_VSX) |
8766                    (1ull << MSR_EE) |
8767                    (1ull << MSR_PR) |
8768                    (1ull << MSR_FP) |
8769                    (1ull << MSR_ME) |
8770                    (1ull << MSR_FE0) |
8771                    (1ull << MSR_SE) |
8772                    (1ull << MSR_DE) |
8773                    (1ull << MSR_FE1) |
8774                    (1ull << MSR_IR) |
8775                    (1ull << MSR_DR) |
8776                    (1ull << MSR_PMM) |
8777                    (1ull << MSR_RI) |
8778                    (1ull << MSR_LE);
8779    pcc->mmu_model = POWERPC_MMU_2_07;
8780#if defined(CONFIG_SOFTMMU)
8781    pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8782    pcc->sps = &POWER7_POWER8_sps;
8783#endif
8784    pcc->excp_model = POWERPC_EXCP_POWER8;
8785    pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
8786    pcc->bfd_mach = bfd_mach_ppc64;
8787    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8788                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8789                 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8790                 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
8791    pcc->l1_dcache_size = 0x8000;
8792    pcc->l1_icache_size = 0x8000;
8793    pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
8794}
8795
8796#ifdef CONFIG_SOFTMMU
8797/*
8798 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
8799 * Encoded as array of int_32s in the form:
8800 *  0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
8801 *  x -> AP encoding
8802 *  y -> radix mode supported page size (encoded as a shift)
8803 */
8804static struct ppc_radix_page_info POWER9_radix_page_info = {
8805    .count = 4,
8806    .entries = {
8807        0x0000000c, /*  4K - enc: 0x0 */
8808        0xa0000010, /* 64K - enc: 0x5 */
8809        0x20000015, /*  2M - enc: 0x1 */
8810        0x4000001e  /*  1G - enc: 0x2 */
8811    }
8812};
8813#endif /* CONFIG_SOFTMMU */
8814
8815static void init_proc_POWER9(CPUPPCState *env)
8816{
8817    /* Common Registers */
8818    init_proc_book3s_common(env);
8819    gen_spr_book3s_207_dbg(env);
8820
8821    /* POWER8 Specific Registers */
8822    gen_spr_book3s_ids(env);
8823    gen_spr_amr(env);
8824    gen_spr_iamr(env);
8825    gen_spr_book3s_purr(env);
8826    gen_spr_power5p_common(env);
8827    gen_spr_power5p_lpar(env);
8828    gen_spr_power5p_ear(env);
8829    gen_spr_power6_common(env);
8830    gen_spr_power6_dbg(env);
8831    gen_spr_power8_tce_address_control(env);
8832    gen_spr_power8_ids(env);
8833    gen_spr_power8_ebb(env);
8834    gen_spr_power8_fscr(env);
8835    gen_spr_power8_pmu_sup(env);
8836    gen_spr_power8_pmu_user(env);
8837    gen_spr_power8_tm(env);
8838    gen_spr_power8_pspb(env);
8839    gen_spr_vtb(env);
8840    gen_spr_power8_ic(env);
8841    gen_spr_power8_book4(env);
8842    gen_spr_power8_rpr(env);
8843
8844    /* POWER9 Specific registers */
8845    spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
8846                     spr_read_generic, spr_write_generic,
8847                     KVM_REG_PPC_TIDR, 0);
8848
8849    /* FIXME: Filter fields properly based on privilege level */
8850    spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
8851                        spr_read_generic, spr_write_generic,
8852                        KVM_REG_PPC_PSSCR, 0);
8853
8854    /* env variables */
8855#if !defined(CONFIG_USER_ONLY)
8856    env->slb_nr = 32;
8857#endif
8858    env->ci_large_pages = true;
8859    env->dcache_line_size = 128;
8860    env->icache_line_size = 128;
8861
8862    /* Allocate hardware IRQ controller */
8863    init_excp_POWER8(env);
8864    ppcPOWER7_irq_init(ppc_env_get_cpu(env));
8865}
8866
8867static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr)
8868{
8869    if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) {
8870        return true;
8871    }
8872    return false;
8873}
8874
8875static bool cpu_has_work_POWER9(CPUState *cs)
8876{
8877    PowerPCCPU *cpu = POWERPC_CPU(cs);
8878    CPUPPCState *env = &cpu->env;
8879
8880    if (cs->halted) {
8881        if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
8882            return false;
8883        }
8884        /* External Exception */
8885        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
8886            (env->spr[SPR_LPCR] & LPCR_EEE)) {
8887            return true;
8888        }
8889        /* Decrementer Exception */
8890        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
8891            (env->spr[SPR_LPCR] & LPCR_DEE)) {
8892            return true;
8893        }
8894        /* Machine Check or Hypervisor Maintenance Exception */
8895        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
8896            1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
8897            return true;
8898        }
8899        /* Privileged Doorbell Exception */
8900        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
8901            (env->spr[SPR_LPCR] & LPCR_PDEE)) {
8902            return true;
8903        }
8904        /* Hypervisor Doorbell Exception */
8905        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
8906            (env->spr[SPR_LPCR] & LPCR_HDEE)) {
8907            return true;
8908        }
8909        if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
8910            return true;
8911        }
8912        return false;
8913    } else {
8914        return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
8915    }
8916}
8917
8918POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
8919{
8920    DeviceClass *dc = DEVICE_CLASS(oc);
8921    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8922    CPUClass *cc = CPU_CLASS(oc);
8923
8924    dc->fw_name = "PowerPC,POWER9";
8925    dc->desc = "POWER9";
8926    dc->props = powerpc_servercpu_properties;
8927    pcc->pvr_match = ppc_pvr_match_power9;
8928    pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07;
8929    pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 |
8930                         PCR_COMPAT_2_05;
8931    pcc->init_proc = init_proc_POWER9;
8932    pcc->check_pow = check_pow_nocheck;
8933    cc->has_work = cpu_has_work_POWER9;
8934    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8935                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8936                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8937                       PPC_FLOAT_FRSQRTES |
8938                       PPC_FLOAT_STFIWX |
8939                       PPC_FLOAT_EXT |
8940                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8941                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
8942                       PPC_MEM_TLBSYNC |
8943                       PPC_64B | PPC_64BX | PPC_ALTIVEC |
8944                       PPC_SEGMENT_64B | PPC_SLBI |
8945                       PPC_POPCNTB | PPC_POPCNTWD |
8946                       PPC_CILDST;
8947    pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
8948                        PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8949                        PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8950                        PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
8951                        PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
8952                        PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
8953                        PPC2_TM | PPC2_PM_ISA206 | PPC2_ISA300;
8954    pcc->msr_mask = (1ull << MSR_SF) |
8955                    (1ull << MSR_TM) |
8956                    (1ull << MSR_VR) |
8957                    (1ull << MSR_VSX) |
8958                    (1ull << MSR_EE) |
8959                    (1ull << MSR_PR) |
8960                    (1ull << MSR_FP) |
8961                    (1ull << MSR_ME) |
8962                    (1ull << MSR_FE0) |
8963                    (1ull << MSR_SE) |
8964                    (1ull << MSR_DE) |
8965                    (1ull << MSR_FE1) |
8966                    (1ull << MSR_IR) |
8967                    (1ull << MSR_DR) |
8968                    (1ull << MSR_PMM) |
8969                    (1ull << MSR_RI) |
8970                    (1ull << MSR_LE);
8971    pcc->mmu_model = POWERPC_MMU_3_00;
8972#if defined(CONFIG_SOFTMMU)
8973    pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault;
8974    /* segment page size remain the same */
8975    pcc->sps = &POWER7_POWER8_sps;
8976    pcc->radix_page_info = &POWER9_radix_page_info;
8977#endif
8978    pcc->excp_model = POWERPC_EXCP_POWER8;
8979    pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
8980    pcc->bfd_mach = bfd_mach_ppc64;
8981    pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8982                 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8983                 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8984                 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
8985    pcc->l1_dcache_size = 0x8000;
8986    pcc->l1_icache_size = 0x8000;
8987    pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
8988}
8989
8990#if !defined(CONFIG_USER_ONLY)
8991void cpu_ppc_set_papr(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
8992{
8993    CPUPPCState *env = &cpu->env;
8994    ppc_spr_t *lpcr = &env->spr_cb[SPR_LPCR];
8995    ppc_spr_t *amor = &env->spr_cb[SPR_AMOR];
8996
8997    cpu->vhyp = vhyp;
8998
8999    /* PAPR always has exception vectors in RAM not ROM. To ensure this,
9000     * MSR[IP] should never be set.

9001     *
9002     * We also disallow setting of MSR_HV
9003     */
9004    env->msr_mask &= ~((1ull << MSR_EP) | MSR_HVB);
9005
9006    /* Set emulated LPCR to not send interrupts to hypervisor. Note that
9007     * under KVM, the actual HW LPCR will be set differently by KVM itself,
9008     * the settings below ensure proper operations with TCG in absence of
9009     * a real hypervisor.
9010     *
9011     * Clearing VPM0 will also cause us to use RMOR in mmu-hash64.c for
9012     * real mode accesses, which thankfully defaults to 0 and isn't
9013     * accessible in guest mode.
9014     */
9015    lpcr->default_value &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV);
9016    lpcr->default_value |= LPCR_LPES0 | LPCR_LPES1;
9017
9018    /* Set RMLS to the max (ie, 16G) */
9019    lpcr->default_value &= ~LPCR_RMLS;
9020    lpcr->default_value |= 1ull << LPCR_RMLS_SHIFT;
9021
9022    switch (env->mmu_model) {
9023    case POWERPC_MMU_3_00:
9024        /* By default we choose legacy mode and switch to new hash or radix
9025         * when a register process table hcall is made. So disable process
9026         * tables and guest translation shootdown by default
9027         *
9028         * Hot-plugged CPUs inherit from the guest radix setting under
9029         * KVM but not under TCG. Update the default LPCR to keep new
9030         * CPUs in sync when radix is enabled.
9031         */
9032        if (ppc64_radix_guest(cpu)) {
9033            lpcr->default_value |= LPCR_UPRT | LPCR_GTSE;
9034        } else {
9035            lpcr->default_value &= ~(LPCR_UPRT | LPCR_GTSE);
9036        }
9037        lpcr->default_value |= LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE |
9038                               LPCR_OEE;
9039        break;
9040    default:
9041        /* P7 and P8 has slightly different PECE bits, mostly because P8 adds
9042         * bit 47 and 48 which are reserved on P7. Here we set them all, which
9043         * will work as expected for both implementations
9044         */
9045        lpcr->default_value |= LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
9046                               LPCR_P8_PECE3 | LPCR_P8_PECE4;
9047    }
9048
9049    /* We should be followed by a CPU reset but update the active value
9050     * just in case...
9051     */
9052    env->spr[SPR_LPCR] = lpcr->default_value;
9053
9054    /* Set a full AMOR so guest can use the AMR as it sees fit */
9055    env->spr[SPR_AMOR] = amor->default_value = 0xffffffffffffffffull;
9056
9057    /* Update some env bits based on new LPCR value */
9058    ppc_hash64_update_rmls(env);
9059    ppc_hash64_update_vrma(env);
9060
9061    /* Tell KVM that we're in PAPR mode */
9062    if (kvm_enabled()) {
9063        kvmppc_set_papr(cpu);
9064    }
9065}
9066
9067#endif /* !defined(CONFIG_USER_ONLY) */
9068
9069#endif /* defined(TARGET_PPC64) */
9070
9071/*****************************************************************************/
9072/* Generic CPU instantiation routine                                         */
9073static void init_ppc_proc(PowerPCCPU *cpu)
9074{
9075    PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9076    CPUPPCState *env = &cpu->env;
9077#if !defined(CONFIG_USER_ONLY)
9078    int i;
9079
9080    env->irq_inputs = NULL;
9081    /* Set all exception vectors to an invalid address */
9082    for (i = 0; i < POWERPC_EXCP_NB; i++)
9083        env->excp_vectors[i] = (target_ulong)(-1ULL);
9084    env->ivor_mask = 0x00000000;
9085    env->ivpr_mask = 0x00000000;
9086    /* Default MMU definitions */
9087    env->nb_BATs = 0;
9088    env->nb_tlb = 0;
9089    env->nb_ways = 0;
9090    env->tlb_type = TLB_NONE;
9091#endif
9092    /* Register SPR common to all PowerPC implementations */
9093    gen_spr_generic(env);
9094    spr_register(env, SPR_PVR, "PVR",
9095                 /* Linux permits userspace to read PVR */
9096#if defined(CONFIG_LINUX_USER)
9097                 &spr_read_generic,
9098#else
9099                 SPR_NOACCESS,
9100#endif
9101                 SPR_NOACCESS,
9102                 &spr_read_generic, SPR_NOACCESS,
9103                 pcc->pvr);
9104    /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
9105    if (pcc->svr != POWERPC_SVR_NONE) {
9106        if (pcc->svr & POWERPC_SVR_E500) {
9107            spr_register(env, SPR_E500_SVR, "SVR",
9108                         SPR_NOACCESS, SPR_NOACCESS,
9109                         &spr_read_generic, SPR_NOACCESS,
9110                         pcc->svr & ~POWERPC_SVR_E500);
9111        } else {
9112            spr_register(env, SPR_SVR, "SVR",
9113                         SPR_NOACCESS, SPR_NOACCESS,
9114                         &spr_read_generic, SPR_NOACCESS,
9115                         pcc->svr);
9116        }
9117    }
9118    /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
9119    (*pcc->init_proc)(env);
9120
9121    /* MSR bits & flags consistency checks */
9122    if (env->msr_mask & (1 << 25)) {
9123        switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9124        case POWERPC_FLAG_SPE:
9125        case POWERPC_FLAG_VRE:
9126            break;
9127        default:
9128            fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9129                    "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
9130            exit(1);
9131        }
9132    } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9133        fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9134                "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
9135        exit(1);
9136    }
9137    if (env->msr_mask & (1 << 17)) {
9138        switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9139        case POWERPC_FLAG_TGPR:
9140        case POWERPC_FLAG_CE:
9141            break;
9142        default:
9143            fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9144                    "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
9145            exit(1);
9146        }
9147    } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9148        fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9149                "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
9150        exit(1);
9151    }
9152    if (env->msr_mask & (1 << 10)) {
9153        switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9154                              POWERPC_FLAG_UBLE)) {
9155        case POWERPC_FLAG_SE:
9156        case POWERPC_FLAG_DWE:
9157        case POWERPC_FLAG_UBLE:
9158            break;
9159        default:
9160            fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9161                    "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
9162                    "POWERPC_FLAG_UBLE\n");
9163            exit(1);
9164        }
9165    } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9166                             POWERPC_FLAG_UBLE)) {
9167        fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9168                "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
9169                "POWERPC_FLAG_UBLE\n");
9170            exit(1);
9171    }
9172    if (env->msr_mask & (1 << 9)) {
9173        switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9174        case POWERPC_FLAG_BE:
9175        case POWERPC_FLAG_DE:
9176            break;
9177        default:
9178            fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9179                    "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
9180            exit(1);
9181        }
9182    } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9183        fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9184                "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
9185        exit(1);
9186    }
9187    if (env->msr_mask & (1 << 2)) {
9188        switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9189        case POWERPC_FLAG_PX:
9190        case POWERPC_FLAG_PMM:
9191            break;
9192        default:
9193            fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9194                    "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
9195            exit(1);
9196        }
9197    } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9198        fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9199                "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
9200        exit(1);
9201    }
9202    if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
9203        fprintf(stderr, "PowerPC flags inconsistency\n"
9204                "Should define the time-base and decrementer clock source\n");
9205        exit(1);
9206    }
9207    /* Allocate TLBs buffer when needed */
9208#if !defined(CONFIG_USER_ONLY)
9209    if (env->nb_tlb != 0) {
9210        int nb_tlb = env->nb_tlb;
9211        if (env->id_tlbs != 0)
9212            nb_tlb *= 2;
9213        switch (env->tlb_type) {
9214        case TLB_6XX:
9215            env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
9216            break;
9217        case TLB_EMB:
9218            env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
9219            break;
9220        case TLB_MAS:
9221            env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
9222            break;
9223        }
9224        /* Pre-compute some useful values */
9225        env->tlb_per_way = env->nb_tlb / env->nb_ways;
9226    }
9227    if (env->irq_inputs == NULL) {
9228        fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
9229                " Attempt QEMU to crash very soon !\n");
9230    }
9231#endif
9232    if (env->check_pow == NULL) {
9233        fprintf(stderr, "WARNING: no power management check handler "
9234                "registered.\n"
9235                " Attempt QEMU to crash very soon !\n");
9236    }
9237}
9238
9239#if defined(PPC_DUMP_CPU)
9240static void dump_ppc_sprs(CPUPPCState *env)
9241{
9242    ppc_spr_t *spr;
9243#if !defined(CONFIG_USER_ONLY)
9244    uint32_t sr, sw;
9245#endif
9246    uint32_t ur, uw;
9247    int i, j, n;
9248
9249    printf("Special purpose registers:\n");
9250    for (i = 0; i < 32; i++) {
9251        for (j = 0; j < 32; j++) {
9252            n = (i << 5) | j;
9253            spr = &env->spr_cb[n];
9254            uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
9255            ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
9256#if !defined(CONFIG_USER_ONLY)
9257            sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
9258            sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
9259            if (sw || sr || uw || ur) {
9260                printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
9261                       (i << 5) | j, (i << 5) | j, spr->name,
9262                       sw ? 'w' : '-', sr ? 'r' : '-',
9263                       uw ? 'w' : '-', ur ? 'r' : '-');
9264            }
9265#else
9266            if (uw || ur) {
9267                printf("SPR: %4d (%03x) %-8s u%c%c\n",
9268                       (i << 5) | j, (i << 5) | j, spr->name,
9269                       uw ? 'w' : '-', ur ? 'r' : '-');
9270            }
9271#endif
9272        }
9273    }
9274    fflush(stdout);
9275    fflush(stderr);
9276}
9277#endif
9278
9279/*****************************************************************************/
9280
9281/* Opcode types */
9282enum {
9283    PPC_DIRECT   = 0, /* Opcode routine        */
9284    PPC_INDIRECT = 1, /* Indirect opcode table */
9285};
9286
9287#define PPC_OPCODE_MASK 0x3
9288
9289static inline int is_indirect_opcode(void *handler)
9290{
9291    return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT;
9292}
9293
9294static inline opc_handler_t **ind_table(void *handler)
9295{
9296    return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK);
9297}
9298
9299/* Instruction table creation */
9300/* Opcodes tables creation */
9301static void fill_new_table(opc_handler_t **table, int len)
9302{
9303    int i;
9304
9305    for (i = 0; i < len; i++)
9306        table[i] = &invalid_handler;
9307}
9308
9309static int create_new_table(opc_handler_t **table, unsigned char idx)
9310{
9311    opc_handler_t **tmp;
9312
9313    tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN);
9314    fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN);
9315    table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
9316
9317    return 0;
9318}
9319
9320static int insert_in_table(opc_handler_t **table, unsigned char idx,
9321                            opc_handler_t *handler)
9322{
9323    if (table[idx] != &invalid_handler)
9324        return -1;
9325    table[idx] = handler;
9326
9327    return 0;
9328}
9329
9330static int register_direct_insn(opc_handler_t **ppc_opcodes,
9331                                unsigned char idx, opc_handler_t *handler)
9332{
9333    if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9334        printf("*** ERROR: opcode %02x already assigned in main "
9335               "opcode table\n", idx);
9336#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9337        printf("           Registered handler '%s' - new handler '%s'\n",
9338               ppc_opcodes[idx]->oname, handler->oname);
9339#endif
9340        return -1;
9341    }
9342
9343    return 0;
9344}
9345
9346static int register_ind_in_table(opc_handler_t **table,
9347                                 unsigned char idx1, unsigned char idx2,
9348                                 opc_handler_t *handler)
9349{
9350    if (table[idx1] == &invalid_handler) {
9351        if (create_new_table(table, idx1) < 0) {
9352            printf("*** ERROR: unable to create indirect table "
9353                   "idx=%02x\n", idx1);
9354            return -1;
9355        }
9356    } else {
9357        if (!is_indirect_opcode(table[idx1])) {
9358            printf("*** ERROR: idx %02x already assigned to a direct "
9359                   "opcode\n", idx1);
9360#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9361            printf("           Registered handler '%s' - new handler '%s'\n",
9362                   ind_table(table[idx1])[idx2]->oname, handler->oname);
9363#endif
9364            return -1;
9365        }
9366    }
9367    if (handler != NULL &&
9368        insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9369        printf("*** ERROR: opcode %02x already assigned in "
9370               "opcode table %02x\n", idx2, idx1);
9371#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9372        printf("           Registered handler '%s' - new handler '%s'\n",
9373               ind_table(table[idx1])[idx2]->oname, handler->oname);
9374#endif
9375        return -1;
9376    }
9377
9378    return 0;
9379}
9380
9381static int register_ind_insn(opc_handler_t **ppc_opcodes,
9382                             unsigned char idx1, unsigned char idx2,
9383                             opc_handler_t *handler)
9384{
9385    return register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
9386}
9387
9388static int register_dblind_insn(opc_handler_t **ppc_opcodes,
9389                                unsigned char idx1, unsigned char idx2,
9390                                unsigned char idx3, opc_handler_t *handler)
9391{
9392    if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9393        printf("*** ERROR: unable to join indirect table idx "
9394               "[%02x-%02x]\n", idx1, idx2);
9395        return -1;
9396    }
9397    if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
9398                              handler) < 0) {
9399        printf("*** ERROR: unable to insert opcode "
9400               "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9401        return -1;
9402    }
9403
9404    return 0;
9405}
9406
9407static int register_trplind_insn(opc_handler_t **ppc_opcodes,
9408                                 unsigned char idx1, unsigned char idx2,
9409                                 unsigned char idx3, unsigned char idx4,
9410                                 opc_handler_t *handler)
9411{
9412    opc_handler_t **table;
9413
9414    if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9415        printf("*** ERROR: unable to join indirect table idx "
9416               "[%02x-%02x]\n", idx1, idx2);
9417        return -1;
9418    }
9419    table = ind_table(ppc_opcodes[idx1]);
9420    if (register_ind_in_table(table, idx2, idx3, NULL) < 0) {
9421        printf("*** ERROR: unable to join 2nd-level indirect table idx "
9422               "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9423        return -1;
9424    }
9425    table = ind_table(table[idx2]);
9426    if (register_ind_in_table(table, idx3, idx4, handler) < 0) {
9427        printf("*** ERROR: unable to insert opcode "
9428               "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4);
9429        return -1;
9430    }
9431    return 0;
9432}
9433static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn)
9434{
9435    if (insn->opc2 != 0xFF) {
9436        if (insn->opc3 != 0xFF) {
9437            if (insn->opc4 != 0xFF) {
9438                if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9439                                          insn->opc3, insn->opc4,
9440                                          &insn->handler) < 0) {
9441                    return -1;
9442                }
9443            } else {
9444                if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9445                                         insn->opc3, &insn->handler) < 0)
9446                    return -1;
9447            }
9448        } else {
9449            if (register_ind_insn(ppc_opcodes, insn->opc1,
9450                                  insn->opc2, &insn->handler) < 0)
9451                return -1;
9452        }
9453    } else {
9454        if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
9455            return -1;
9456    }
9457
9458    return 0;
9459}
9460
9461static int test_opcode_table(opc_handler_t **table, int len)
9462{
9463    int i, count, tmp;
9464
9465    for (i = 0, count = 0; i < len; i++) {
9466        /* Consistency fixup */
9467        if (table[i] == NULL)
9468            table[i] = &invalid_handler;
9469        if (table[i] != &invalid_handler) {
9470            if (is_indirect_opcode(table[i])) {
9471                tmp = test_opcode_table(ind_table(table[i]),
9472                    PPC_CPU_INDIRECT_OPCODES_LEN);
9473                if (tmp == 0) {
9474                    free(table[i]);
9475                    table[i] = &invalid_handler;
9476                } else {
9477                    count++;
9478                }
9479            } else {
9480                count++;
9481            }
9482        }
9483    }
9484
9485    return count;
9486}
9487
9488static void fix_opcode_tables(opc_handler_t **ppc_opcodes)
9489{
9490    if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0)
9491        printf("*** WARNING: no opcode defined !\n");
9492}
9493
9494/*****************************************************************************/
9495static void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
9496{
9497    PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9498    CPUPPCState *env = &cpu->env;
9499    opcode_t *opc;
9500
9501    fill_new_table(env->opcodes, PPC_CPU_OPCODES_LEN);
9502    for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
9503        if (((opc->handler.type & pcc->insns_flags) != 0) ||
9504            ((opc->handler.type2 & pcc->insns_flags2) != 0)) {
9505            if (register_insn(env->opcodes, opc) < 0) {
9506                error_setg(errp, "ERROR initializing PowerPC instruction "
9507                           "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
9508                           opc->opc3);
9509                return;
9510            }
9511        }
9512    }
9513    fix_opcode_tables(env->opcodes);
9514    fflush(stdout);
9515    fflush(stderr);
9516}
9517
9518#if defined(PPC_DUMP_CPU)
9519static void dump_ppc_insns(CPUPPCState *env)
9520{
9521    opc_handler_t **table, *handler;
9522    const char *p, *q;
9523    uint8_t opc1, opc2, opc3, opc4;
9524
9525    printf("Instructions set:\n");
9526    /* opc1 is 6 bits long */
9527    for (opc1 = 0x00; opc1 < PPC_CPU_OPCODES_LEN; opc1++) {
9528        table = env->opcodes;
9529        handler = table[opc1];
9530        if (is_indirect_opcode(handler)) {
9531            /* opc2 is 5 bits long */
9532            for (opc2 = 0; opc2 < PPC_CPU_INDIRECT_OPCODES_LEN; opc2++) {
9533                table = env->opcodes;
9534                handler = env->opcodes[opc1];
9535                table = ind_table(handler);
9536                handler = table[opc2];
9537                if (is_indirect_opcode(handler)) {
9538                    table = ind_table(handler);
9539                    /* opc3 is 5 bits long */
9540                    for (opc3 = 0; opc3 < PPC_CPU_INDIRECT_OPCODES_LEN;
9541                            opc3++) {
9542                        handler = table[opc3];
9543                        if (is_indirect_opcode(handler)) {
9544                            table = ind_table(handler);
9545                            /* opc4 is 5 bits long */
9546                            for (opc4 = 0; opc4 < PPC_CPU_INDIRECT_OPCODES_LEN;
9547                                 opc4++) {
9548                                handler = table[opc4];
9549                                if (handler->handler != &gen_invalid) {
9550                                    printf("INSN: %02x %02x %02x %02x -- "
9551                                           "(%02d %04d %02d) : %s\n",
9552                                           opc1, opc2, opc3, opc4,
9553                                           opc1, (opc3 << 5) | opc2, opc4,
9554                                           handler->oname);
9555                                }
9556                            }
9557                        } else {
9558                            if (handler->handler != &gen_invalid) {
9559                                /* Special hack to properly dump SPE insns */
9560                                p = strchr(handler->oname, '_');
9561                                if (p == NULL) {
9562                                    printf("INSN: %02x %02x %02x (%02d %04d) : "
9563                                           "%s\n",
9564                                           opc1, opc2, opc3, opc1,
9565                                           (opc3 << 5) | opc2,
9566                                           handler->oname);
9567                                } else {
9568                                    q = "speundef";
9569                                    if ((p - handler->oname) != strlen(q)
9570                                        || (memcmp(handler->oname, q, strlen(q))
9571                                            != 0)) {
9572                                        /* First instruction */
9573                                        printf("INSN: %02x %02x %02x"
9574                                               "(%02d %04d) : %.*s\n",
9575                                               opc1, opc2 << 1, opc3, opc1,
9576                                               (opc3 << 6) | (opc2 << 1),
9577                                               (int)(p - handler->oname),
9578                                               handler->oname);
9579                                    }
9580                                    if (strcmp(p + 1, q) != 0) {
9581                                        /* Second instruction */
9582                                        printf("INSN: %02x %02x %02x "
9583                                               "(%02d %04d) : %s\n", opc1,
9584                                               (opc2 << 1) | 1, opc3, opc1,
9585                                               (opc3 << 6) | (opc2 << 1) | 1,
9586                                               p + 1);
9587                                    }
9588                                }
9589                            }
9590                        }
9591                    }
9592                } else {
9593                    if (handler->handler != &gen_invalid) {
9594                        printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9595                               opc1, opc2, opc1, opc2, handler->oname);
9596                    }
9597                }
9598            }
9599        } else {
9600            if (handler->handler != &gen_invalid) {
9601                printf("INSN: %02x -- -- (%02d ----) : %s\n",
9602                       opc1, opc1, handler->oname);
9603            }
9604        }
9605    }
9606}
9607#endif
9608
9609static bool avr_need_swap(CPUPPCState *env)
9610{
9611#ifdef HOST_WORDS_BIGENDIAN
9612    return msr_le;
9613#else
9614    return !msr_le;
9615#endif
9616}
9617
9618static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9619{
9620    if (n < 32) {
9621        stfq_p(mem_buf, env->fpr[n]);
9622        ppc_maybe_bswap_register(env, mem_buf, 8);
9623        return 8;
9624    }
9625    if (n == 32) {
9626        stl_p(mem_buf, env->fpscr);
9627        ppc_maybe_bswap_register(env, mem_buf, 4);
9628        return 4;
9629    }
9630    return 0;
9631}
9632
9633static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9634{
9635    if (n < 32) {
9636        ppc_maybe_bswap_register(env, mem_buf, 8);
9637        env->fpr[n] = ldfq_p(mem_buf);
9638        return 8;
9639    }
9640    if (n == 32) {
9641        ppc_maybe_bswap_register(env, mem_buf, 4);
9642        helper_store_fpscr(env, ldl_p(mem_buf), 0xffffffff);
9643        return 4;
9644    }
9645    return 0;
9646}
9647
9648static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9649{
9650    if (n < 32) {
9651        if (!avr_need_swap(env)) {
9652            stq_p(mem_buf, env->avr[n].u64[0]);
9653            stq_p(mem_buf+8, env->avr[n].u64[1]);
9654        } else {
9655            stq_p(mem_buf, env->avr[n].u64[1]);
9656            stq_p(mem_buf+8, env->avr[n].u64[0]);
9657        }
9658        ppc_maybe_bswap_register(env, mem_buf, 8);
9659        ppc_maybe_bswap_register(env, mem_buf + 8, 8);
9660        return 16;
9661    }
9662    if (n == 32) {
9663        stl_p(mem_buf, env->vscr);
9664        ppc_maybe_bswap_register(env, mem_buf, 4);
9665        return 4;
9666    }
9667    if (n == 33) {
9668        stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
9669        ppc_maybe_bswap_register(env, mem_buf, 4);
9670        return 4;
9671    }
9672    return 0;
9673}
9674
9675static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9676{
9677    if (n < 32) {
9678        ppc_maybe_bswap_register(env, mem_buf, 8);
9679        ppc_maybe_bswap_register(env, mem_buf + 8, 8);
9680        if (!avr_need_swap(env)) {
9681            env->avr[n].u64[0] = ldq_p(mem_buf);
9682            env->avr[n].u64[1] = ldq_p(mem_buf+8);
9683        } else {
9684            env->avr[n].u64[1] = ldq_p(mem_buf);
9685            env->avr[n].u64[0] = ldq_p(mem_buf+8);
9686        }
9687        return 16;
9688    }
9689    if (n == 32) {
9690        ppc_maybe_bswap_register(env, mem_buf, 4);
9691        env->vscr = ldl_p(mem_buf);
9692        return 4;
9693    }
9694    if (n == 33) {
9695        ppc_maybe_bswap_register(env, mem_buf, 4);
9696        env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9697        return 4;
9698    }
9699    return 0;
9700}
9701
9702static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9703{
9704    if (n < 32) {
9705#if defined(TARGET_PPC64)
9706        stl_p(mem_buf, env->gpr[n] >> 32);
9707        ppc_maybe_bswap_register(env, mem_buf, 4);
9708#else
9709        stl_p(mem_buf, env->gprh[n]);
9710#endif
9711        return 4;
9712    }
9713    if (n == 32) {
9714        stq_p(mem_buf, env->spe_acc);
9715        ppc_maybe_bswap_register(env, mem_buf, 8);
9716        return 8;
9717    }
9718    if (n == 33) {
9719        stl_p(mem_buf, env->spe_fscr);
9720        ppc_maybe_bswap_register(env, mem_buf, 4);
9721        return 4;
9722    }
9723    return 0;
9724}
9725
9726static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9727{
9728    if (n < 32) {
9729#if defined(TARGET_PPC64)
9730        target_ulong lo = (uint32_t)env->gpr[n];
9731        target_ulong hi;
9732
9733        ppc_maybe_bswap_register(env, mem_buf, 4);
9734
9735        hi = (target_ulong)ldl_p(mem_buf) << 32;
9736        env->gpr[n] = lo | hi;
9737#else
9738        env->gprh[n] = ldl_p(mem_buf);
9739#endif
9740        return 4;
9741    }
9742    if (n == 32) {
9743        ppc_maybe_bswap_register(env, mem_buf, 8);
9744        env->spe_acc = ldq_p(mem_buf);
9745        return 8;
9746    }
9747    if (n == 33) {
9748        ppc_maybe_bswap_register(env, mem_buf, 4);
9749        env->spe_fscr = ldl_p(mem_buf);
9750        return 4;
9751    }
9752    return 0;
9753}
9754
9755static int gdb_get_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9756{
9757    if (n < 32) {
9758        stq_p(mem_buf, env->vsr[n]);
9759        ppc_maybe_bswap_register(env, mem_buf, 8);
9760        return 8;
9761    }
9762    return 0;
9763}
9764
9765static int gdb_set_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9766{
9767    if (n < 32) {
9768        ppc_maybe_bswap_register(env, mem_buf, 8);
9769        env->vsr[n] = ldq_p(mem_buf);
9770        return 8;
9771    }
9772    return 0;
9773}
9774
9775static int ppc_fixup_cpu(PowerPCCPU *cpu)
9776{
9777    CPUPPCState *env = &cpu->env;
9778
9779    /* TCG doesn't (yet) emulate some groups of instructions that
9780     * are implemented on some otherwise supported CPUs (e.g. VSX
9781     * and decimal floating point instructions on POWER7).  We
9782     * remove unsupported instruction groups from the cpu state's
9783     * instruction masks and hope the guest can cope.  For at
9784     * least the pseries machine, the unavailability of these
9785     * instructions can be advertised to the guest via the device
9786     * tree. */
9787    if ((env->insns_flags & ~PPC_TCG_INSNS)
9788        || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
9789        fprintf(stderr, "Warning: Disabling some instructions which are not "
9790                "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")\n",
9791                env->insns_flags & ~PPC_TCG_INSNS,
9792                env->insns_flags2 & ~PPC_TCG_INSNS2);
9793    }
9794    env->insns_flags &= PPC_TCG_INSNS;
9795    env->insns_flags2 &= PPC_TCG_INSNS2;
9796    return 0;
9797}
9798
9799static inline bool ppc_cpu_is_valid(PowerPCCPUClass *pcc)
9800{
9801#ifdef TARGET_PPCEMB
9802    return pcc->mmu_model == POWERPC_MMU_BOOKE ||
9803           pcc->mmu_model == POWERPC_MMU_SOFT_4xx ||
9804           pcc->mmu_model == POWERPC_MMU_SOFT_4xx_Z;
9805#else
9806    return true;
9807#endif
9808}
9809
9810static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
9811{
9812    CPUState *cs = CPU(dev);
9813    PowerPCCPU *cpu = POWERPC_CPU(dev);
9814    PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9815    Error *local_err = NULL;
9816#if !defined(CONFIG_USER_ONLY)
9817    int max_smt = kvmppc_smt_threads();
9818#endif
9819
9820#if !defined(CONFIG_USER_ONLY)
9821    if (smp_threads > max_smt) {
9822        error_setg(errp, "Cannot support more than %d threads on PPC with %s",
9823                   max_smt, kvm_enabled() ? "KVM" : "TCG");
9824        return;
9825    }
9826    if (!is_power_of_2(smp_threads)) {
9827        error_setg(errp, "Cannot support %d threads on PPC with %s, "
9828                   "threads count must be a power of 2.",
9829                   smp_threads, kvm_enabled() ? "KVM" : "TCG");
9830        return;
9831    }
9832#endif
9833
9834    cpu_exec_realizefn(cs, &local_err);
9835    if (local_err != NULL) {
9836        error_propagate(errp, local_err);
9837        return;
9838    }
9839
9840#if !defined(CONFIG_USER_ONLY)
9841    cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * max_smt
9842        + (cs->cpu_index % smp_threads);
9843
9844    if (kvm_enabled() && !kvm_vcpu_id_is_valid(cpu->cpu_dt_id)) {
9845        error_setg(errp, "Can't create CPU with id %d in KVM", cpu->cpu_dt_id);
9846        error_append_hint(errp, "Adjust the number of cpus to %d "
9847                          "or try to raise the number of threads per core\n",
9848                          cpu->cpu_dt_id * smp_threads / max_smt);
9849        goto unrealize;
9850    }
9851#endif
9852
9853    if (tcg_enabled()) {
9854        if (ppc_fixup_cpu(cpu) != 0) {
9855            error_setg(errp, "Unable to emulate selected CPU with TCG");
9856            goto unrealize;
9857        }
9858    }
9859
9860#if defined(TARGET_PPCEMB)
9861    if (!ppc_cpu_is_valid(pcc)) {
9862        error_setg(errp, "CPU does not possess a BookE or 4xx MMU. "
9863                   "Please use qemu-system-ppc or qemu-system-ppc64 instead "
9864                   "or choose another CPU model.");
9865        goto unrealize;
9866    }
9867#endif
9868
9869    create_ppc_opcodes(cpu, &local_err);
9870    if (local_err != NULL) {
9871        error_propagate(errp, local_err);
9872        goto unrealize;
9873    }
9874    init_ppc_proc(cpu);
9875
9876    if (pcc->insns_flags & PPC_FLOAT) {
9877        gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg,
9878                                 33, "power-fpu.xml", 0);
9879    }
9880    if (pcc->insns_flags & PPC_ALTIVEC) {
9881        gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg,
9882                                 34, "power-altivec.xml", 0);
9883    }
9884    if (pcc->insns_flags & PPC_SPE) {
9885        gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg,
9886                                 34, "power-spe.xml", 0);
9887    }
9888    if (pcc->insns_flags2 & PPC2_VSX) {
9889        gdb_register_coprocessor(cs, gdb_get_vsx_reg, gdb_set_vsx_reg,
9890                                 32, "power-vsx.xml", 0);
9891    }
9892
9893    qemu_init_vcpu(cs);
9894
9895    pcc->parent_realize(dev, errp);
9896
9897#if defined(PPC_DUMP_CPU)
9898    {
9899        CPUPPCState *env = &cpu->env;
9900        const char *mmu_model, *excp_model, *bus_model;
9901        switch (env->mmu_model) {
9902        case POWERPC_MMU_32B:
9903            mmu_model = "PowerPC 32";
9904            break;
9905        case POWERPC_MMU_SOFT_6xx:
9906            mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
9907            break;
9908        case POWERPC_MMU_SOFT_74xx:
9909            mmu_model = "PowerPC 74xx with software driven TLBs";
9910            break;
9911        case POWERPC_MMU_SOFT_4xx:
9912            mmu_model = "PowerPC 4xx with software driven TLBs";
9913            break;
9914        case POWERPC_MMU_SOFT_4xx_Z:
9915            mmu_model = "PowerPC 4xx with software driven TLBs "
9916                "and zones protections";
9917            break;
9918        case POWERPC_MMU_REAL:
9919            mmu_model = "PowerPC real mode only";
9920            break;
9921        case POWERPC_MMU_MPC8xx:
9922            mmu_model = "PowerPC MPC8xx";
9923            break;
9924        case POWERPC_MMU_BOOKE:
9925            mmu_model = "PowerPC BookE";
9926            break;
9927        case POWERPC_MMU_BOOKE206:
9928            mmu_model = "PowerPC BookE 2.06";
9929            break;
9930        case POWERPC_MMU_601:
9931            mmu_model = "PowerPC 601";
9932            break;
9933#if defined(TARGET_PPC64)
9934        case POWERPC_MMU_64B:
9935            mmu_model = "PowerPC 64";
9936            break;
9937#endif
9938        default:
9939            mmu_model = "Unknown or invalid";
9940            break;
9941        }
9942        switch (env->excp_model) {
9943        case POWERPC_EXCP_STD:
9944            excp_model = "PowerPC";
9945            break;
9946        case POWERPC_EXCP_40x:
9947            excp_model = "PowerPC 40x";
9948            break;
9949        case POWERPC_EXCP_601:
9950            excp_model = "PowerPC 601";
9951            break;
9952        case POWERPC_EXCP_602:
9953            excp_model = "PowerPC 602";
9954            break;
9955        case POWERPC_EXCP_603:
9956            excp_model = "PowerPC 603";
9957            break;
9958        case POWERPC_EXCP_603E:
9959            excp_model = "PowerPC 603e";
9960            break;
9961        case POWERPC_EXCP_604:
9962            excp_model = "PowerPC 604";
9963            break;
9964        case POWERPC_EXCP_7x0:
9965            excp_model = "PowerPC 740/750";
9966            break;
9967        case POWERPC_EXCP_7x5:
9968            excp_model = "PowerPC 745/755";
9969            break;
9970        case POWERPC_EXCP_74xx:
9971            excp_model = "PowerPC 74xx";
9972            break;
9973        case POWERPC_EXCP_BOOKE:
9974            excp_model = "PowerPC BookE";
9975            break;
9976#if defined(TARGET_PPC64)
9977        case POWERPC_EXCP_970:
9978            excp_model = "PowerPC 970";
9979            break;
9980#endif
9981        default:
9982            excp_model = "Unknown or invalid";
9983            break;
9984        }
9985        switch (env->bus_model) {
9986        case PPC_FLAGS_INPUT_6xx:
9987            bus_model = "PowerPC 6xx";
9988            break;
9989        case PPC_FLAGS_INPUT_BookE:
9990            bus_model = "PowerPC BookE";
9991            break;
9992        case PPC_FLAGS_INPUT_405:
9993            bus_model = "PowerPC 405";
9994            break;
9995        case PPC_FLAGS_INPUT_401:
9996            bus_model = "PowerPC 401/403";
9997            break;
9998        case PPC_FLAGS_INPUT_RCPU:
9999            bus_model = "RCPU / MPC8xx";
10000            break;

10001#if defined(TARGET_PPC64)
10002        case PPC_FLAGS_INPUT_970:
10003            bus_model = "PowerPC 970";
10004            break;
10005#endif
10006        default:
10007            bus_model = "Unknown or invalid";
10008            break;
10009        }
10010        printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
10011               "    MMU model        : %s\n",
10012               object_class_get_name(OBJECT_CLASS(pcc)),
10013               pcc->pvr, pcc->msr_mask, mmu_model);
10014#if !defined(CONFIG_USER_ONLY)
10015        if (env->tlb.tlb6) {
10016            printf("                       %d %s TLB in %d ways\n",
10017                   env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
10018                   env->nb_ways);
10019        }
10020#endif
10021        printf("    Exceptions model : %s\n"
10022               "    Bus model        : %s\n",
10023               excp_model, bus_model);
10024        printf("    MSR features     :\n");
10025        if (env->flags & POWERPC_FLAG_SPE)
10026            printf("                        signal processing engine enable"
10027                   "\n");
10028        else if (env->flags & POWERPC_FLAG_VRE)
10029            printf("                        vector processor enable\n");
10030        if (env->flags & POWERPC_FLAG_TGPR)
10031            printf("                        temporary GPRs\n");
10032        else if (env->flags & POWERPC_FLAG_CE)
10033            printf("                        critical input enable\n");
10034        if (env->flags & POWERPC_FLAG_SE)
10035            printf("                        single-step trace mode\n");
10036        else if (env->flags & POWERPC_FLAG_DWE)
10037            printf("                        debug wait enable\n");
10038        else if (env->flags & POWERPC_FLAG_UBLE)
10039            printf("                        user BTB lock enable\n");
10040        if (env->flags & POWERPC_FLAG_BE)
10041            printf("                        branch-step trace mode\n");
10042        else if (env->flags & POWERPC_FLAG_DE)
10043            printf("                        debug interrupt enable\n");
10044        if (env->flags & POWERPC_FLAG_PX)
10045            printf("                        inclusive protection\n");
10046        else if (env->flags & POWERPC_FLAG_PMM)
10047            printf("                        performance monitor mark\n");
10048        if (env->flags == POWERPC_FLAG_NONE)
10049            printf("                        none\n");
10050        printf("    Time-base/decrementer clock source: %s\n",
10051               env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
10052        dump_ppc_insns(env);
10053        dump_ppc_sprs(env);
10054        fflush(stdout);
10055    }
10056#endif
10057    return;
10058
10059unrealize:
10060    cpu_exec_unrealizefn(cs);
10061}
10062
10063static void ppc_cpu_unrealizefn(DeviceState *dev, Error **errp)
10064{
10065    PowerPCCPU *cpu = POWERPC_CPU(dev);
10066    PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
10067    CPUPPCState *env = &cpu->env;
10068    Error *local_err = NULL;
10069    opc_handler_t **table, **table_2;
10070    int i, j, k;
10071
10072    pcc->parent_unrealize(dev, &local_err);
10073    if (local_err != NULL) {
10074        error_propagate(errp, local_err);
10075        return;
10076    }
10077
10078    for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) {
10079        if (env->opcodes[i] == &invalid_handler) {
10080            continue;
10081        }
10082        if (is_indirect_opcode(env->opcodes[i])) {
10083            table = ind_table(env->opcodes[i]);
10084            for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) {
10085                if (table[j] == &invalid_handler) {
10086                    continue;
10087                }
10088                if (is_indirect_opcode(table[j])) {
10089                    table_2 = ind_table(table[j]);
10090                    for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) {
10091                        if (table_2[k] != &invalid_handler &&
10092                            is_indirect_opcode(table_2[k])) {
10093                            g_free((opc_handler_t *)((uintptr_t)table_2[k] &
10094                                                     ~PPC_INDIRECT));
10095                        }
10096                    }
10097                    g_free((opc_handler_t *)((uintptr_t)table[j] &
10098                                             ~PPC_INDIRECT));
10099                }
10100            }
10101            g_free((opc_handler_t *)((uintptr_t)env->opcodes[i] &
10102                ~PPC_INDIRECT));
10103        }
10104    }
10105}
10106
10107static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
10108{
10109    ObjectClass *oc = (ObjectClass *)a;
10110    uint32_t pvr = *(uint32_t *)b;
10111    PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
10112
10113    /* -cpu host does a PVR lookup during construction */
10114    if (unlikely(strcmp(object_class_get_name(oc),
10115                        TYPE_HOST_POWERPC_CPU) == 0)) {
10116        return -1;
10117    }
10118
10119    if (!ppc_cpu_is_valid(pcc)) {
10120        return -1;
10121    }
10122
10123    return pcc->pvr == pvr ? 0 : -1;
10124}
10125
10126PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
10127{
10128    GSList *list, *item;
10129    PowerPCCPUClass *pcc = NULL;
10130
10131    list = object_class_get_list(TYPE_POWERPC_CPU, false);
10132    item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
10133    if (item != NULL) {
10134        pcc = POWERPC_CPU_CLASS(item->data);
10135    }
10136    g_slist_free(list);
10137
10138    return pcc;
10139}
10140
10141static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
10142{
10143    ObjectClass *oc = (ObjectClass *)a;
10144    uint32_t pvr = *(uint32_t *)b;
10145    PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
10146
10147    /* -cpu host does a PVR lookup during construction */
10148    if (unlikely(strcmp(object_class_get_name(oc),
10149                        TYPE_HOST_POWERPC_CPU) == 0)) {
10150        return -1;
10151    }
10152
10153    if (!ppc_cpu_is_valid(pcc)) {
10154        return -1;
10155    }
10156
10157    if (pcc->pvr_match(pcc, pvr)) {
10158        return 0;
10159    }
10160
10161    return -1;
10162}
10163
10164PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
10165{
10166    GSList *list, *item;
10167    PowerPCCPUClass *pcc = NULL;
10168
10169    list = object_class_get_list(TYPE_POWERPC_CPU, true);
10170    item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
10171    if (item != NULL) {
10172        pcc = POWERPC_CPU_CLASS(item->data);
10173    }
10174    g_slist_free(list);
10175
10176    return pcc;
10177}
10178
10179static gint ppc_cpu_compare_class_name(gconstpointer a, gconstpointer b)
10180{
10181    ObjectClass *oc = (ObjectClass *)a;
10182    const char *name = b;
10183    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10184
10185    if (strncasecmp(name, object_class_get_name(oc), strlen(name)) == 0 &&
10186        ppc_cpu_is_valid(pcc) &&
10187        strcmp(object_class_get_name(oc) + strlen(name),
10188               "-" TYPE_POWERPC_CPU) == 0) {
10189        return 0;
10190    }
10191    return -1;
10192}
10193
10194
10195static ObjectClass *ppc_cpu_class_by_name(const char *name);
10196
10197static ObjectClass *ppc_cpu_class_by_alias(PowerPCCPUAlias *alias)
10198{
10199    ObjectClass *invalid_class = (void*)ppc_cpu_class_by_alias;
10200
10201    /* Cache target class lookups in the alias table */
10202    if (!alias->oc) {
10203        alias->oc = ppc_cpu_class_by_name(alias->model);
10204        if (!alias->oc) {
10205            /* Fast check for non-existing aliases */
10206            alias->oc = invalid_class;
10207        }
10208    }
10209
10210    if (alias->oc == invalid_class) {
10211        return NULL;
10212    } else {
10213        return alias->oc;
10214    }
10215}
10216
10217static ObjectClass *ppc_cpu_class_by_name(const char *name)
10218{
10219    GSList *list, *item;
10220    ObjectClass *ret = NULL;
10221    const char *p;
10222    int i, len;
10223
10224    /* Check if the given name is a PVR */
10225    len = strlen(name);
10226    if (len == 10 && name[0] == '0' && name[1] == 'x') {
10227        p = name + 2;
10228        goto check_pvr;
10229    } else if (len == 8) {
10230        p = name;
10231    check_pvr:
10232        for (i = 0; i < 8; i++) {
10233            if (!qemu_isxdigit(*p++))
10234                break;
10235        }
10236        if (i == 8) {
10237            return OBJECT_CLASS(ppc_cpu_class_by_pvr(strtoul(name, NULL, 16)));
10238        }
10239    }
10240
10241    list = object_class_get_list(TYPE_POWERPC_CPU, false);
10242    item = g_slist_find_custom(list, name, ppc_cpu_compare_class_name);
10243    if (item != NULL) {
10244        ret = OBJECT_CLASS(item->data);
10245    }
10246    g_slist_free(list);
10247
10248    if (ret) {
10249        return ret;
10250    }
10251
10252    for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
10253        if (strcmp(ppc_cpu_aliases[i].alias, name) == 0) {
10254            return ppc_cpu_class_by_alias(&ppc_cpu_aliases[i]);
10255        }
10256    }
10257
10258    return NULL;
10259}
10260
10261const char *ppc_cpu_lookup_alias(const char *alias)
10262{
10263    int ai;
10264
10265    for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) {
10266        if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) {
10267            return ppc_cpu_aliases[ai].model;
10268        }
10269    }
10270
10271    return NULL;
10272}
10273
10274PowerPCCPU *cpu_ppc_init(const char *cpu_model)
10275{
10276    return POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, cpu_model));
10277}
10278
10279PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc)
10280{
10281    ObjectClass *oc = OBJECT_CLASS(pcc);
10282
10283    while (oc && !object_class_is_abstract(oc)) {
10284        oc = object_class_get_parent(oc);
10285    }
10286    assert(oc);
10287
10288    return POWERPC_CPU_CLASS(oc);
10289}
10290
10291/* Sort by PVR, ordering special case "host" last. */
10292static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
10293{
10294    ObjectClass *oc_a = (ObjectClass *)a;
10295    ObjectClass *oc_b = (ObjectClass *)b;
10296    PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
10297    PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
10298    const char *name_a = object_class_get_name(oc_a);
10299    const char *name_b = object_class_get_name(oc_b);
10300
10301    if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
10302        return 1;
10303    } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
10304        return -1;
10305    } else {
10306        /* Avoid an integer overflow during subtraction */
10307        if (pcc_a->pvr < pcc_b->pvr) {
10308            return -1;
10309        } else if (pcc_a->pvr > pcc_b->pvr) {
10310            return 1;
10311        } else {
10312            return 0;
10313        }
10314    }
10315}
10316
10317static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
10318{
10319    ObjectClass *oc = data;
10320    CPUListState *s = user_data;
10321    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10322    DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc));
10323    const char *typename = object_class_get_name(oc);
10324    char *name;
10325    int i;
10326
10327    if (!ppc_cpu_is_valid(pcc)) {
10328        return;
10329    }
10330    if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
10331        return;
10332    }
10333
10334    name = g_strndup(typename,
10335                     strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
10336    (*s->cpu_fprintf)(s->file, "PowerPC %-16s PVR %08x\n",
10337                      name, pcc->pvr);
10338    for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
10339        PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
10340        ObjectClass *alias_oc = ppc_cpu_class_by_alias(alias);
10341
10342        if (alias_oc != oc) {
10343            continue;
10344        }
10345        /*
10346         * If running with KVM, we might update the family alias later, so
10347         * avoid printing the wrong alias here and use "preferred" instead
10348         */
10349        if (strcmp(alias->alias, family->desc) == 0) {
10350            (*s->cpu_fprintf)(s->file,
10351                              "PowerPC %-16s (alias for preferred %s CPU)\n",
10352                              alias->alias, family->desc);
10353        } else {
10354            (*s->cpu_fprintf)(s->file, "PowerPC %-16s (alias for %s)\n",
10355                              alias->alias, name);
10356        }
10357    }
10358    g_free(name);
10359}
10360
10361void ppc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
10362{
10363    CPUListState s = {
10364        .file = f,
10365        .cpu_fprintf = cpu_fprintf,
10366    };
10367    GSList *list;
10368
10369    list = object_class_get_list(TYPE_POWERPC_CPU, false);
10370    list = g_slist_sort(list, ppc_cpu_list_compare);
10371    g_slist_foreach(list, ppc_cpu_list_entry, &s);
10372    g_slist_free(list);
10373
10374#ifdef CONFIG_KVM
10375    cpu_fprintf(f, "\n");
10376    cpu_fprintf(f, "PowerPC %-16s\n", "host");
10377#endif
10378}
10379
10380static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
10381{
10382    ObjectClass *oc = data;
10383    CpuDefinitionInfoList **first = user_data;
10384    const char *typename;
10385    CpuDefinitionInfoList *entry;
10386    CpuDefinitionInfo *info;
10387    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10388
10389    if (!ppc_cpu_is_valid(pcc)) {
10390        return;
10391    }
10392
10393    typename = object_class_get_name(oc);
10394    info = g_malloc0(sizeof(*info));
10395    info->name = g_strndup(typename,
10396                           strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
10397
10398    entry = g_malloc0(sizeof(*entry));
10399    entry->value = info;
10400    entry->next = *first;
10401    *first = entry;
10402}
10403
10404CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
10405{
10406    CpuDefinitionInfoList *cpu_list = NULL;
10407    GSList *list;
10408    int i;
10409
10410    list = object_class_get_list(TYPE_POWERPC_CPU, false);
10411    g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
10412    g_slist_free(list);
10413
10414    for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
10415        PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
10416        ObjectClass *oc;
10417        CpuDefinitionInfoList *entry;
10418        CpuDefinitionInfo *info;
10419
10420        oc = ppc_cpu_class_by_alias(alias);
10421        if (oc == NULL) {
10422            continue;
10423        }
10424
10425        info = g_malloc0(sizeof(*info));
10426        info->name = g_strdup(alias->alias);
10427        info->q_typename = g_strdup(object_class_get_name(oc));
10428
10429        entry = g_malloc0(sizeof(*entry));
10430        entry->value = info;
10431        entry->next = cpu_list;
10432        cpu_list = entry;
10433    }
10434
10435    return cpu_list;
10436}
10437
10438static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
10439{
10440    PowerPCCPU *cpu = POWERPC_CPU(cs);
10441
10442    cpu->env.nip = value;
10443}
10444
10445static bool ppc_cpu_has_work(CPUState *cs)
10446{
10447    PowerPCCPU *cpu = POWERPC_CPU(cs);
10448    CPUPPCState *env = &cpu->env;
10449
10450    return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
10451}
10452
10453/* CPUClass::reset() */
10454static void ppc_cpu_reset(CPUState *s)
10455{
10456    PowerPCCPU *cpu = POWERPC_CPU(s);
10457    PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
10458    CPUPPCState *env = &cpu->env;
10459    target_ulong msr;
10460    int i;
10461
10462    pcc->parent_reset(s);
10463
10464    msr = (target_ulong)0;
10465    msr |= (target_ulong)MSR_HVB;
10466    msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
10467    msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
10468    msr |= (target_ulong)1 << MSR_EP;
10469#if defined(DO_SINGLE_STEP) && 0
10470    /* Single step trace mode */
10471    msr |= (target_ulong)1 << MSR_SE;
10472    msr |= (target_ulong)1 << MSR_BE;
10473#endif
10474#if defined(CONFIG_USER_ONLY)
10475    msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
10476    msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
10477    msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
10478    msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
10479    msr |= (target_ulong)1 << MSR_PR;
10480#if defined(TARGET_PPC64)
10481    msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */
10482#endif
10483#if !defined(TARGET_WORDS_BIGENDIAN)
10484    msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
10485    if (!((env->msr_mask >> MSR_LE) & 1)) {
10486        fprintf(stderr, "Selected CPU does not support little-endian.\n");
10487        exit(1);
10488    }
10489#endif
10490#endif
10491
10492#if defined(TARGET_PPC64)
10493    if (env->mmu_model & POWERPC_MMU_64) {
10494        msr |= (1ULL << MSR_SF);
10495    }
10496#endif
10497
10498    hreg_store_msr(env, msr, 1);
10499
10500#if !defined(CONFIG_USER_ONLY)
10501    env->nip = env->hreset_vector | env->excp_prefix;
10502    if (env->mmu_model != POWERPC_MMU_REAL) {
10503        ppc_tlb_invalidate_all(env);
10504    }
10505#endif
10506
10507    hreg_compute_hflags(env);
10508    env->reserve_addr = (target_ulong)-1ULL;
10509    /* Be sure no exception or interrupt is pending */
10510    env->pending_interrupts = 0;
10511    s->exception_index = POWERPC_EXCP_NONE;
10512    env->error_code = 0;
10513
10514#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
10515    env->vpa_addr = 0;
10516    env->slb_shadow_addr = 0;
10517    env->slb_shadow_size = 0;
10518    env->dtl_addr = 0;
10519    env->dtl_size = 0;
10520#endif /* TARGET_PPC64 */
10521
10522    for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
10523        ppc_spr_t *spr = &env->spr_cb[i];
10524
10525        if (!spr->name) {
10526            continue;
10527        }
10528        env->spr[i] = spr->default_value;
10529    }
10530}
10531
10532#ifndef CONFIG_USER_ONLY
10533static bool ppc_cpu_is_big_endian(CPUState *cs)
10534{
10535    PowerPCCPU *cpu = POWERPC_CPU(cs);
10536    CPUPPCState *env = &cpu->env;
10537
10538    cpu_synchronize_state(cs);
10539
10540    return !msr_le;
10541}
10542#endif
10543
10544static void ppc_cpu_initfn(Object *obj)
10545{
10546    CPUState *cs = CPU(obj);
10547    PowerPCCPU *cpu = POWERPC_CPU(obj);
10548    PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
10549    CPUPPCState *env = &cpu->env;
10550
10551    cs->env_ptr = env;
10552
10553    env->msr_mask = pcc->msr_mask;
10554    env->mmu_model = pcc->mmu_model;
10555    env->excp_model = pcc->excp_model;
10556    env->bus_model = pcc->bus_model;
10557    env->insns_flags = pcc->insns_flags;
10558    env->insns_flags2 = pcc->insns_flags2;
10559    env->flags = pcc->flags;
10560    env->bfd_mach = pcc->bfd_mach;
10561    env->check_pow = pcc->check_pow;
10562
10563    /* Mark HV mode as supported if the CPU has an MSR_HV bit
10564     * in the msr_mask. The mask can later be cleared by PAPR
10565     * mode but the hv mode support will remain, thus enforcing
10566     * that we cannot use priv. instructions in guest in PAPR
10567     * mode. For 970 we currently simply don't set HV in msr_mask
10568     * thus simulating an "Apple mode" 970. If we ever want to
10569     * support 970 HV mode, we'll have to add a processor attribute
10570     * of some sort.
10571     */
10572#if !defined(CONFIG_USER_ONLY)
10573    env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
10574#endif
10575
10576#if defined(TARGET_PPC64)
10577    if (pcc->sps) {
10578        env->sps = *pcc->sps;
10579    } else if (env->mmu_model & POWERPC_MMU_64) {
10580        /* Use default sets of page sizes. We don't support MPSS */
10581        static const struct ppc_segment_page_sizes defsps_4k = {
10582            .sps = {
10583                { .page_shift = 12, /* 4K */
10584                  .slb_enc = 0,
10585                  .enc = { { .page_shift = 12, .pte_enc = 0 } }
10586                },
10587                { .page_shift = 24, /* 16M */
10588                  .slb_enc = 0x100,
10589                  .enc = { { .page_shift = 24, .pte_enc = 0 } }
10590                },
10591            },
10592        };
10593        static const struct ppc_segment_page_sizes defsps_64k = {
10594            .sps = {
10595                { .page_shift = 12, /* 4K */
10596                  .slb_enc = 0,
10597                  .enc = { { .page_shift = 12, .pte_enc = 0 } }
10598                },
10599                { .page_shift = 16, /* 64K */
10600                  .slb_enc = 0x110,
10601                  .enc = { { .page_shift = 16, .pte_enc = 1 } }
10602                },
10603                { .page_shift = 24, /* 16M */
10604                  .slb_enc = 0x100,
10605                  .enc = { { .page_shift = 24, .pte_enc = 0 } }
10606                },
10607            },
10608        };
10609        env->sps = (env->mmu_model & POWERPC_MMU_64K) ? defsps_64k : defsps_4k;
10610    }
10611#endif /* defined(TARGET_PPC64) */
10612
10613    if (tcg_enabled()) {
10614        ppc_translate_init();
10615    }
10616}
10617
10618static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr)
10619{
10620    return pcc->pvr == pvr;
10621}
10622
10623static gchar *ppc_gdb_arch_name(CPUState *cs)
10624{
10625#if defined(TARGET_PPC64)
10626    return g_strdup("powerpc:common64");
10627#else
10628    return g_strdup("powerpc:common");
10629#endif
10630}
10631
10632static Property ppc_cpu_properties[] = {
10633    DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false),
10634    DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration,
10635                     false),
10636    DEFINE_PROP_END_OF_LIST(),
10637};
10638
10639static void ppc_cpu_class_init(ObjectClass *oc, void *data)
10640{
10641    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10642    CPUClass *cc = CPU_CLASS(oc);
10643    DeviceClass *dc = DEVICE_CLASS(oc);
10644
10645    pcc->parent_realize = dc->realize;
10646    pcc->parent_unrealize = dc->unrealize;
10647    pcc->pvr_match = ppc_pvr_match_default;
10648    pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always;
10649    dc->realize = ppc_cpu_realizefn;
10650    dc->unrealize = ppc_cpu_unrealizefn;
10651    dc->props = ppc_cpu_properties;
10652
10653    pcc->parent_reset = cc->reset;
10654    cc->reset = ppc_cpu_reset;
10655
10656    cc->class_by_name = ppc_cpu_class_by_name;
10657    cc->has_work = ppc_cpu_has_work;
10658    cc->do_interrupt = ppc_cpu_do_interrupt;
10659    cc->cpu_exec_interrupt = ppc_cpu_exec_interrupt;
10660    cc->dump_state = ppc_cpu_dump_state;
10661    cc->dump_statistics = ppc_cpu_dump_statistics;
10662    cc->set_pc = ppc_cpu_set_pc;
10663    cc->gdb_read_register = ppc_cpu_gdb_read_register;
10664    cc->gdb_write_register = ppc_cpu_gdb_write_register;
10665#ifdef CONFIG_USER_ONLY
10666    cc->handle_mmu_fault = ppc_cpu_handle_mmu_fault;
10667#else
10668    cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
10669    cc->vmsd = &vmstate_ppc_cpu;
10670#endif
10671#if defined(CONFIG_SOFTMMU)
10672    cc->write_elf64_note = ppc64_cpu_write_elf64_note;
10673    cc->write_elf32_note = ppc32_cpu_write_elf32_note;
10674#endif
10675
10676    cc->gdb_num_core_regs = 71;
10677
10678#ifdef USE_APPLE_GDB
10679    cc->gdb_read_register = ppc_cpu_gdb_read_register_apple;
10680    cc->gdb_write_register = ppc_cpu_gdb_write_register_apple;
10681    cc->gdb_num_core_regs = 71 + 32;
10682#endif
10683
10684    cc->gdb_arch_name = ppc_gdb_arch_name;
10685#if defined(TARGET_PPC64)
10686    cc->gdb_core_xml_file = "power64-core.xml";
10687#else
10688    cc->gdb_core_xml_file = "power-core.xml";
10689#endif
10690#ifndef CONFIG_USER_ONLY
10691    cc->virtio_is_big_endian = ppc_cpu_is_big_endian;
10692#endif
10693
10694    dc->fw_name = "PowerPC,UNKNOWN";
10695}
10696
10697static const TypeInfo ppc_cpu_type_info = {
10698    .name = TYPE_POWERPC_CPU,
10699    .parent = TYPE_CPU,
10700    .instance_size = sizeof(PowerPCCPU),
10701    .instance_init = ppc_cpu_initfn,
10702    .abstract = true,
10703    .class_size = sizeof(PowerPCCPUClass),
10704    .class_init = ppc_cpu_class_init,
10705};
10706
10707static const TypeInfo ppc_vhyp_type_info = {
10708    .name = TYPE_PPC_VIRTUAL_HYPERVISOR,
10709    .parent = TYPE_INTERFACE,
10710    .class_size = sizeof(PPCVirtualHypervisorClass),
10711};
10712
10713static void ppc_cpu_register_types(void)
10714{
10715    type_register_static(&ppc_cpu_type_info);
10716    type_register_static(&ppc_vhyp_type_info);
10717}
10718
10719type_init(ppc_cpu_register_types)
10720