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22#include "qemu/osdep.h"
23#include "qapi/error.h"
24#include "cpu.h"
25#include "qemu-common.h"
26#include "migration/vmstate.h"
27#include "exec/exec-all.h"
28
29
30static void superh_cpu_set_pc(CPUState *cs, vaddr value)
31{
32 SuperHCPU *cpu = SUPERH_CPU(cs);
33
34 cpu->env.pc = value;
35}
36
37static void superh_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
38{
39 SuperHCPU *cpu = SUPERH_CPU(cs);
40
41 cpu->env.pc = tb->pc;
42 cpu->env.flags = tb->flags & TB_FLAG_ENVFLAGS_MASK;
43}
44
45static bool superh_cpu_has_work(CPUState *cs)
46{
47 return cs->interrupt_request & CPU_INTERRUPT_HARD;
48}
49
50
51static void superh_cpu_reset(CPUState *s)
52{
53 SuperHCPU *cpu = SUPERH_CPU(s);
54 SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu);
55 CPUSH4State *env = &cpu->env;
56
57 scc->parent_reset(s);
58
59 memset(env, 0, offsetof(CPUSH4State, end_reset_fields));
60
61 env->pc = 0xA0000000;
62#if defined(CONFIG_USER_ONLY)
63 env->fpscr = FPSCR_PR;
64 set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
65#else
66 env->sr = (1u << SR_MD) | (1u << SR_RB) | (1u << SR_BL) |
67 (1u << SR_I3) | (1u << SR_I2) | (1u << SR_I1) | (1u << SR_I0);
68 env->fpscr = FPSCR_DN | FPSCR_RM_ZERO;
69 set_float_rounding_mode(float_round_to_zero, &env->fp_status);
70 set_flush_to_zero(1, &env->fp_status);
71#endif
72 set_default_nan_mode(1, &env->fp_status);
73 set_snan_bit_is_one(1, &env->fp_status);
74}
75
76static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
77{
78 info->mach = bfd_mach_sh4;
79 info->print_insn = print_insn_sh;
80}
81
82typedef struct SuperHCPUListState {
83 fprintf_function cpu_fprintf;
84 FILE *file;
85} SuperHCPUListState;
86
87
88static gint superh_cpu_list_compare(gconstpointer a, gconstpointer b)
89{
90 ObjectClass *class_a = (ObjectClass *)a;
91 ObjectClass *class_b = (ObjectClass *)b;
92 const char *name_a, *name_b;
93
94 name_a = object_class_get_name(class_a);
95 name_b = object_class_get_name(class_b);
96 return strcmp(name_a, name_b);
97}
98
99static void superh_cpu_list_entry(gpointer data, gpointer user_data)
100{
101 ObjectClass *oc = data;
102 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
103 SuperHCPUListState *s = user_data;
104
105 (*s->cpu_fprintf)(s->file, "%s\n",
106 scc->name);
107}
108
109void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf)
110{
111 SuperHCPUListState s = {
112 .cpu_fprintf = cpu_fprintf,
113 .file = f,
114 };
115 GSList *list;
116
117 list = object_class_get_list(TYPE_SUPERH_CPU, false);
118 list = g_slist_sort(list, superh_cpu_list_compare);
119 g_slist_foreach(list, superh_cpu_list_entry, &s);
120 g_slist_free(list);
121}
122
123static gint superh_cpu_name_compare(gconstpointer a, gconstpointer b)
124{
125 const SuperHCPUClass *scc = SUPERH_CPU_CLASS(a);
126 const char *name = b;
127
128 return strcasecmp(scc->name, name);
129}
130
131static ObjectClass *superh_cpu_class_by_name(const char *cpu_model)
132{
133 ObjectClass *oc;
134 GSList *list, *item;
135
136 if (cpu_model == NULL) {
137 return NULL;
138 }
139 if (strcasecmp(cpu_model, "any") == 0) {
140 return object_class_by_name(TYPE_SH7750R_CPU);
141 }
142
143 oc = object_class_by_name(cpu_model);
144 if (oc != NULL && object_class_dynamic_cast(oc, TYPE_SUPERH_CPU) != NULL
145 && !object_class_is_abstract(oc)) {
146 return oc;
147 }
148
149 oc = NULL;
150 list = object_class_get_list(TYPE_SUPERH_CPU, false);
151 item = g_slist_find_custom(list, cpu_model, superh_cpu_name_compare);
152 if (item != NULL) {
153 oc = item->data;
154 }
155 g_slist_free(list);
156 return oc;
157}
158
159SuperHCPU *cpu_sh4_init(const char *cpu_model)
160{
161 return SUPERH_CPU(cpu_generic_init(TYPE_SUPERH_CPU, cpu_model));
162}
163
164static void sh7750r_cpu_initfn(Object *obj)
165{
166 SuperHCPU *cpu = SUPERH_CPU(obj);
167 CPUSH4State *env = &cpu->env;
168
169 env->id = SH_CPU_SH7750R;
170 env->features = SH_FEATURE_BCR3_AND_BCR4;
171}
172
173static void sh7750r_class_init(ObjectClass *oc, void *data)
174{
175 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
176
177 scc->name = "SH7750R";
178 scc->pvr = 0x00050000;
179 scc->prr = 0x00000100;
180 scc->cvr = 0x00110000;
181}
182
183static const TypeInfo sh7750r_type_info = {
184 .name = TYPE_SH7750R_CPU,
185 .parent = TYPE_SUPERH_CPU,
186 .class_init = sh7750r_class_init,
187 .instance_init = sh7750r_cpu_initfn,
188};
189
190static void sh7751r_cpu_initfn(Object *obj)
191{
192 SuperHCPU *cpu = SUPERH_CPU(obj);
193 CPUSH4State *env = &cpu->env;
194
195 env->id = SH_CPU_SH7751R;
196 env->features = SH_FEATURE_BCR3_AND_BCR4;
197}
198
199static void sh7751r_class_init(ObjectClass *oc, void *data)
200{
201 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
202
203 scc->name = "SH7751R";
204 scc->pvr = 0x04050005;
205 scc->prr = 0x00000113;
206 scc->cvr = 0x00110000;
207}
208
209static const TypeInfo sh7751r_type_info = {
210 .name = TYPE_SH7751R_CPU,
211 .parent = TYPE_SUPERH_CPU,
212 .class_init = sh7751r_class_init,
213 .instance_init = sh7751r_cpu_initfn,
214};
215
216static void sh7785_cpu_initfn(Object *obj)
217{
218 SuperHCPU *cpu = SUPERH_CPU(obj);
219 CPUSH4State *env = &cpu->env;
220
221 env->id = SH_CPU_SH7785;
222 env->features = SH_FEATURE_SH4A;
223}
224
225static void sh7785_class_init(ObjectClass *oc, void *data)
226{
227 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
228
229 scc->name = "SH7785";
230 scc->pvr = 0x10300700;
231 scc->prr = 0x00000200;
232 scc->cvr = 0x71440211;
233}
234
235static const TypeInfo sh7785_type_info = {
236 .name = TYPE_SH7785_CPU,
237 .parent = TYPE_SUPERH_CPU,
238 .class_init = sh7785_class_init,
239 .instance_init = sh7785_cpu_initfn,
240};
241
242static void superh_cpu_realizefn(DeviceState *dev, Error **errp)
243{
244 CPUState *cs = CPU(dev);
245 SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev);
246 Error *local_err = NULL;
247
248 cpu_exec_realizefn(cs, &local_err);
249 if (local_err != NULL) {
250 error_propagate(errp, local_err);
251 return;
252 }
253
254 cpu_reset(cs);
255 qemu_init_vcpu(cs);
256
257 scc->parent_realize(dev, errp);
258}
259
260static void superh_cpu_initfn(Object *obj)
261{
262 CPUState *cs = CPU(obj);
263 SuperHCPU *cpu = SUPERH_CPU(obj);
264 CPUSH4State *env = &cpu->env;
265
266 cs->env_ptr = env;
267
268 env->movcal_backup_tail = &(env->movcal_backup);
269
270 if (tcg_enabled()) {
271 sh4_translate_init();
272 }
273}
274
275static const VMStateDescription vmstate_sh_cpu = {
276 .name = "cpu",
277 .unmigratable = 1,
278};
279
280static void superh_cpu_class_init(ObjectClass *oc, void *data)
281{
282 DeviceClass *dc = DEVICE_CLASS(oc);
283 CPUClass *cc = CPU_CLASS(oc);
284 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
285
286 scc->parent_realize = dc->realize;
287 dc->realize = superh_cpu_realizefn;
288
289 scc->parent_reset = cc->reset;
290 cc->reset = superh_cpu_reset;
291
292 cc->class_by_name = superh_cpu_class_by_name;
293 cc->has_work = superh_cpu_has_work;
294 cc->do_interrupt = superh_cpu_do_interrupt;
295 cc->cpu_exec_interrupt = superh_cpu_exec_interrupt;
296 cc->dump_state = superh_cpu_dump_state;
297 cc->set_pc = superh_cpu_set_pc;
298 cc->synchronize_from_tb = superh_cpu_synchronize_from_tb;
299 cc->gdb_read_register = superh_cpu_gdb_read_register;
300 cc->gdb_write_register = superh_cpu_gdb_write_register;
301#ifdef CONFIG_USER_ONLY
302 cc->handle_mmu_fault = superh_cpu_handle_mmu_fault;
303#else
304 cc->do_unaligned_access = superh_cpu_do_unaligned_access;
305 cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
306#endif
307 cc->disas_set_info = superh_cpu_disas_set_info;
308
309 cc->gdb_num_core_regs = 59;
310
311 dc->vmsd = &vmstate_sh_cpu;
312}
313
314static const TypeInfo superh_cpu_type_info = {
315 .name = TYPE_SUPERH_CPU,
316 .parent = TYPE_CPU,
317 .instance_size = sizeof(SuperHCPU),
318 .instance_init = superh_cpu_initfn,
319 .abstract = true,
320 .class_size = sizeof(SuperHCPUClass),
321 .class_init = superh_cpu_class_init,
322};
323
324static void superh_cpu_register_types(void)
325{
326 type_register_static(&superh_cpu_type_info);
327 type_register_static(&sh7750r_type_info);
328 type_register_static(&sh7751r_type_info);
329 type_register_static(&sh7785_type_info);
330}
331
332type_init(superh_cpu_register_types)
333
