LXR qemu/target/tilegx/cpu.c

   1/*
   2 * QEMU TILE-Gx CPU
   3 *
   4 *  Copyright (c) 2015 Chen Gang
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2.1 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see
  18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19 */
  20
  21#include "qemu/osdep.h"
  22#include "qapi/error.h"
  23#include "cpu.h"
  24#include "qemu-common.h"
  25#include "hw/qdev-properties.h"
  26#include "linux-user/syscall_defs.h"
  27#include "exec/exec-all.h"
  28
  29static void tilegx_cpu_dump_state(CPUState *cs, FILE *f,
  30                                  fprintf_function cpu_fprintf, int flags)
  31{
  32    static const char * const reg_names[TILEGX_R_COUNT] = {
  33         "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
  34         "r8",  "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  35        "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
  36        "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
  37        "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
  38        "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
  39        "r48", "r49", "r50", "r51",  "bp",  "tp",  "sp",  "lr"
  40    };
  41
  42    TileGXCPU *cpu = TILEGX_CPU(cs);
  43    CPUTLGState *env = &cpu->env;
  44    int i;
  45
  46    for (i = 0; i < TILEGX_R_COUNT; i++) {
  47        cpu_fprintf(f, "%-4s" TARGET_FMT_lx "%s",
  48                    reg_names[i], env->regs[i],
  49                    (i % 4) == 3 ? "\n" : " ");
  50    }
  51    cpu_fprintf(f, "PC  " TARGET_FMT_lx " CEX " TARGET_FMT_lx "\n\n",
  52                env->pc, env->spregs[TILEGX_SPR_CMPEXCH]);
  53}
  54
  55TileGXCPU *cpu_tilegx_init(const char *cpu_model)
  56{
  57    TileGXCPU *cpu;
  58
  59    cpu = TILEGX_CPU(object_new(TYPE_TILEGX_CPU));
  60
  61    object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
  62
  63    return cpu;
  64}
  65
  66static void tilegx_cpu_set_pc(CPUState *cs, vaddr value)
  67{
  68    TileGXCPU *cpu = TILEGX_CPU(cs);
  69
  70    cpu->env.pc = value;
  71}
  72
  73static bool tilegx_cpu_has_work(CPUState *cs)
  74{
  75    return true;
  76}
  77
  78static void tilegx_cpu_reset(CPUState *s)
  79{
  80    TileGXCPU *cpu = TILEGX_CPU(s);
  81    TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(cpu);
  82    CPUTLGState *env = &cpu->env;
  83
  84    tcc->parent_reset(s);
  85
  86    memset(env, 0, offsetof(CPUTLGState, end_reset_fields));
  87}
  88
  89static void tilegx_cpu_realizefn(DeviceState *dev, Error **errp)
  90{
  91    CPUState *cs = CPU(dev);
  92    TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(dev);
  93    Error *local_err = NULL;
  94
  95    cpu_exec_realizefn(cs, &local_err);
  96    if (local_err != NULL) {
  97        error_propagate(errp, local_err);
  98        return;
  99    }
 100
 101    cpu_reset(cs);
 102    qemu_init_vcpu(cs);
 103
 104    tcc->parent_realize(dev, errp);
 105}
 106
 107static void tilegx_cpu_initfn(Object *obj)
 108{
 109    CPUState *cs = CPU(obj);
 110    TileGXCPU *cpu = TILEGX_CPU(obj);
 111    CPUTLGState *env = &cpu->env;
 112    static bool tcg_initialized;
 113
 114    cs->env_ptr = env;
 115
 116    if (tcg_enabled() && !tcg_initialized) {
 117        tcg_initialized = true;
 118        tilegx_tcg_init();
 119    }
 120}
 121
 122static void tilegx_cpu_do_interrupt(CPUState *cs)
 123{
 124    cs->exception_index = -1;
 125}
 126
 127static int tilegx_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
 128                                       int mmu_idx)
 129{
 130    TileGXCPU *cpu = TILEGX_CPU(cs);
 131
 132    /* The sigcode field will be filled in by do_signal in main.c.  */
 133    cs->exception_index = TILEGX_EXCP_SIGNAL;
 134    cpu->env.excaddr = address;
 135    cpu->env.signo = TARGET_SIGSEGV;
 136    cpu->env.sigcode = 0;
 137
 138    return 1;
 139}
 140
 141static bool tilegx_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 142{
 143    if (interrupt_request & CPU_INTERRUPT_HARD) {
 144        tilegx_cpu_do_interrupt(cs);
 145        return true;
 146    }
 147    return false;
 148}
 149
 150static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
 151{
 152    DeviceClass *dc = DEVICE_CLASS(oc);
 153    CPUClass *cc = CPU_CLASS(oc);
 154    TileGXCPUClass *tcc = TILEGX_CPU_CLASS(oc);
 155
 156    tcc->parent_realize = dc->realize;
 157    dc->realize = tilegx_cpu_realizefn;
 158
 159    tcc->parent_reset = cc->reset;
 160    cc->reset = tilegx_cpu_reset;
 161
 162    cc->has_work = tilegx_cpu_has_work;
 163    cc->do_interrupt = tilegx_cpu_do_interrupt;
 164    cc->cpu_exec_interrupt = tilegx_cpu_exec_interrupt;
 165    cc->dump_state = tilegx_cpu_dump_state;
 166    cc->set_pc = tilegx_cpu_set_pc;
 167    cc->handle_mmu_fault = tilegx_cpu_handle_mmu_fault;
 168    cc->gdb_num_core_regs = 0;
 169}
 170
 171static const TypeInfo tilegx_cpu_type_info = {
 172    .name = TYPE_TILEGX_CPU,
 173    .parent = TYPE_CPU,
 174    .instance_size = sizeof(TileGXCPU),
 175    .instance_init = tilegx_cpu_initfn,
 176    .class_size = sizeof(TileGXCPUClass),
 177    .class_init = tilegx_cpu_class_init,
 178};
 179
 180static void tilegx_cpu_register_types(void)
 181{
 182    type_register_static(&tilegx_cpu_type_info);
 183}
 184
 185type_init(tilegx_cpu_register_types)
 186