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31#include "qemu/osdep.h"
32#include "qapi/error.h"
33#include "cpu.h"
34#include "qemu-common.h"
35#include "migration/vmstate.h"
36#include "exec/exec-all.h"
37
38
39static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
40{
41 XtensaCPU *cpu = XTENSA_CPU(cs);
42
43 cpu->env.pc = value;
44}
45
46static bool xtensa_cpu_has_work(CPUState *cs)
47{
48 XtensaCPU *cpu = XTENSA_CPU(cs);
49
50 return !cpu->env.runstall && cpu->env.pending_irq_level;
51}
52
53
54static void xtensa_cpu_reset(CPUState *s)
55{
56 XtensaCPU *cpu = XTENSA_CPU(s);
57 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu);
58 CPUXtensaState *env = &cpu->env;
59
60 xcc->parent_reset(s);
61
62 env->exception_taken = 0;
63 env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors];
64 env->sregs[LITBASE] &= ~1;
65 env->sregs[PS] = xtensa_option_enabled(env->config,
66 XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10;
67 env->sregs[VECBASE] = env->config->vecbase;
68 env->sregs[IBREAKENABLE] = 0;
69 env->sregs[MEMCTL] = MEMCTL_IL0EN & env->config->memctl_mask;
70 env->sregs[CACHEATTR] = 0x22222222;
71 env->sregs[ATOMCTL] = xtensa_option_enabled(env->config,
72 XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15;
73 env->sregs[CONFIGID0] = env->config->configid[0];
74 env->sregs[CONFIGID1] = env->config->configid[1];
75
76 env->pending_irq_level = 0;
77 reset_mmu(env);
78 s->halted = env->runstall;
79}
80
81static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model)
82{
83 ObjectClass *oc;
84 char *typename;
85
86 if (cpu_model == NULL) {
87 return NULL;
88 }
89
90 typename = g_strdup_printf("%s-" TYPE_XTENSA_CPU, cpu_model);
91 oc = object_class_by_name(typename);
92 g_free(typename);
93 if (oc == NULL || !object_class_dynamic_cast(oc, TYPE_XTENSA_CPU) ||
94 object_class_is_abstract(oc)) {
95 return NULL;
96 }
97 return oc;
98}
99
100static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
101{
102 CPUState *cs = CPU(dev);
103 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev);
104 Error *local_err = NULL;
105
106 cpu_exec_realizefn(cs, &local_err);
107 if (local_err != NULL) {
108 error_propagate(errp, local_err);
109 return;
110 }
111
112 cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs;
113
114 qemu_init_vcpu(cs);
115
116 xcc->parent_realize(dev, errp);
117}
118
119static void xtensa_cpu_initfn(Object *obj)
120{
121 CPUState *cs = CPU(obj);
122 XtensaCPU *cpu = XTENSA_CPU(obj);
123 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj);
124 CPUXtensaState *env = &cpu->env;
125 static bool tcg_inited;
126
127 cs->env_ptr = env;
128 env->config = xcc->config;
129
130 env->address_space_er = g_malloc(sizeof(*env->address_space_er));
131 env->system_er = g_malloc(sizeof(*env->system_er));
132 memory_region_init_io(env->system_er, NULL, NULL, env, "er",
133 UINT64_C(0x100000000));
134 address_space_init(env->address_space_er, env->system_er, "ER");
135
136 if (tcg_enabled() && !tcg_inited) {
137 tcg_inited = true;
138 xtensa_translate_init();
139 }
140}
141
142static const VMStateDescription vmstate_xtensa_cpu = {
143 .name = "cpu",
144 .unmigratable = 1,
145};
146
147static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
148{
149 DeviceClass *dc = DEVICE_CLASS(oc);
150 CPUClass *cc = CPU_CLASS(oc);
151 XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc);
152
153 xcc->parent_realize = dc->realize;
154 dc->realize = xtensa_cpu_realizefn;
155
156 xcc->parent_reset = cc->reset;
157 cc->reset = xtensa_cpu_reset;
158
159 cc->class_by_name = xtensa_cpu_class_by_name;
160 cc->has_work = xtensa_cpu_has_work;
161 cc->do_interrupt = xtensa_cpu_do_interrupt;
162 cc->cpu_exec_interrupt = xtensa_cpu_exec_interrupt;
163 cc->dump_state = xtensa_cpu_dump_state;
164 cc->set_pc = xtensa_cpu_set_pc;
165 cc->gdb_read_register = xtensa_cpu_gdb_read_register;
166 cc->gdb_write_register = xtensa_cpu_gdb_write_register;
167 cc->gdb_stop_before_watchpoint = true;
168#ifndef CONFIG_USER_ONLY
169 cc->do_unaligned_access = xtensa_cpu_do_unaligned_access;
170 cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
171 cc->do_unassigned_access = xtensa_cpu_do_unassigned_access;
172#endif
173 cc->debug_excp_handler = xtensa_breakpoint_handler;
174 dc->vmsd = &vmstate_xtensa_cpu;
175}
176
177static const TypeInfo xtensa_cpu_type_info = {
178 .name = TYPE_XTENSA_CPU,
179 .parent = TYPE_CPU,
180 .instance_size = sizeof(XtensaCPU),
181 .instance_init = xtensa_cpu_initfn,
182 .abstract = true,
183 .class_size = sizeof(XtensaCPUClass),
184 .class_init = xtensa_cpu_class_init,
185};
186
187static void xtensa_cpu_register_types(void)
188{
189 type_register_static(&xtensa_cpu_type_info);
190}
191
192type_init(xtensa_cpu_register_types)
193