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24#include "qemu/osdep.h"
25#include "qapi/error.h"
26#include "qemu-common.h"
27#include "cpu.h"
28#include "hw/hw.h"
29#include "hw/pci/pci.h"
30#include "hw/pci-host/apb.h"
31#include "hw/i386/pc.h"
32#include "hw/char/serial.h"
33#include "hw/timer/m48t59.h"
34#include "hw/block/fdc.h"
35#include "net/net.h"
36#include "qemu/timer.h"
37#include "sysemu/sysemu.h"
38#include "hw/boards.h"
39#include "hw/nvram/sun_nvram.h"
40#include "hw/nvram/chrp_nvram.h"
41#include "hw/sparc/sparc64.h"
42#include "hw/nvram/fw_cfg.h"
43#include "hw/sysbus.h"
44#include "hw/ide.h"
45#include "hw/loader.h"
46#include "elf.h"
47#include "qemu/cutils.h"
48
49
50
51#ifdef DEBUG_EBUS
52#define EBUS_DPRINTF(fmt, ...) \
53 do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0)
54#else
55#define EBUS_DPRINTF(fmt, ...)
56#endif
57
58#define KERNEL_LOAD_ADDR 0x00404000
59#define CMDLINE_ADDR 0x003ff000
60#define PROM_SIZE_MAX (4 * 1024 * 1024)
61#define PROM_VADDR 0x000ffd00000ULL
62#define APB_SPECIAL_BASE 0x1fe00000000ULL
63#define APB_MEM_BASE 0x1ff00000000ULL
64#define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL)
65#define PROM_FILENAME "openbios-sparc64"
66#define NVRAM_SIZE 0x2000
67#define MAX_IDE_BUS 2
68#define BIOS_CFG_IOPORT 0x510
69#define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
70#define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
71#define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
72
73#define IVEC_MAX 0x40
74
75struct hwdef {
76 const char * const default_cpu_model;
77 uint16_t machine_id;
78 uint64_t prom_addr;
79 uint64_t console_serial_base;
80};
81
82typedef struct EbusState {
83 PCIDevice pci_dev;
84 MemoryRegion bar0;
85 MemoryRegion bar1;
86} EbusState;
87
88void DMA_init(ISABus *bus, int high_page_enable)
89{
90}
91
92static void fw_cfg_boot_set(void *opaque, const char *boot_device,
93 Error **errp)
94{
95 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
96}
97
98static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size,
99 const char *arch, ram_addr_t RAM_size,
100 const char *boot_devices,
101 uint32_t kernel_image, uint32_t kernel_size,
102 const char *cmdline,
103 uint32_t initrd_image, uint32_t initrd_size,
104 uint32_t NVRAM_image,
105 int width, int height, int depth,
106 const uint8_t *macaddr)
107{
108 unsigned int i;
109 int sysp_end;
110 uint8_t image[0x1ff0];
111 NvramClass *k = NVRAM_GET_CLASS(nvram);
112
113 memset(image, '\0', sizeof(image));
114
115
116 sysp_end = chrp_nvram_create_system_partition(image, 0);
117
118
119 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
120
121 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
122
123 for (i = 0; i < sizeof(image); i++) {
124 (k->write)(nvram, i, image[i]);
125 }
126
127 return 0;
128}
129
130static uint64_t sun4u_load_kernel(const char *kernel_filename,
131 const char *initrd_filename,
132 ram_addr_t RAM_size, uint64_t *initrd_size,
133 uint64_t *initrd_addr, uint64_t *kernel_addr,
134 uint64_t *kernel_entry)
135{
136 int linux_boot;
137 unsigned int i;
138 long kernel_size;
139 uint8_t *ptr;
140 uint64_t kernel_top;
141
142 linux_boot = (kernel_filename != NULL);
143
144 kernel_size = 0;
145 if (linux_boot) {
146 int bswap_needed;
147
148#ifdef BSWAP_NEEDED
149 bswap_needed = 1;
150#else
151 bswap_needed = 0;
152#endif
153 kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry,
154 kernel_addr, &kernel_top, 1, EM_SPARCV9, 0, 0);
155 if (kernel_size < 0) {
156 *kernel_addr = KERNEL_LOAD_ADDR;
157 *kernel_entry = KERNEL_LOAD_ADDR;
158 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
159 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
160 TARGET_PAGE_SIZE);
161 }
162 if (kernel_size < 0) {
163 kernel_size = load_image_targphys(kernel_filename,
164 KERNEL_LOAD_ADDR,
165 RAM_size - KERNEL_LOAD_ADDR);
166 }
167 if (kernel_size < 0) {
168 fprintf(stderr, "qemu: could not load kernel '%s'\n",
169 kernel_filename);
170 exit(1);
171 }
172
173 *initrd_size = 0;
174 if (initrd_filename) {
175 *initrd_addr = TARGET_PAGE_ALIGN(kernel_top);
176
177 *initrd_size = load_image_targphys(initrd_filename,
178 *initrd_addr,
179 RAM_size - *initrd_addr);
180 if ((int)*initrd_size < 0) {
181 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
182 initrd_filename);
183 exit(1);
184 }
185 }
186 if (*initrd_size > 0) {
187 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
188 ptr = rom_ptr(*kernel_addr + i);
189 if (ldl_p(ptr + 8) == 0x48647253) {
190 stl_p(ptr + 24, *initrd_addr + *kernel_addr);
191 stl_p(ptr + 28, *initrd_size);
192 break;
193 }
194 }
195 }
196 }
197 return kernel_size;
198}
199
200typedef struct ResetData {
201 SPARCCPU *cpu;
202 uint64_t prom_addr;
203} ResetData;
204
205static void isa_irq_handler(void *opaque, int n, int level)
206{
207 static const int isa_irq_to_ivec[16] = {
208 [1] = 0x29,
209 [4] = 0x2b,
210 [6] = 0x27,
211 [7] = 0x22,
212 [12] = 0x2a,
213 };
214 qemu_irq *irqs = opaque;
215 int ivec;
216
217 assert(n < ARRAY_SIZE(isa_irq_to_ivec));
218 ivec = isa_irq_to_ivec[n];
219 EBUS_DPRINTF("Set ISA IRQ %d level %d -> ivec 0x%x\n", n, level, ivec);
220 if (ivec) {
221 qemu_set_irq(irqs[ivec], level);
222 }
223}
224
225
226static ISABus *
227pci_ebus_init(PCIBus *bus, int devfn, qemu_irq *irqs)
228{
229 qemu_irq *isa_irq;
230 PCIDevice *pci_dev;
231 ISABus *isa_bus;
232
233 pci_dev = pci_create_simple(bus, devfn, "ebus");
234 isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0"));
235 isa_irq = qemu_allocate_irqs(isa_irq_handler, irqs, 16);
236 isa_bus_irqs(isa_bus, isa_irq);
237 return isa_bus;
238}
239
240static void pci_ebus_realize(PCIDevice *pci_dev, Error **errp)
241{
242 EbusState *s = DO_UPCAST(EbusState, pci_dev, pci_dev);
243
244 if (!isa_bus_new(DEVICE(pci_dev), get_system_memory(),
245 pci_address_space_io(pci_dev), errp)) {
246 return;
247 }
248
249 pci_dev->config[0x04] = 0x06;
250 pci_dev->config[0x05] = 0x00;
251 pci_dev->config[0x06] = 0xa0;
252 pci_dev->config[0x07] = 0x03;
253 pci_dev->config[0x09] = 0x00;
254 pci_dev->config[0x0D] = 0x0a;
255
256 memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(),
257 0, 0x1000000);
258 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
259 memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(),
260 0, 0x4000);
261 pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1);
262}
263
264static void ebus_class_init(ObjectClass *klass, void *data)
265{
266 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
267
268 k->realize = pci_ebus_realize;
269 k->vendor_id = PCI_VENDOR_ID_SUN;
270 k->device_id = PCI_DEVICE_ID_SUN_EBUS;
271 k->revision = 0x01;
272 k->class_id = PCI_CLASS_BRIDGE_OTHER;
273}
274
275static const TypeInfo ebus_info = {
276 .name = "ebus",
277 .parent = TYPE_PCI_DEVICE,
278 .instance_size = sizeof(EbusState),
279 .class_init = ebus_class_init,
280};
281
282#define TYPE_OPENPROM "openprom"
283#define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
284
285typedef struct PROMState {
286 SysBusDevice parent_obj;
287
288 MemoryRegion prom;
289} PROMState;
290
291static uint64_t translate_prom_address(void *opaque, uint64_t addr)
292{
293 hwaddr *base_addr = (hwaddr *)opaque;
294 return addr + *base_addr - PROM_VADDR;
295}
296
297
298static void prom_init(hwaddr addr, const char *bios_name)
299{
300 DeviceState *dev;
301 SysBusDevice *s;
302 char *filename;
303 int ret;
304
305 dev = qdev_create(NULL, TYPE_OPENPROM);
306 qdev_init_nofail(dev);
307 s = SYS_BUS_DEVICE(dev);
308
309 sysbus_mmio_map(s, 0, addr);
310
311
312 if (bios_name == NULL) {
313 bios_name = PROM_FILENAME;
314 }
315 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
316 if (filename) {
317 ret = load_elf(filename, translate_prom_address, &addr,
318 NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0);
319 if (ret < 0 || ret > PROM_SIZE_MAX) {
320 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
321 }
322 g_free(filename);
323 } else {
324 ret = -1;
325 }
326 if (ret < 0 || ret > PROM_SIZE_MAX) {
327 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
328 exit(1);
329 }
330}
331
332static void prom_init1(Object *obj)
333{
334 PROMState *s = OPENPROM(obj);
335 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
336
337 memory_region_init_ram_nomigrate(&s->prom, obj, "sun4u.prom", PROM_SIZE_MAX,
338 &error_fatal);
339 vmstate_register_ram_global(&s->prom);
340 memory_region_set_readonly(&s->prom, true);
341 sysbus_init_mmio(dev, &s->prom);
342}
343
344static Property prom_properties[] = {
345 {},
346};
347
348static void prom_class_init(ObjectClass *klass, void *data)
349{
350 DeviceClass *dc = DEVICE_CLASS(klass);
351
352 dc->props = prom_properties;
353}
354
355static const TypeInfo prom_info = {
356 .name = TYPE_OPENPROM,
357 .parent = TYPE_SYS_BUS_DEVICE,
358 .instance_size = sizeof(PROMState),
359 .class_init = prom_class_init,
360 .instance_init = prom_init1,
361};
362
363
364#define TYPE_SUN4U_MEMORY "memory"
365#define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY)
366
367typedef struct RamDevice {
368 SysBusDevice parent_obj;
369
370 MemoryRegion ram;
371 uint64_t size;
372} RamDevice;
373
374
375static void ram_realize(DeviceState *dev, Error **errp)
376{
377 RamDevice *d = SUN4U_RAM(dev);
378 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
379
380 memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size,
381 &error_fatal);
382 vmstate_register_ram_global(&d->ram);
383 sysbus_init_mmio(sbd, &d->ram);
384}
385
386static void ram_init(hwaddr addr, ram_addr_t RAM_size)
387{
388 DeviceState *dev;
389 SysBusDevice *s;
390 RamDevice *d;
391
392
393 dev = qdev_create(NULL, TYPE_SUN4U_MEMORY);
394 s = SYS_BUS_DEVICE(dev);
395
396 d = SUN4U_RAM(dev);
397 d->size = RAM_size;
398 qdev_init_nofail(dev);
399
400 sysbus_mmio_map(s, 0, addr);
401}
402
403static Property ram_properties[] = {
404 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
405 DEFINE_PROP_END_OF_LIST(),
406};
407
408static void ram_class_init(ObjectClass *klass, void *data)
409{
410 DeviceClass *dc = DEVICE_CLASS(klass);
411
412 dc->realize = ram_realize;
413 dc->props = ram_properties;
414}
415
416static const TypeInfo ram_info = {
417 .name = TYPE_SUN4U_MEMORY,
418 .parent = TYPE_SYS_BUS_DEVICE,
419 .instance_size = sizeof(RamDevice),
420 .class_init = ram_class_init,
421};
422
423static void sun4uv_init(MemoryRegion *address_space_mem,
424 MachineState *machine,
425 const struct hwdef *hwdef)
426{
427 SPARCCPU *cpu;
428 Nvram *nvram;
429 unsigned int i;
430 uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
431 PCIBus *pci_bus, *pci_bus2, *pci_bus3;
432 ISABus *isa_bus;
433 SysBusDevice *s;
434 qemu_irq *ivec_irqs, *pbm_irqs;
435 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
436 DriveInfo *fd[MAX_FD];
437 DeviceState *dev;
438 FWCfgState *fw_cfg;
439
440
441 cpu = sparc64_cpu_devinit(machine->cpu_model, hwdef->default_cpu_model,
442 hwdef->prom_addr);
443
444
445 ram_init(0, machine->ram_size);
446
447 prom_init(hwdef->prom_addr, bios_name);
448
449 ivec_irqs = qemu_allocate_irqs(sparc64_cpu_set_ivec_irq, cpu, IVEC_MAX);
450 pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &pci_bus2,
451 &pci_bus3, &pbm_irqs);
452 pci_vga_init(pci_bus);
453
454
455 isa_bus = pci_ebus_init(pci_bus, -1, pbm_irqs);
456
457 i = 0;
458 if (hwdef->console_serial_base) {
459 serial_mm_init(address_space_mem, hwdef->console_serial_base, 0,
460 NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN);
461 i++;
462 }
463
464 serial_hds_isa_init(isa_bus, i, MAX_SERIAL_PORTS);
465 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
466
467 for(i = 0; i < nb_nics; i++)
468 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
469
470 ide_drive_get(hd, ARRAY_SIZE(hd));
471
472 pci_cmd646_ide_init(pci_bus, hd, 1);
473
474 isa_create_simple(isa_bus, "i8042");
475
476
477 for(i = 0; i < MAX_FD; i++) {
478 fd[i] = drive_get(IF_FLOPPY, 0, i);
479 }
480 dev = DEVICE(isa_create(isa_bus, TYPE_ISA_FDC));
481 if (fd[0]) {
482 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]),
483 &error_abort);
484 }
485 if (fd[1]) {
486 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]),
487 &error_abort);
488 }
489 qdev_prop_set_uint32(dev, "dma", -1);
490 qdev_init_nofail(dev);
491
492
493 nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59);
494 s = SYS_BUS_DEVICE(nvram);
495 memory_region_add_subregion(get_system_io(), 0x2000,
496 sysbus_mmio_get_region(s, 0));
497
498 initrd_size = 0;
499 initrd_addr = 0;
500 kernel_size = sun4u_load_kernel(machine->kernel_filename,
501 machine->initrd_filename,
502 ram_size, &initrd_size, &initrd_addr,
503 &kernel_addr, &kernel_entry);
504
505 sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size,
506 machine->boot_order,
507 kernel_addr, kernel_size,
508 machine->kernel_cmdline,
509 initrd_addr, initrd_size,
510
511 0,
512 graphic_width, graphic_height, graphic_depth,
513 (uint8_t *)&nd_table[0].macaddr);
514
515 fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT);
516 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
517 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
518 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
519 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
520 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry);
521 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
522 if (machine->kernel_cmdline) {
523 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
524 strlen(machine->kernel_cmdline) + 1);
525 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
526 } else {
527 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
528 }
529 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
530 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
531 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
532
533 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
534 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
535 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
536
537 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
538}
539
540enum {
541 sun4u_id = 0,
542 sun4v_id = 64,
543};
544
545static const struct hwdef hwdefs[] = {
546
547 {
548 .default_cpu_model = "TI UltraSparc IIi",
549 .machine_id = sun4u_id,
550 .prom_addr = 0x1fff0000000ULL,
551 .console_serial_base = 0,
552 },
553
554 {
555 .default_cpu_model = "Sun UltraSparc T1",
556 .machine_id = sun4v_id,
557 .prom_addr = 0x1fff0000000ULL,
558 .console_serial_base = 0,
559 },
560};
561
562
563static void sun4u_init(MachineState *machine)
564{
565 sun4uv_init(get_system_memory(), machine, &hwdefs[0]);
566}
567
568
569static void sun4v_init(MachineState *machine)
570{
571 sun4uv_init(get_system_memory(), machine, &hwdefs[1]);
572}
573
574static void sun4u_class_init(ObjectClass *oc, void *data)
575{
576 MachineClass *mc = MACHINE_CLASS(oc);
577
578 mc->desc = "Sun4u platform";
579 mc->init = sun4u_init;
580 mc->block_default_type = IF_IDE;
581 mc->max_cpus = 1;
582 mc->is_default = 1;
583 mc->default_boot_order = "c";
584}
585
586static const TypeInfo sun4u_type = {
587 .name = MACHINE_TYPE_NAME("sun4u"),
588 .parent = TYPE_MACHINE,
589 .class_init = sun4u_class_init,
590};
591
592static void sun4v_class_init(ObjectClass *oc, void *data)
593{
594 MachineClass *mc = MACHINE_CLASS(oc);
595
596 mc->desc = "Sun4v platform";
597 mc->init = sun4v_init;
598 mc->block_default_type = IF_IDE;
599 mc->max_cpus = 1;
600 mc->default_boot_order = "c";
601}
602
603static const TypeInfo sun4v_type = {
604 .name = MACHINE_TYPE_NAME("sun4v"),
605 .parent = TYPE_MACHINE,
606 .class_init = sun4v_class_init,
607};
608
609static void sun4u_register_types(void)
610{
611 type_register_static(&ebus_info);
612 type_register_static(&prom_info);
613 type_register_static(&ram_info);
614
615 type_register_static(&sun4u_type);
616 type_register_static(&sun4v_type);
617}
618
619type_init(sun4u_register_types)
620
