LXR qemu/target/m68k/cpu.h

   1/*
   2 * m68k virtual CPU header
   3 *
   4 *  Copyright (c) 2005-2007 CodeSourcery
   5 *  Written by Paul Brook
   6 *
   7 * This library is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU Lesser General Public
   9 * License as published by the Free Software Foundation; either
  10 * version 2 of the License, or (at your option) any later version.
  11 *
  12 * This library is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 * General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU Lesser General Public
  18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19 */
  20
  21#ifndef M68K_CPU_H
  22#define M68K_CPU_H
  23
  24#define TARGET_LONG_BITS 32
  25
  26#define CPUArchState struct CPUM68KState
  27
  28#include "qemu-common.h"
  29#include "exec/cpu-defs.h"
  30#include "cpu-qom.h"
  31#include "fpu/softfloat.h"
  32
  33#define OS_BYTE     0
  34#define OS_WORD     1
  35#define OS_LONG     2
  36#define OS_SINGLE   3
  37#define OS_DOUBLE   4
  38#define OS_EXTENDED 5
  39#define OS_PACKED   6
  40#define OS_UNSIZED  7
  41
  42#define MAX_QREGS 32
  43
  44#define EXCP_ACCESS         2   /* Access (MMU) error.  */
  45#define EXCP_ADDRESS        3   /* Address error.  */
  46#define EXCP_ILLEGAL        4   /* Illegal instruction.  */
  47#define EXCP_DIV0           5   /* Divide by zero */
  48#define EXCP_PRIVILEGE      8   /* Privilege violation.  */
  49#define EXCP_TRACE          9
  50#define EXCP_LINEA          10  /* Unimplemented line-A (MAC) opcode.  */
  51#define EXCP_LINEF          11  /* Unimplemented line-F (FPU) opcode.  */
  52#define EXCP_DEBUGNBP       12  /* Non-breakpoint debug interrupt.  */
  53#define EXCP_DEBEGBP        13  /* Breakpoint debug interrupt.  */
  54#define EXCP_FORMAT         14  /* RTE format error.  */
  55#define EXCP_UNINITIALIZED  15
  56#define EXCP_TRAP0          32   /* User trap #0.  */
  57#define EXCP_TRAP15         47   /* User trap #15.  */
  58#define EXCP_FP_BSUN        48 /* Branch Set on Unordered */
  59#define EXCP_FP_INEX        49 /* Inexact result */
  60#define EXCP_FP_DZ          50 /* Divide by Zero */
  61#define EXCP_FP_UNFL        51 /* Underflow */
  62#define EXCP_FP_OPERR       52 /* Operand Error */
  63#define EXCP_FP_OVFL        53 /* Overflow */
  64#define EXCP_FP_SNAN        54 /* Signaling Not-A-Number */
  65#define EXCP_FP_UNIMP       55 /* Unimplemented Data type */
  66#define EXCP_UNSUPPORTED    61
  67
  68#define EXCP_RTE            0x100
  69#define EXCP_HALT_INSN      0x101
  70
  71#define NB_MMU_MODES 2
  72#define TARGET_INSN_START_EXTRA_WORDS 1
  73
  74typedef CPU_LDoubleU FPReg;
  75
  76typedef struct CPUM68KState {
  77    uint32_t dregs[8];
  78    uint32_t aregs[8];
  79    uint32_t pc;
  80    uint32_t sr;
  81
  82    /* SSP and USP.  The current_sp is stored in aregs[7], the other here.  */
  83    int current_sp;
  84    uint32_t sp[2];
  85
  86    /* Condition flags.  */
  87    uint32_t cc_op;
  88    uint32_t cc_x; /* always 0/1 */
  89    uint32_t cc_n; /* in bit 31 (i.e. negative) */
  90    uint32_t cc_v; /* in bit 31, unused, or computed from cc_n and cc_v */
  91    uint32_t cc_c; /* either 0/1, unused, or computed from cc_n and cc_v */
  92    uint32_t cc_z; /* == 0 or unused */
  93
  94    FPReg fregs[8];
  95    FPReg fp_result;
  96    uint32_t fpcr;
  97    uint32_t fpsr;
  98    float_status fp_status;
  99
 100    uint64_t mactmp;
 101    /* EMAC Hardware deals with 48-bit values composed of one 32-bit and
 102       two 8-bit parts.  We store a single 64-bit value and
 103       rearrange/extend this when changing modes.  */
 104    uint64_t macc[4];
 105    uint32_t macsr;
 106    uint32_t mac_mask;
 107
 108    /* MMU status.  */
 109    struct {
 110        uint32_t ar;
 111    } mmu;
 112
 113    /* Control registers.  */
 114    uint32_t vbr;
 115    uint32_t mbar;
 116    uint32_t rambar0;
 117    uint32_t cacr;
 118
 119    int pending_vector;
 120    int pending_level;
 121
 122    uint32_t qregs[MAX_QREGS];
 123
 124    /* Fields up to this point are cleared by a CPU reset */
 125    struct {} end_reset_fields;
 126
 127    CPU_COMMON
 128
 129    /* Fields from here on are preserved across CPU reset. */
 130    uint32_t features;
 131} CPUM68KState;
 132
 133/**
 134 * M68kCPU:
 135 * @env: #CPUM68KState
 136 *
 137 * A Motorola 68k CPU.
 138 */
 139struct M68kCPU {
 140    /*< private >*/
 141    CPUState parent_obj;
 142    /*< public >*/
 143
 144    CPUM68KState env;
 145};
 146
 147static inline M68kCPU *m68k_env_get_cpu(CPUM68KState *env)
 148{
 149    return container_of(env, M68kCPU, env);
 150}
 151
 152#define ENV_GET_CPU(e) CPU(m68k_env_get_cpu(e))
 153
 154#define ENV_OFFSET offsetof(M68kCPU, env)
 155
 156void m68k_cpu_do_interrupt(CPUState *cpu);
 157bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req);
 158void m68k_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
 159                         int flags);
 160hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 161int m68k_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 162int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 163
 164void m68k_tcg_init(void);
 165void m68k_cpu_init_gdb(M68kCPU *cpu);
 166M68kCPU *cpu_m68k_init(const char *cpu_model);
 167/* you can call this signal handler from your SIGBUS and SIGSEGV
 168   signal handlers to inform the virtual CPU of exceptions. non zero
 169   is returned if the signal was handled by the virtual CPU.  */
 170int cpu_m68k_signal_handler(int host_signum, void *pinfo,
 171                           void *puc);
 172uint32_t cpu_m68k_get_ccr(CPUM68KState *env);
 173void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t);
 174void cpu_m68k_set_fpcr(CPUM68KState *env, uint32_t val);
 175
 176
 177/* Instead of computing the condition codes after each m68k instruction,
 178 * QEMU just stores one operand (called CC_SRC), the result
 179 * (called CC_DEST) and the type of operation (called CC_OP). When the
 180 * condition codes are needed, the condition codes can be calculated
 181 * using this information. Condition codes are not generated if they
 182 * are only needed for conditional branches.
 183 */
 184typedef enum {
 185    /* Translator only -- use env->cc_op.  */
 186    CC_OP_DYNAMIC = -1,
 187
 188    /* Each flag bit computed into cc_[xcnvz].  */
 189    CC_OP_FLAGS,
 190
 191    /* X in cc_x, C = X, N in cc_n, Z in cc_n, V via cc_n/cc_v.  */
 192    CC_OP_ADDB, CC_OP_ADDW, CC_OP_ADDL,
 193    CC_OP_SUBB, CC_OP_SUBW, CC_OP_SUBL,
 194
 195    /* X in cc_x, {N,Z,C,V} via cc_n/cc_v.  */
 196    CC_OP_CMPB, CC_OP_CMPW, CC_OP_CMPL,
 197
 198    /* X in cc_x, C = 0, V = 0, N in cc_n, Z in cc_n.  */
 199    CC_OP_LOGIC,
 200
 201    CC_OP_NB
 202} CCOp;
 203
 204#define CCF_C 0x01
 205#define CCF_V 0x02
 206#define CCF_Z 0x04
 207#define CCF_N 0x08
 208#define CCF_X 0x10
 209
 210#define SR_I_SHIFT 8
 211#define SR_I  0x0700
 212#define SR_M  0x1000
 213#define SR_S  0x2000
 214#define SR_T  0x8000
 215
 216#define M68K_SSP    0
 217#define M68K_USP    1
 218
 219#define M68K_FPIAR_SHIFT  0
 220#define M68K_FPIAR        (1 << M68K_FPIAR_SHIFT)
 221#define M68K_FPSR_SHIFT   1
 222#define M68K_FPSR         (1 << M68K_FPSR_SHIFT)
 223#define M68K_FPCR_SHIFT   2
 224#define M68K_FPCR         (1 << M68K_FPCR_SHIFT)
 225
 226/* Floating-Point Status Register */
 227
 228/* Condition Code */
 229#define FPSR_CC_MASK  0x0f000000
 230#define FPSR_CC_A     0x01000000 /* Not-A-Number */
 231#define FPSR_CC_I     0x02000000 /* Infinity */
 232#define FPSR_CC_Z     0x04000000 /* Zero */
 233#define FPSR_CC_N     0x08000000 /* Negative */
 234
 235/* Quotient */
 236
 237#define FPSR_QT_MASK  0x00ff0000
 238
 239/* Floating-Point Control Register */
 240/* Rounding mode */
 241#define FPCR_RND_MASK   0x0030
 242#define FPCR_RND_N      0x0000
 243#define FPCR_RND_Z      0x0010
 244#define FPCR_RND_M      0x0020
 245#define FPCR_RND_P      0x0030
 246
 247/* Rounding precision */
 248#define FPCR_PREC_MASK  0x00c0
 249#define FPCR_PREC_X     0x0000
 250#define FPCR_PREC_S     0x0040
 251#define FPCR_PREC_D     0x0080
 252#define FPCR_PREC_U     0x00c0
 253
 254#define FPCR_EXCP_MASK 0xff00
 255
 256/* CACR fields are implementation defined, but some bits are common.  */
 257#define M68K_CACR_EUSP  0x10
 258
 259#define MACSR_PAV0  0x100
 260#define MACSR_OMC   0x080
 261#define MACSR_SU    0x040
 262#define MACSR_FI    0x020
 263#define MACSR_RT    0x010
 264#define MACSR_N     0x008
 265#define MACSR_Z     0x004
 266#define MACSR_V     0x002
 267#define MACSR_EV    0x001
 268
 269void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector);
 270void m68k_switch_sp(CPUM68KState *env);
 271
 272void do_m68k_semihosting(CPUM68KState *env, int nr);
 273
 274/* There are 4 ColdFire core ISA revisions: A, A+, B and C.
 275   Each feature covers the subset of instructions common to the
 276   ISA revisions mentioned.  */
 277
 278enum m68k_features {
 279    M68K_FEATURE_M68000,
 280    M68K_FEATURE_CF_ISA_A,
 281    M68K_FEATURE_CF_ISA_B, /* (ISA B or C).  */
 282    M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C).  */
 283    M68K_FEATURE_BRAL, /* Long unconditional branch.  (ISA A+ or B).  */
 284    M68K_FEATURE_CF_FPU,
 285    M68K_FEATURE_CF_MAC,
 286    M68K_FEATURE_CF_EMAC,
 287    M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate).  */
 288    M68K_FEATURE_USP, /* User Stack Pointer.  (ISA A+, B or C).  */
 289    M68K_FEATURE_EXT_FULL, /* 68020+ full extension word.  */
 290    M68K_FEATURE_WORD_INDEX, /* word sized address index registers.  */
 291    M68K_FEATURE_SCALED_INDEX, /* scaled address index registers.  */
 292    M68K_FEATURE_LONG_MULDIV, /* 32 bit multiply/divide. */
 293    M68K_FEATURE_QUAD_MULDIV, /* 64 bit multiply/divide. */
 294    M68K_FEATURE_BCCL, /* Long conditional branches.  */
 295    M68K_FEATURE_BITFIELD, /* Bit field insns.  */
 296    M68K_FEATURE_FPU,
 297    M68K_FEATURE_CAS,
 298    M68K_FEATURE_BKPT,
 299    M68K_FEATURE_RTD,
 300};
 301
 302static inline int m68k_feature(CPUM68KState *env, int feature)
 303{
 304    return (env->features & (1u << feature)) != 0;
 305}
 306
 307void m68k_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 308
 309void register_m68k_insns (CPUM68KState *env);
 310
 311#ifdef CONFIG_USER_ONLY
 312/* Coldfire Linux uses 8k pages
 313 * and m68k linux uses 4k pages
 314 * use the smaller one
 315 */
 316#define TARGET_PAGE_BITS 12
 317#else
 318/* Smallest TLB entry size is 1k.  */
 319#define TARGET_PAGE_BITS 10
 320#endif
 321
 322#define TARGET_PHYS_ADDR_SPACE_BITS 32
 323#define TARGET_VIRT_ADDR_SPACE_BITS 32
 324
 325#define cpu_init(cpu_model) CPU(cpu_m68k_init(cpu_model))
 326
 327#define cpu_signal_handler cpu_m68k_signal_handler
 328#define cpu_list m68k_cpu_list
 329
 330/* MMU modes definitions */
 331#define MMU_MODE0_SUFFIX _kernel
 332#define MMU_MODE1_SUFFIX _user
 333#define MMU_USER_IDX 1
 334static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch)
 335{
 336    return (env->sr & SR_S) == 0 ? 1 : 0;
 337}
 338
 339int m68k_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 340                              int mmu_idx);
 341
 342#include "exec/cpu-all.h"
 343
 344static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc,
 345                                        target_ulong *cs_base, uint32_t *flags)
 346{
 347    *pc = env->pc;
 348    *cs_base = 0;
 349    *flags = (env->sr & SR_S)                   /* Bit  13 */
 350            | ((env->macsr >> 4) & 0xf);        /* Bits 0-3 */
 351}
 352
 353#endif
 354