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10#include "qemu/osdep.h"
11#include "hw/arm/armv7m.h"
12#include "qapi/error.h"
13#include "qemu-common.h"
14#include "cpu.h"
15#include "hw/sysbus.h"
16#include "hw/arm/arm.h"
17#include "hw/loader.h"
18#include "elf.h"
19#include "sysemu/qtest.h"
20#include "qemu/error-report.h"
21#include "exec/address-spaces.h"
22
23
24
25
26static inline hwaddr bitband_addr(BitBandState *s, hwaddr offset)
27{
28 return s->base | (offset & 0x1ffffff) >> 5;
29}
30
31static MemTxResult bitband_read(void *opaque, hwaddr offset,
32 uint64_t *data, unsigned size, MemTxAttrs attrs)
33{
34 BitBandState *s = opaque;
35 uint8_t buf[4];
36 MemTxResult res;
37 int bitpos, bit;
38 hwaddr addr;
39
40 assert(size <= 4);
41
42
43 addr = bitband_addr(s, offset) & (-size);
44 res = address_space_read(&s->source_as, addr, attrs, buf, size);
45 if (res) {
46 return res;
47 }
48
49 bitpos = (offset >> 2) & ((size * 8) - 1);
50
51 bit = (buf[bitpos >> 3] >> (bitpos & 7)) & 1;
52 *data = bit;
53 return MEMTX_OK;
54}
55
56static MemTxResult bitband_write(void *opaque, hwaddr offset, uint64_t value,
57 unsigned size, MemTxAttrs attrs)
58{
59 BitBandState *s = opaque;
60 uint8_t buf[4];
61 MemTxResult res;
62 int bitpos, bit;
63 hwaddr addr;
64
65 assert(size <= 4);
66
67
68 addr = bitband_addr(s, offset) & (-size);
69 res = address_space_read(&s->source_as, addr, attrs, buf, size);
70 if (res) {
71 return res;
72 }
73
74 bitpos = (offset >> 2) & ((size * 8) - 1);
75
76 bit = 1 << (bitpos & 7);
77 if (value & 1) {
78 buf[bitpos >> 3] |= bit;
79 } else {
80 buf[bitpos >> 3] &= ~bit;
81 }
82 return address_space_write(&s->source_as, addr, attrs, buf, size);
83}
84
85static const MemoryRegionOps bitband_ops = {
86 .read_with_attrs = bitband_read,
87 .write_with_attrs = bitband_write,
88 .endianness = DEVICE_NATIVE_ENDIAN,
89 .impl.min_access_size = 1,
90 .impl.max_access_size = 4,
91 .valid.min_access_size = 1,
92 .valid.max_access_size = 4,
93};
94
95static void bitband_init(Object *obj)
96{
97 BitBandState *s = BITBAND(obj);
98 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
99
100 object_property_add_link(obj, "source-memory",
101 TYPE_MEMORY_REGION,
102 (Object **)&s->source_memory,
103 qdev_prop_allow_set_link_before_realize,
104 OBJ_PROP_LINK_UNREF_ON_RELEASE,
105 &error_abort);
106 memory_region_init_io(&s->iomem, obj, &bitband_ops, s,
107 "bitband", 0x02000000);
108 sysbus_init_mmio(dev, &s->iomem);
109}
110
111static void bitband_realize(DeviceState *dev, Error **errp)
112{
113 BitBandState *s = BITBAND(dev);
114
115 if (!s->source_memory) {
116 error_setg(errp, "source-memory property not set");
117 return;
118 }
119
120 address_space_init(&s->source_as, s->source_memory, "bitband-source");
121}
122
123
124
125static const hwaddr bitband_input_addr[ARMV7M_NUM_BITBANDS] = {
126 0x20000000, 0x40000000
127};
128
129static const hwaddr bitband_output_addr[ARMV7M_NUM_BITBANDS] = {
130 0x22000000, 0x42000000
131};
132
133static void armv7m_instance_init(Object *obj)
134{
135 ARMv7MState *s = ARMV7M(obj);
136 int i;
137
138
139
140 object_property_add_link(obj, "memory",
141 TYPE_MEMORY_REGION,
142 (Object **)&s->board_memory,
143 qdev_prop_allow_set_link_before_realize,
144 OBJ_PROP_LINK_UNREF_ON_RELEASE,
145 &error_abort);
146 memory_region_init(&s->container, obj, "armv7m-container", UINT64_MAX);
147
148 object_initialize(&s->nvic, sizeof(s->nvic), "armv7m_nvic");
149 qdev_set_parent_bus(DEVICE(&s->nvic), sysbus_get_default());
150 object_property_add_alias(obj, "num-irq",
151 OBJECT(&s->nvic), "num-irq", &error_abort);
152
153 for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
154 object_initialize(&s->bitband[i], sizeof(s->bitband[i]), TYPE_BITBAND);
155 qdev_set_parent_bus(DEVICE(&s->bitband[i]), sysbus_get_default());
156 }
157}
158
159static void armv7m_realize(DeviceState *dev, Error **errp)
160{
161 ARMv7MState *s = ARMV7M(dev);
162 SysBusDevice *sbd;
163 Error *err = NULL;
164 int i;
165 char **cpustr;
166 ObjectClass *oc;
167 const char *typename;
168 CPUClass *cc;
169
170 if (!s->board_memory) {
171 error_setg(errp, "memory property was not set");
172 return;
173 }
174
175 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);
176
177 cpustr = g_strsplit(s->cpu_model, ",", 2);
178
179 oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);
180 if (!oc) {
181 error_setg(errp, "Unknown CPU model %s", cpustr[0]);
182 g_strfreev(cpustr);
183 return;
184 }
185
186 cc = CPU_CLASS(oc);
187 typename = object_class_get_name(oc);
188 cc->parse_features(typename, cpustr[1], &err);
189 g_strfreev(cpustr);
190 if (err) {
191 error_propagate(errp, err);
192 return;
193 }
194
195 s->cpu = ARM_CPU(object_new(typename));
196 if (!s->cpu) {
197 error_setg(errp, "Unknown CPU model %s", s->cpu_model);
198 return;
199 }
200
201 object_property_set_link(OBJECT(s->cpu), OBJECT(&s->container), "memory",
202 &error_abort);
203 object_property_set_bool(OBJECT(s->cpu), true, "realized", &err);
204 if (err != NULL) {
205 error_propagate(errp, err);
206 return;
207 }
208
209
210 object_property_set_bool(OBJECT(&s->nvic), true, "realized", &err);
211 if (err != NULL) {
212 error_propagate(errp, err);
213 return;
214 }
215
216
217
218
219
220 qdev_pass_gpios(DEVICE(&s->nvic), dev, NULL);
221 qdev_pass_gpios(DEVICE(&s->nvic), dev, "SYSRESETREQ");
222
223
224 sbd = SYS_BUS_DEVICE(&s->nvic);
225 sysbus_connect_irq(sbd, 0,
226 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
227 s->cpu->env.nvic = &s->nvic;
228
229 memory_region_add_subregion(&s->container, 0xe000e000,
230 sysbus_mmio_get_region(sbd, 0));
231
232 for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
233 Object *obj = OBJECT(&s->bitband[i]);
234 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->bitband[i]);
235
236 object_property_set_int(obj, bitband_input_addr[i], "base", &err);
237 if (err != NULL) {
238 error_propagate(errp, err);
239 return;
240 }
241 object_property_set_link(obj, OBJECT(s->board_memory),
242 "source-memory", &error_abort);
243 object_property_set_bool(obj, true, "realized", &err);
244 if (err != NULL) {
245 error_propagate(errp, err);
246 return;
247 }
248
249 memory_region_add_subregion(&s->container, bitband_output_addr[i],
250 sysbus_mmio_get_region(sbd, 0));
251 }
252}
253
254static Property armv7m_properties[] = {
255 DEFINE_PROP_STRING("cpu-model", ARMv7MState, cpu_model),
256 DEFINE_PROP_END_OF_LIST(),
257};
258
259static void armv7m_class_init(ObjectClass *klass, void *data)
260{
261 DeviceClass *dc = DEVICE_CLASS(klass);
262
263 dc->realize = armv7m_realize;
264 dc->props = armv7m_properties;
265}
266
267static const TypeInfo armv7m_info = {
268 .name = TYPE_ARMV7M,
269 .parent = TYPE_SYS_BUS_DEVICE,
270 .instance_size = sizeof(ARMv7MState),
271 .instance_init = armv7m_instance_init,
272 .class_init = armv7m_class_init,
273};
274
275static void armv7m_reset(void *opaque)
276{
277 ARMCPU *cpu = opaque;
278
279 cpu_reset(CPU(cpu));
280}
281
282
283
284
285
286DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,
287 const char *kernel_filename, const char *cpu_model)
288{
289 DeviceState *armv7m;
290
291 if (cpu_model == NULL) {
292 cpu_model = "cortex-m3";
293 }
294
295 armv7m = qdev_create(NULL, "armv7m");
296 qdev_prop_set_uint32(armv7m, "num-irq", num_irq);
297 qdev_prop_set_string(armv7m, "cpu-model", cpu_model);
298 object_property_set_link(OBJECT(armv7m), OBJECT(get_system_memory()),
299 "memory", &error_abort);
300
301 qdev_init_nofail(armv7m);
302
303 armv7m_load_kernel(ARM_CPU(first_cpu), kernel_filename, mem_size);
304 return armv7m;
305}
306
307void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size)
308{
309 int image_size;
310 uint64_t entry;
311 uint64_t lowaddr;
312 int big_endian;
313
314#ifdef TARGET_WORDS_BIGENDIAN
315 big_endian = 1;
316#else
317 big_endian = 0;
318#endif
319
320 if (!kernel_filename && !qtest_enabled()) {
321 fprintf(stderr, "Guest image must be specified (using -kernel)\n");
322 exit(1);
323 }
324
325 if (kernel_filename) {
326 image_size = load_elf(kernel_filename, NULL, NULL, &entry, &lowaddr,
327 NULL, big_endian, EM_ARM, 1, 0);
328 if (image_size < 0) {
329 image_size = load_image_targphys(kernel_filename, 0, mem_size);
330 lowaddr = 0;
331 }
332 if (image_size < 0) {
333 error_report("Could not load kernel '%s'", kernel_filename);
334 exit(1);
335 }
336 }
337
338
339
340
341
342
343
344
345
346 qemu_register_reset(armv7m_reset, cpu);
347}
348
349static Property bitband_properties[] = {
350 DEFINE_PROP_UINT32("base", BitBandState, base, 0),
351 DEFINE_PROP_END_OF_LIST(),
352};
353
354static void bitband_class_init(ObjectClass *klass, void *data)
355{
356 DeviceClass *dc = DEVICE_CLASS(klass);
357
358 dc->realize = bitband_realize;
359 dc->props = bitband_properties;
360}
361
362static const TypeInfo bitband_info = {
363 .name = TYPE_BITBAND,
364 .parent = TYPE_SYS_BUS_DEVICE,
365 .instance_size = sizeof(BitBandState),
366 .instance_init = bitband_init,
367 .class_init = bitband_class_init,
368};
369
370static void armv7m_register_types(void)
371{
372 type_register_static(&bitband_info);
373 type_register_static(&armv7m_info);
374}
375
376type_init(armv7m_register_types)
377