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24#include "qemu/osdep.h"
25#include "qapi/error.h"
26#include "qemu/error-report.h"
27#include "qemu-common.h"
28#include "cpu.h"
29#include "sysemu/sysemu.h"
30#include "sysemu/qtest.h"
31#include "hw/sysbus.h"
32#include "net/net.h"
33#include "hw/arm/arm.h"
34#include "exec/address-spaces.h"
35#include "hw/arm/exynos4210.h"
36#include "hw/boards.h"
37
38#undef DEBUG
39
40
41
42#ifdef DEBUG
43 #undef PRINT_DEBUG
44 #define PRINT_DEBUG(fmt, args...) \
45 do { \
46 fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \
47 } while (0)
48#else
49 #define PRINT_DEBUG(fmt, args...) do {} while (0)
50#endif
51
52#define SMDK_LAN9118_BASE_ADDR 0x05000000
53
54typedef enum Exynos4BoardType {
55 EXYNOS4_BOARD_NURI,
56 EXYNOS4_BOARD_SMDKC210,
57 EXYNOS4_NUM_OF_BOARDS
58} Exynos4BoardType;
59
60typedef struct Exynos4BoardState {
61 Exynos4210State *soc;
62 MemoryRegion dram0_mem;
63 MemoryRegion dram1_mem;
64} Exynos4BoardState;
65
66static int exynos4_board_id[EXYNOS4_NUM_OF_BOARDS] = {
67 [EXYNOS4_BOARD_NURI] = 0xD33,
68 [EXYNOS4_BOARD_SMDKC210] = 0xB16,
69};
70
71static int exynos4_board_smp_bootreg_addr[EXYNOS4_NUM_OF_BOARDS] = {
72 [EXYNOS4_BOARD_NURI] = EXYNOS4210_SECOND_CPU_BOOTREG,
73 [EXYNOS4_BOARD_SMDKC210] = EXYNOS4210_SECOND_CPU_BOOTREG,
74};
75
76static unsigned long exynos4_board_ram_size[EXYNOS4_NUM_OF_BOARDS] = {
77 [EXYNOS4_BOARD_NURI] = 0x40000000,
78 [EXYNOS4_BOARD_SMDKC210] = 0x40000000,
79};
80
81static struct arm_boot_info exynos4_board_binfo = {
82 .loader_start = EXYNOS4210_BASE_BOOT_ADDR,
83 .smp_loader_start = EXYNOS4210_SMP_BOOT_ADDR,
84 .nb_cpus = EXYNOS4210_NCPUS,
85 .write_secondary_boot = exynos4210_write_secondary,
86};
87
88static void lan9215_init(uint32_t base, qemu_irq irq)
89{
90 DeviceState *dev;
91 SysBusDevice *s;
92
93
94 if (nd_table[0].used) {
95 qemu_check_nic_model(&nd_table[0], "lan9118");
96 dev = qdev_create(NULL, "lan9118");
97 qdev_set_nic_properties(dev, &nd_table[0]);
98 qdev_prop_set_uint32(dev, "mode_16bit", 1);
99 qdev_init_nofail(dev);
100 s = SYS_BUS_DEVICE(dev);
101 sysbus_mmio_map(s, 0, base);
102 sysbus_connect_irq(s, 0, irq);
103 }
104}
105
106static void exynos4_boards_init_ram(Exynos4BoardState *s,
107 MemoryRegion *system_mem,
108 unsigned long ram_size)
109{
110 unsigned long mem_size = ram_size;
111
112 if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) {
113 memory_region_init_ram(&s->dram1_mem, NULL, "exynos4210.dram1",
114 mem_size - EXYNOS4210_DRAM_MAX_SIZE,
115 &error_fatal);
116 memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR,
117 &s->dram1_mem);
118 mem_size = EXYNOS4210_DRAM_MAX_SIZE;
119 }
120
121 memory_region_init_ram(&s->dram0_mem, NULL, "exynos4210.dram0", mem_size,
122 &error_fatal);
123 memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR,
124 &s->dram0_mem);
125}
126
127static Exynos4BoardState *
128exynos4_boards_init_common(MachineState *machine,
129 Exynos4BoardType board_type)
130{
131 Exynos4BoardState *s = g_new(Exynos4BoardState, 1);
132 MachineClass *mc = MACHINE_GET_CLASS(machine);
133
134 if (smp_cpus != EXYNOS4210_NCPUS && !qtest_enabled()) {
135 error_report("%s board supports only %d CPU cores, ignoring smp_cpus"
136 " value",
137 mc->name, EXYNOS4210_NCPUS);
138 }
139
140 exynos4_board_binfo.ram_size = exynos4_board_ram_size[board_type];
141 exynos4_board_binfo.board_id = exynos4_board_id[board_type];
142 exynos4_board_binfo.smp_bootreg_addr =
143 exynos4_board_smp_bootreg_addr[board_type];
144 exynos4_board_binfo.kernel_filename = machine->kernel_filename;
145 exynos4_board_binfo.initrd_filename = machine->initrd_filename;
146 exynos4_board_binfo.kernel_cmdline = machine->kernel_cmdline;
147 exynos4_board_binfo.gic_cpu_if_addr =
148 EXYNOS4210_SMP_PRIVATE_BASE_ADDR + 0x100;
149
150 PRINT_DEBUG("\n ram_size: %luMiB [0x%08lx]\n"
151 " kernel_filename: %s\n"
152 " kernel_cmdline: %s\n"
153 " initrd_filename: %s\n",
154 exynos4_board_ram_size[board_type] / 1048576,
155 exynos4_board_ram_size[board_type],
156 machine->kernel_filename,
157 machine->kernel_cmdline,
158 machine->initrd_filename);
159
160 exynos4_boards_init_ram(s, get_system_memory(),
161 exynos4_board_ram_size[board_type]);
162
163 s->soc = exynos4210_init(get_system_memory());
164
165 return s;
166}
167
168static void nuri_init(MachineState *machine)
169{
170 exynos4_boards_init_common(machine, EXYNOS4_BOARD_NURI);
171
172 arm_load_kernel(ARM_CPU(first_cpu), &exynos4_board_binfo);
173}
174
175static void smdkc210_init(MachineState *machine)
176{
177 Exynos4BoardState *s = exynos4_boards_init_common(machine,
178 EXYNOS4_BOARD_SMDKC210);
179
180 lan9215_init(SMDK_LAN9118_BASE_ADDR,
181 qemu_irq_invert(s->soc->irq_table[exynos4210_get_irq(37, 1)]));
182 arm_load_kernel(ARM_CPU(first_cpu), &exynos4_board_binfo);
183}
184
185static void nuri_class_init(ObjectClass *oc, void *data)
186{
187 MachineClass *mc = MACHINE_CLASS(oc);
188
189 mc->desc = "Samsung NURI board (Exynos4210)";
190 mc->init = nuri_init;
191 mc->max_cpus = EXYNOS4210_NCPUS;
192}
193
194static const TypeInfo nuri_type = {
195 .name = MACHINE_TYPE_NAME("nuri"),
196 .parent = TYPE_MACHINE,
197 .class_init = nuri_class_init,
198};
199
200static void smdkc210_class_init(ObjectClass *oc, void *data)
201{
202 MachineClass *mc = MACHINE_CLASS(oc);
203
204 mc->desc = "Samsung SMDKC210 board (Exynos4210)";
205 mc->init = smdkc210_init;
206 mc->max_cpus = EXYNOS4210_NCPUS;
207}
208
209static const TypeInfo smdkc210_type = {
210 .name = MACHINE_TYPE_NAME("smdkc210"),
211 .parent = TYPE_MACHINE,
212 .class_init = smdkc210_class_init,
213};
214
215static void exynos4_machines_init(void)
216{
217 type_register_static(&nuri_type);
218 type_register_static(&smdkc210_type);
219}
220
221type_init(exynos4_machines_init)
222
