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21#include "qemu/osdep.h"
22#include "qapi/error.h"
23#include "hw/cpu/a15mpcore.h"
24#include "sysemu/kvm.h"
25#include "kvm_arm.h"
26
27static void a15mp_priv_set_irq(void *opaque, int irq, int level)
28{
29 A15MPPrivState *s = (A15MPPrivState *)opaque;
30
31 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level);
32}
33
34static void a15mp_priv_initfn(Object *obj)
35{
36 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
37 A15MPPrivState *s = A15MPCORE_PRIV(obj);
38 DeviceState *gicdev;
39
40 memory_region_init(&s->container, obj, "a15mp-priv-container", 0x8000);
41 sysbus_init_mmio(sbd, &s->container);
42
43 object_initialize(&s->gic, sizeof(s->gic), gic_class_name());
44 gicdev = DEVICE(&s->gic);
45 qdev_set_parent_bus(gicdev, sysbus_get_default());
46 qdev_prop_set_uint32(gicdev, "revision", 2);
47}
48
49static void a15mp_priv_realize(DeviceState *dev, Error **errp)
50{
51 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
52 A15MPPrivState *s = A15MPCORE_PRIV(dev);
53 DeviceState *gicdev;
54 SysBusDevice *busdev;
55 int i;
56 Error *err = NULL;
57 bool has_el3;
58 Object *cpuobj;
59
60 gicdev = DEVICE(&s->gic);
61 qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
62 qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
63
64 if (!kvm_irqchip_in_kernel()) {
65
66
67
68 cpuobj = OBJECT(qemu_get_cpu(0));
69 has_el3 = object_property_find(cpuobj, "has_el3", NULL) &&
70 object_property_get_bool(cpuobj, "has_el3", &error_abort);
71 qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3);
72 }
73
74 object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
75 if (err != NULL) {
76 error_propagate(errp, err);
77 return;
78 }
79 busdev = SYS_BUS_DEVICE(&s->gic);
80
81
82 sysbus_pass_irq(sbd, busdev);
83
84
85 qdev_init_gpio_in(dev, a15mp_priv_set_irq, s->num_irq - 32);
86
87
88
89
90 for (i = 0; i < s->num_cpu; i++) {
91 DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
92 int ppibase = s->num_irq - 32 + i * 32;
93 int irq;
94
95
96
97 const int timer_irq[] = {
98 [GTIMER_PHYS] = 30,
99 [GTIMER_VIRT] = 27,
100 [GTIMER_HYP] = 26,
101 [GTIMER_SEC] = 29,
102 };
103 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
104 qdev_connect_gpio_out(cpudev, irq,
105 qdev_get_gpio_in(gicdev,
106 ppibase + timer_irq[irq]));
107 }
108 }
109
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117
118 memory_region_add_subregion(&s->container, 0x1000,
119 sysbus_mmio_get_region(busdev, 0));
120 memory_region_add_subregion(&s->container, 0x2000,
121 sysbus_mmio_get_region(busdev, 1));
122}
123
124static Property a15mp_priv_properties[] = {
125 DEFINE_PROP_UINT32("num-cpu", A15MPPrivState, num_cpu, 1),
126
127
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130
131
132 DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 160),
133 DEFINE_PROP_END_OF_LIST(),
134};
135
136static void a15mp_priv_class_init(ObjectClass *klass, void *data)
137{
138 DeviceClass *dc = DEVICE_CLASS(klass);
139
140 dc->realize = a15mp_priv_realize;
141 dc->props = a15mp_priv_properties;
142
143}
144
145static const TypeInfo a15mp_priv_info = {
146 .name = TYPE_A15MPCORE_PRIV,
147 .parent = TYPE_SYS_BUS_DEVICE,
148 .instance_size = sizeof(A15MPPrivState),
149 .instance_init = a15mp_priv_initfn,
150 .class_init = a15mp_priv_class_init,
151};
152
153static void a15mp_register_types(void)
154{
155 type_register_static(&a15mp_priv_info);
156}
157
158type_init(a15mp_register_types)
159