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25#include "qemu/osdep.h"
26#include "cpu.h"
27#include "hw/hw.h"
28#include "hw/timer/m48t59.h"
29#include "hw/i386/pc.h"
30#include "hw/char/serial.h"
31#include "hw/block/fdc.h"
32#include "net/net.h"
33#include "sysemu/sysemu.h"
34#include "hw/isa/isa.h"
35#include "hw/pci/pci.h"
36#include "hw/pci/pci_host.h"
37#include "hw/ppc/ppc.h"
38#include "hw/boards.h"
39#include "qemu/error-report.h"
40#include "qemu/log.h"
41#include "hw/ide.h"
42#include "hw/loader.h"
43#include "hw/timer/mc146818rtc.h"
44#include "hw/isa/pc87312.h"
45#include "sysemu/block-backend.h"
46#include "sysemu/arch_init.h"
47#include "sysemu/kvm.h"
48#include "sysemu/qtest.h"
49#include "exec/address-spaces.h"
50#include "trace.h"
51#include "elf.h"
52#include "qemu/cutils.h"
53#include "kvm_ppc.h"
54
55
56#define MAX_CPUS 1
57
58#define MAX_IDE_BUS 2
59
60#define CFG_ADDR 0xf0000510
61
62#define BIOS_SIZE (1024 * 1024)
63#define BIOS_FILENAME "ppc_rom.bin"
64#define KERNEL_LOAD_ADDR 0x01000000
65#define INITRD_LOAD_ADDR 0x01800000
66
67
68static const int ide_iobase[2] = { 0x1f0, 0x170 };
69static const int ide_iobase2[2] = { 0x3f6, 0x376 };
70static const int ide_irq[2] = { 13, 13 };
71
72#define NE2000_NB_MAX 6
73
74static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
75static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
76
77
78#define PPC_IO_BASE 0x80000000
79
80
81#if 0
82static struct {
83
84 uint32_t veni_devi;
85 uint32_t revi;
86
87 uint32_t gcsr;
88 uint32_t xcfr;
89 uint32_t ct32;
90 uint32_t mcsr;
91
92 uint32_t gprg[6];
93
94 uint32_t feen;
95 uint32_t fest;
96 uint32_t fema;
97 uint32_t fecl;
98 uint32_t eeen;
99 uint32_t eest;
100 uint32_t eecl;
101 uint32_t eeint;
102 uint32_t eemck0;
103 uint32_t eemck1;
104
105} XCSR;
106
107static void PPC_XCSR_writeb (void *opaque,
108 hwaddr addr, uint32_t value)
109{
110 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
111 value);
112}
113
114static void PPC_XCSR_writew (void *opaque,
115 hwaddr addr, uint32_t value)
116{
117 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
118 value);
119}
120
121static void PPC_XCSR_writel (void *opaque,
122 hwaddr addr, uint32_t value)
123{
124 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
125 value);
126}
127
128static uint32_t PPC_XCSR_readb (void *opaque, hwaddr addr)
129{
130 uint32_t retval = 0;
131
132 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
133 retval);
134
135 return retval;
136}
137
138static uint32_t PPC_XCSR_readw (void *opaque, hwaddr addr)
139{
140 uint32_t retval = 0;
141
142 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
143 retval);
144
145 return retval;
146}
147
148static uint32_t PPC_XCSR_readl (void *opaque, hwaddr addr)
149{
150 uint32_t retval = 0;
151
152 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
153 retval);
154
155 return retval;
156}
157
158static const MemoryRegionOps PPC_XCSR_ops = {
159 .old_mmio = {
160 .read = { PPC_XCSR_readb, PPC_XCSR_readw, PPC_XCSR_readl, },
161 .write = { PPC_XCSR_writeb, PPC_XCSR_writew, PPC_XCSR_writel, },
162 },
163 .endianness = DEVICE_LITTLE_ENDIAN,
164};
165
166#endif
167
168
169typedef struct sysctrl_t {
170 qemu_irq reset_irq;
171 Nvram *nvram;
172 uint8_t state;
173 uint8_t syscontrol;
174 int contiguous_map;
175 qemu_irq contiguous_map_irq;
176 int endian;
177} sysctrl_t;
178
179enum {
180 STATE_HARDFILE = 0x01,
181};
182
183static sysctrl_t *sysctrl;
184
185static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
186{
187 sysctrl_t *sysctrl = opaque;
188
189 trace_prep_io_800_writeb(addr - PPC_IO_BASE, val);
190 switch (addr) {
191 case 0x0092:
192
193
194 if (val & 0x01) {
195 qemu_irq_raise(sysctrl->reset_irq);
196 } else {
197 qemu_irq_lower(sysctrl->reset_irq);
198 }
199
200 if (val & 0x02) {
201 sysctrl->endian = 1;
202 } else {
203 sysctrl->endian = 0;
204 }
205 break;
206 case 0x0800:
207
208 break;
209 case 0x0802:
210
211 break;
212 case 0x0803:
213
214 break;
215 case 0x0808:
216
217 if (val & 1)
218 sysctrl->state |= STATE_HARDFILE;
219 else
220 sysctrl->state &= ~STATE_HARDFILE;
221 break;
222 case 0x0810:
223
224 if (sysctrl->nvram != NULL) {
225 NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
226 (k->toggle_lock)(sysctrl->nvram, 1);
227 }
228 break;
229 case 0x0812:
230
231 if (sysctrl->nvram != NULL) {
232 NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
233 (k->toggle_lock)(sysctrl->nvram, 2);
234 }
235 break;
236 case 0x0814:
237
238
239 break;
240 case 0x081C:
241
242 sysctrl->syscontrol = val & 0x0F;
243 break;
244 case 0x0850:
245
246 sysctrl->contiguous_map = val & 0x01;
247 qemu_set_irq(sysctrl->contiguous_map_irq, sysctrl->contiguous_map);
248 break;
249 default:
250 printf("ERROR: unaffected IO port write: %04" PRIx32
251 " => %02" PRIx32"\n", addr, val);
252 break;
253 }
254}
255
256static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
257{
258 sysctrl_t *sysctrl = opaque;
259 uint32_t retval = 0xFF;
260
261 switch (addr) {
262 case 0x0092:
263
264 retval = sysctrl->endian << 1;
265 break;
266 case 0x0800:
267
268 retval = 0xEF;
269 break;
270 case 0x0802:
271
272 retval = 0xAD;
273 break;
274 case 0x0803:
275
276 retval = 0xE0;
277 break;
278 case 0x080C:
279
280
281
282
283
284
285 retval = 0x3C;
286 break;
287 case 0x0810:
288
289 retval = 0x39;
290 break;
291 case 0x0814:
292
293 break;
294 case 0x0818:
295
296 retval = 0x00;
297 break;
298 case 0x081C:
299
300
301
302 retval = sysctrl->syscontrol;
303 break;
304 case 0x0823:
305
306 retval = 0x03;
307 break;
308 case 0x0850:
309
310 retval = sysctrl->contiguous_map;
311 break;
312 default:
313 printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
314 break;
315 }
316 trace_prep_io_800_readb(addr - PPC_IO_BASE, retval);
317
318 return retval;
319}
320
321
322#define NVRAM_SIZE 0x2000
323
324static void fw_cfg_boot_set(void *opaque, const char *boot_device,
325 Error **errp)
326{
327 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
328}
329
330static void ppc_prep_reset(void *opaque)
331{
332 PowerPCCPU *cpu = opaque;
333
334 cpu_reset(CPU(cpu));
335}
336
337static const MemoryRegionPortio prep_portio_list[] = {
338
339 { 0x0092, 1, 1, .read = PREP_io_800_readb, .write = PREP_io_800_writeb, },
340 { 0x0800, 0x52, 1,
341 .read = PREP_io_800_readb, .write = PREP_io_800_writeb, },
342
343 { 0x0F00, 4, 1, .write = PPC_debug_write, },
344 PORTIO_END_OF_LIST(),
345};
346
347static PortioList prep_port_list;
348
349
350
351static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr)
352{
353 NvramClass *k = NVRAM_GET_CLASS(nvram);
354 return (k->read)(nvram, addr);
355}
356
357static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val)
358{
359 NvramClass *k = NVRAM_GET_CLASS(nvram);
360 (k->write)(nvram, addr, val);
361}
362
363static void NVRAM_set_byte(Nvram *nvram, uint32_t addr, uint8_t value)
364{
365 nvram_write(nvram, addr, value);
366}
367
368static uint8_t NVRAM_get_byte(Nvram *nvram, uint32_t addr)
369{
370 return nvram_read(nvram, addr);
371}
372
373static void NVRAM_set_word(Nvram *nvram, uint32_t addr, uint16_t value)
374{
375 nvram_write(nvram, addr, value >> 8);
376 nvram_write(nvram, addr + 1, value & 0xFF);
377}
378
379static uint16_t NVRAM_get_word(Nvram *nvram, uint32_t addr)
380{
381 uint16_t tmp;
382
383 tmp = nvram_read(nvram, addr) << 8;
384 tmp |= nvram_read(nvram, addr + 1);
385
386 return tmp;
387}
388
389static void NVRAM_set_lword(Nvram *nvram, uint32_t addr, uint32_t value)
390{
391 nvram_write(nvram, addr, value >> 24);
392 nvram_write(nvram, addr + 1, (value >> 16) & 0xFF);
393 nvram_write(nvram, addr + 2, (value >> 8) & 0xFF);
394 nvram_write(nvram, addr + 3, value & 0xFF);
395}
396
397static void NVRAM_set_string(Nvram *nvram, uint32_t addr, const char *str,
398 uint32_t max)
399{
400 int i;
401
402 for (i = 0; i < max && str[i] != '\0'; i++) {
403 nvram_write(nvram, addr + i, str[i]);
404 }
405 nvram_write(nvram, addr + i, str[i]);
406 nvram_write(nvram, addr + max - 1, '\0');
407}
408
409static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
410{
411 uint16_t tmp;
412 uint16_t pd, pd1, pd2;
413
414 tmp = prev >> 8;
415 pd = prev ^ value;
416 pd1 = pd & 0x000F;
417 pd2 = ((pd >> 4) & 0x000F) ^ pd1;
418 tmp ^= (pd1 << 3) | (pd1 << 8);
419 tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
420
421 return tmp;
422}
423
424static uint16_t NVRAM_compute_crc (Nvram *nvram, uint32_t start, uint32_t count)
425{
426 uint32_t i;
427 uint16_t crc = 0xFFFF;
428 int odd;
429
430 odd = count & 1;
431 count &= ~1;
432 for (i = 0; i != count; i++) {
433 crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
434 }
435 if (odd) {
436 crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
437 }
438
439 return crc;
440}
441
442#define CMDLINE_ADDR 0x017ff000
443
444static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size,
445 const char *arch,
446 uint32_t RAM_size, int boot_device,
447 uint32_t kernel_image, uint32_t kernel_size,
448 const char *cmdline,
449 uint32_t initrd_image, uint32_t initrd_size,
450 uint32_t NVRAM_image,
451 int width, int height, int depth)
452{
453 uint16_t crc;
454
455
456 NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
457 NVRAM_set_lword(nvram, 0x10, 0x00000002);
458 NVRAM_set_word(nvram, 0x14, NVRAM_size);
459 NVRAM_set_string(nvram, 0x20, arch, 16);
460 NVRAM_set_lword(nvram, 0x30, RAM_size);
461 NVRAM_set_byte(nvram, 0x34, boot_device);
462 NVRAM_set_lword(nvram, 0x38, kernel_image);
463 NVRAM_set_lword(nvram, 0x3C, kernel_size);
464 if (cmdline) {
465
466 pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR,
467 cmdline);
468 NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
469 NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
470 } else {
471 NVRAM_set_lword(nvram, 0x40, 0);
472 NVRAM_set_lword(nvram, 0x44, 0);
473 }
474 NVRAM_set_lword(nvram, 0x48, initrd_image);
475 NVRAM_set_lword(nvram, 0x4C, initrd_size);
476 NVRAM_set_lword(nvram, 0x50, NVRAM_image);
477
478 NVRAM_set_word(nvram, 0x54, width);
479 NVRAM_set_word(nvram, 0x56, height);
480 NVRAM_set_word(nvram, 0x58, depth);
481 crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
482 NVRAM_set_word(nvram, 0xFC, crc);
483
484 return 0;
485}
486
487
488static void ppc_prep_init(MachineState *machine)
489{
490 ram_addr_t ram_size = machine->ram_size;
491 const char *kernel_filename = machine->kernel_filename;
492 const char *kernel_cmdline = machine->kernel_cmdline;
493 const char *initrd_filename = machine->initrd_filename;
494 const char *boot_device = machine->boot_order;
495 MemoryRegion *sysmem = get_system_memory();
496 PowerPCCPU *cpu = NULL;
497 CPUPPCState *env = NULL;
498 Nvram *m48t59;
499#if 0
500 MemoryRegion *xcsr = g_new(MemoryRegion, 1);
501#endif
502 int linux_boot, i, nb_nics1;
503 MemoryRegion *ram = g_new(MemoryRegion, 1);
504 uint32_t kernel_base, initrd_base;
505 long kernel_size, initrd_size;
506 DeviceState *dev;
507 PCIHostState *pcihost;
508 PCIBus *pci_bus;
509 PCIDevice *pci;
510 ISABus *isa_bus;
511 ISADevice *isa;
512 int ppc_boot_device;
513 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
514
515 sysctrl = g_malloc0(sizeof(sysctrl_t));
516
517 linux_boot = (kernel_filename != NULL);
518
519
520 if (machine->cpu_model == NULL)
521 machine->cpu_model = "602";
522 for (i = 0; i < smp_cpus; i++) {
523 cpu = cpu_ppc_init(machine->cpu_model);
524 if (cpu == NULL) {
525 fprintf(stderr, "Unable to find PowerPC CPU definition\n");
526 exit(1);
527 }
528 env = &cpu->env;
529
530 if (env->flags & POWERPC_FLAG_RTC_CLK) {
531
532 cpu_ppc_tb_init(env, 7812500UL);
533 } else {
534
535 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
536 }
537 qemu_register_reset(ppc_prep_reset, cpu);
538 }
539
540
541 memory_region_allocate_system_memory(ram, NULL, "ppc_prep.ram", ram_size);
542 memory_region_add_subregion(sysmem, 0, ram);
543
544 if (linux_boot) {
545 kernel_base = KERNEL_LOAD_ADDR;
546
547 kernel_size = load_image_targphys(kernel_filename, kernel_base,
548 ram_size - kernel_base);
549 if (kernel_size < 0) {
550 error_report("could not load kernel '%s'", kernel_filename);
551 exit(1);
552 }
553
554 if (initrd_filename) {
555 initrd_base = INITRD_LOAD_ADDR;
556 initrd_size = load_image_targphys(initrd_filename, initrd_base,
557 ram_size - initrd_base);
558 if (initrd_size < 0) {
559 error_report("could not load initial ram disk '%s'",
560 initrd_filename);
561 exit(1);
562 }
563 } else {
564 initrd_base = 0;
565 initrd_size = 0;
566 }
567 ppc_boot_device = 'm';
568 } else {
569 kernel_base = 0;
570 kernel_size = 0;
571 initrd_base = 0;
572 initrd_size = 0;
573 ppc_boot_device = '\0';
574
575 for (i = 0; boot_device[i] != '\0'; i++) {
576 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
577 ppc_boot_device = boot_device[i];
578 break;
579 }
580 }
581 if (ppc_boot_device == '\0') {
582 fprintf(stderr, "No valid boot device for Mac99 machine\n");
583 exit(1);
584 }
585 }
586
587 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
588 error_report("Only 6xx bus is supported on PREP machine");
589 exit(1);
590 }
591
592 dev = qdev_create(NULL, "raven-pcihost");
593 if (bios_name == NULL) {
594 bios_name = BIOS_FILENAME;
595 }
596 qdev_prop_set_string(dev, "bios-name", bios_name);
597 qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
598 pcihost = PCI_HOST_BRIDGE(dev);
599 object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL);
600 qdev_init_nofail(dev);
601 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
602 if (pci_bus == NULL) {
603 fprintf(stderr, "Couldn't create PCI host controller.\n");
604 exit(1);
605 }
606 sysctrl->contiguous_map_irq = qdev_get_gpio_in(dev, 0);
607
608
609 pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378");
610 cpu = POWERPC_CPU(first_cpu);
611 qdev_connect_gpio_out(&pci->qdev, 0,
612 cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
613 sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9));
614 sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11));
615 sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9));
616 sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11));
617 isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci), "isa.0"));
618
619
620 isa = isa_create(isa_bus, TYPE_PC87312);
621 dev = DEVICE(isa);
622 qdev_prop_set_uint8(dev, "config", 13);
623 qdev_init_nofail(dev);
624
625
626 pci_vga_init(pci_bus);
627
628 nb_nics1 = nb_nics;
629 if (nb_nics1 > NE2000_NB_MAX)
630 nb_nics1 = NE2000_NB_MAX;
631 for(i = 0; i < nb_nics1; i++) {
632 if (nd_table[i].model == NULL) {
633 nd_table[i].model = g_strdup("ne2k_isa");
634 }
635 if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
636 isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i],
637 &nd_table[i]);
638 } else {
639 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
640 }
641 }
642
643 ide_drive_get(hd, ARRAY_SIZE(hd));
644 for(i = 0; i < MAX_IDE_BUS; i++) {
645 isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i],
646 hd[2 * i],
647 hd[2 * i + 1]);
648 }
649 isa_create_simple(isa_bus, "i8042");
650
651 cpu = POWERPC_CPU(first_cpu);
652 sysctrl->reset_irq = cpu->env.irq_inputs[PPC6xx_INPUT_HRESET];
653
654 portio_list_init(&prep_port_list, NULL, prep_portio_list, sysctrl, "prep");
655 portio_list_add(&prep_port_list, isa_address_space_io(isa), 0x0);
656
657
658#if 0
659 memory_region_init_io(xcsr, NULL, &PPC_XCSR_ops, NULL, "ppc-xcsr", 0x1000);
660 memory_region_add_subregion(sysmem, 0xFEFF0000, xcsr);
661#endif
662
663 if (machine_usb(machine)) {
664 pci_create_simple(pci_bus, -1, "pci-ohci");
665 }
666
667 m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 2000, 59);
668 if (m48t59 == NULL)
669 return;
670 sysctrl->nvram = m48t59;
671
672
673 PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size,
674 ppc_boot_device,
675 kernel_base, kernel_size,
676 kernel_cmdline,
677 initrd_base, initrd_size,
678
679 0,
680 graphic_width, graphic_height, graphic_depth);
681}
682
683static void prep_machine_init(MachineClass *mc)
684{
685 mc->desc = "PowerPC PREP platform";
686 mc->init = ppc_prep_init;
687 mc->block_default_type = IF_IDE;
688 mc->max_cpus = MAX_CPUS;
689 mc->default_boot_order = "cad";
690}
691
692static int prep_set_cmos_checksum(DeviceState *dev, void *opaque)
693{
694 uint16_t checksum = *(uint16_t *)opaque;
695 ISADevice *rtc;
696
697 if (object_dynamic_cast(OBJECT(dev), "mc146818rtc")) {
698 rtc = ISA_DEVICE(dev);
699 rtc_set_memory(rtc, 0x2e, checksum & 0xff);
700 rtc_set_memory(rtc, 0x3e, checksum & 0xff);
701 rtc_set_memory(rtc, 0x2f, checksum >> 8);
702 rtc_set_memory(rtc, 0x3f, checksum >> 8);
703 }
704 return 0;
705}
706
707static void ibm_40p_init(MachineState *machine)
708{
709 CPUPPCState *env = NULL;
710 uint16_t cmos_checksum;
711 PowerPCCPU *cpu;
712 DeviceState *dev;
713 SysBusDevice *pcihost;
714 Nvram *m48t59 = NULL;
715 PCIBus *pci_bus;
716 ISABus *isa_bus;
717 void *fw_cfg;
718 int i;
719 uint32_t kernel_base = 0, initrd_base = 0;
720 long kernel_size = 0, initrd_size = 0;
721 char boot_device;
722
723
724 if (!machine->cpu_model) {
725 machine->cpu_model = "604";
726 }
727 cpu = cpu_ppc_init(machine->cpu_model);
728 if (!cpu) {
729 error_report("could not initialize CPU '%s'",
730 machine->cpu_model);
731 exit(1);
732 }
733 env = &cpu->env;
734 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
735 error_report("only 6xx bus is supported on this machine");
736 exit(1);
737 }
738
739 if (env->flags & POWERPC_FLAG_RTC_CLK) {
740
741 cpu_ppc_tb_init(env, 7812500UL);
742 } else {
743
744 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
745 }
746 qemu_register_reset(ppc_prep_reset, cpu);
747
748
749 dev = qdev_create(NULL, "raven-pcihost");
750 if (!bios_name) {
751 bios_name = BIOS_FILENAME;
752 }
753 qdev_prop_set_string(dev, "bios-name", bios_name);
754 qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
755 pcihost = SYS_BUS_DEVICE(dev);
756 object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL);
757 qdev_init_nofail(dev);
758 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0"));
759 if (!pci_bus) {
760 error_report("could not create PCI host controller");
761 exit(1);
762 }
763
764
765 dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(11, 0), "i82378"));
766 qdev_connect_gpio_out(dev, 0,
767 cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
768 sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(dev, 15));
769 sysbus_connect_irq(pcihost, 1, qdev_get_gpio_in(dev, 13));
770 sysbus_connect_irq(pcihost, 2, qdev_get_gpio_in(dev, 15));
771 sysbus_connect_irq(pcihost, 3, qdev_get_gpio_in(dev, 13));
772 isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
773
774
775 dev = DEVICE(isa_create(isa_bus, "rs6000-mc"));
776 qdev_prop_set_uint32(dev, "ram-size", machine->ram_size);
777 qdev_init_nofail(dev);
778
779
780 cmos_checksum = 0x6aa9;
781 qbus_walk_children(BUS(isa_bus), prep_set_cmos_checksum, NULL, NULL, NULL,
782 &cmos_checksum);
783
784
785 if (defaults_enabled()) {
786 isa_create_simple(isa_bus, "i8042");
787 m48t59 = NVRAM(isa_create_simple(isa_bus, "isa-m48t59"));
788
789 dev = DEVICE(isa_create(isa_bus, "cs4231a"));
790 qdev_prop_set_uint32(dev, "iobase", 0x830);
791 qdev_prop_set_uint32(dev, "irq", 10);
792 qdev_init_nofail(dev);
793
794 dev = DEVICE(isa_create(isa_bus, "pc87312"));
795 qdev_prop_set_uint32(dev, "config", 12);
796 qdev_init_nofail(dev);
797
798 dev = DEVICE(isa_create(isa_bus, "prep-systemio"));
799 qdev_prop_set_uint32(dev, "ibm-planar-id", 0xfc);
800 qdev_prop_set_uint32(dev, "equipment", 0xc0);
801 qdev_init_nofail(dev);
802
803 pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "lsi53c810");
804
805
806 pci_vga_init(pci_bus);
807
808 for (i = 0; i < nb_nics; i++) {
809 pci_nic_init_nofail(&nd_table[i], pci_bus, "pcnet",
810 i == 0 ? "3" : NULL);
811 }
812 }
813
814
815 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
816
817 if (machine->kernel_filename) {
818
819 kernel_base = KERNEL_LOAD_ADDR;
820 kernel_size = load_image_targphys(machine->kernel_filename,
821 kernel_base,
822 machine->ram_size - kernel_base);
823 if (kernel_size < 0) {
824 error_report("could not load kernel '%s'",
825 machine->kernel_filename);
826 exit(1);
827 }
828 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
829 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
830
831 if (machine->initrd_filename) {
832 initrd_base = INITRD_LOAD_ADDR;
833 initrd_size = load_image_targphys(machine->initrd_filename,
834 initrd_base,
835 machine->ram_size - initrd_base);
836 if (initrd_size < 0) {
837 error_report("could not load initial ram disk '%s'",
838 machine->initrd_filename);
839 exit(1);
840 }
841 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
842 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
843 }
844 if (machine->kernel_cmdline && *machine->kernel_cmdline) {
845 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
846 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
847 machine->kernel_cmdline);
848 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA,
849 machine->kernel_cmdline);
850 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
851 strlen(machine->kernel_cmdline) + 1);
852 }
853 boot_device = 'm';
854 } else {
855 boot_device = machine->boot_order[0];
856 }
857
858 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
859 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
860 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_PREP);
861
862 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
863 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
864 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
865
866 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
867 if (kvm_enabled()) {
868#ifdef CONFIG_KVM
869 uint8_t *hypercall;
870
871 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq());
872 hypercall = g_malloc(16);
873 kvmppc_get_hypercall(env, hypercall, 16);
874 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
875 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
876#endif
877 } else {
878 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, NANOSECONDS_PER_SECOND);
879 }
880 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device);
881 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
882
883
884 if (m48t59) {
885 PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size,
886 boot_device,
887 kernel_base, kernel_size,
888 machine->kernel_cmdline,
889 initrd_base, initrd_size,
890
891 0,
892 graphic_width, graphic_height, graphic_depth);
893 }
894}
895
896static void ibm_40p_machine_init(MachineClass *mc)
897{
898 mc->desc = "IBM RS/6000 7020 (40p)",
899 mc->init = ibm_40p_init;
900 mc->max_cpus = 1;
901 mc->pci_allow_0_address = true;
902 mc->default_ram_size = 128 * M_BYTE;
903 mc->block_default_type = IF_SCSI;
904 mc->default_boot_order = "c";
905}
906
907DEFINE_MACHINE("40p", ibm_40p_machine_init)
908DEFINE_MACHINE("prep", prep_machine_init)
909