1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27#include "qemu/osdep.h"
28#include "qapi/error.h"
29#include "sysemu/sysemu.h"
30#include "sysemu/numa.h"
31#include "hw/hw.h"
32#include "qemu/log.h"
33#include "hw/fw-path-provider.h"
34#include "elf.h"
35#include "net/net.h"
36#include "sysemu/device_tree.h"
37#include "sysemu/block-backend.h"
38#include "sysemu/cpus.h"
39#include "sysemu/hw_accel.h"
40#include "kvm_ppc.h"
41#include "migration/misc.h"
42#include "migration/global_state.h"
43#include "migration/register.h"
44#include "mmu-hash64.h"
45#include "mmu-book3s-v3.h"
46#include "cpu-models.h"
47#include "qom/cpu.h"
48
49#include "hw/boards.h"
50#include "hw/ppc/ppc.h"
51#include "hw/loader.h"
52
53#include "hw/ppc/fdt.h"
54#include "hw/ppc/spapr.h"
55#include "hw/ppc/spapr_vio.h"
56#include "hw/pci-host/spapr.h"
57#include "hw/ppc/xics.h"
58#include "hw/pci/msi.h"
59
60#include "hw/pci/pci.h"
61#include "hw/scsi/scsi.h"
62#include "hw/virtio/virtio-scsi.h"
63#include "hw/virtio/vhost-scsi-common.h"
64
65#include "exec/address-spaces.h"
66#include "hw/usb.h"
67#include "qemu/config-file.h"
68#include "qemu/error-report.h"
69#include "trace.h"
70#include "hw/nmi.h"
71#include "hw/intc/intc.h"
72
73#include "hw/compat.h"
74#include "qemu/cutils.h"
75#include "hw/ppc/spapr_cpu_core.h"
76#include "qmp-commands.h"
77
78#include <libfdt.h>
79
80
81
82
83
84
85
86
87
88
89
90#define FDT_MAX_SIZE 0x100000
91#define RTAS_MAX_SIZE 0x10000
92#define RTAS_MAX_ADDR 0x80000000
93#define FW_MAX_SIZE 0x400000
94#define FW_FILE_NAME "slof.bin"
95#define FW_OVERHEAD 0x2800000
96#define KERNEL_LOAD_ADDR FW_MAX_SIZE
97
98#define MIN_RMA_SLOF 128UL
99
100#define PHANDLE_XICP 0x00001111
101
102static ICSState *spapr_ics_create(sPAPRMachineState *spapr,
103 const char *type_ics,
104 int nr_irqs, Error **errp)
105{
106 Error *local_err = NULL;
107 Object *obj;
108
109 obj = object_new(type_ics);
110 object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort);
111 object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr),
112 &error_abort);
113 object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err);
114 if (local_err) {
115 goto error;
116 }
117 object_property_set_bool(obj, true, "realized", &local_err);
118 if (local_err) {
119 goto error;
120 }
121
122 return ICS_SIMPLE(obj);
123
124error:
125 error_propagate(errp, local_err);
126 return NULL;
127}
128
129static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque)
130{
131
132
133
134
135 return false;
136}
137
138static const VMStateDescription pre_2_10_vmstate_dummy_icp = {
139 .name = "icp/server",
140 .version_id = 1,
141 .minimum_version_id = 1,
142 .needed = pre_2_10_vmstate_dummy_icp_needed,
143 .fields = (VMStateField[]) {
144 VMSTATE_UNUSED(4),
145 VMSTATE_UNUSED(1),
146 VMSTATE_UNUSED(1),
147 VMSTATE_END_OF_LIST()
148 },
149};
150
151static void pre_2_10_vmstate_register_dummy_icp(int i)
152{
153 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp,
154 (void *)(uintptr_t) i);
155}
156
157static void pre_2_10_vmstate_unregister_dummy_icp(int i)
158{
159 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp,
160 (void *)(uintptr_t) i);
161}
162
163static inline int xics_max_server_number(void)
164{
165 return DIV_ROUND_UP(max_cpus * kvmppc_smt_threads(), smp_threads);
166}
167
168static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp)
169{
170 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
171 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
172
173 if (kvm_enabled()) {
174 if (machine_kernel_irqchip_allowed(machine) &&
175 !xics_kvm_init(spapr, errp)) {
176 spapr->icp_type = TYPE_KVM_ICP;
177 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs, errp);
178 }
179 if (machine_kernel_irqchip_required(machine) && !spapr->ics) {
180 error_prepend(errp, "kernel_irqchip requested but unavailable: ");
181 return;
182 }
183 }
184
185 if (!spapr->ics) {
186 xics_spapr_init(spapr);
187 spapr->icp_type = TYPE_ICP;
188 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs, errp);
189 if (!spapr->ics) {
190 return;
191 }
192 }
193
194 if (smc->pre_2_10_has_unused_icps) {
195 int i;
196
197 for (i = 0; i < xics_max_server_number(); i++) {
198
199
200
201 pre_2_10_vmstate_register_dummy_icp(i);
202 }
203 }
204}
205
206static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
207 int smt_threads)
208{
209 int i, ret = 0;
210 uint32_t servers_prop[smt_threads];
211 uint32_t gservers_prop[smt_threads * 2];
212 int index = ppc_get_vcpu_dt_id(cpu);
213
214 if (cpu->compat_pvr) {
215 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr);
216 if (ret < 0) {
217 return ret;
218 }
219 }
220
221
222 for (i = 0; i < smt_threads; i++) {
223 servers_prop[i] = cpu_to_be32(index + i);
224
225 gservers_prop[i*2] = cpu_to_be32(index + i);
226 gservers_prop[i*2 + 1] = 0;
227 }
228 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
229 servers_prop, sizeof(servers_prop));
230 if (ret < 0) {
231 return ret;
232 }
233 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
234 gservers_prop, sizeof(gservers_prop));
235
236 return ret;
237}
238
239static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu)
240{
241 int index = ppc_get_vcpu_dt_id(cpu);
242 uint32_t associativity[] = {cpu_to_be32(0x5),
243 cpu_to_be32(0x0),
244 cpu_to_be32(0x0),
245 cpu_to_be32(0x0),
246 cpu_to_be32(cpu->node_id),
247 cpu_to_be32(index)};
248
249
250 return fdt_setprop(fdt, offset, "ibm,associativity", associativity,
251 sizeof(associativity));
252}
253
254
255static void spapr_populate_pa_features(PowerPCCPU *cpu, void *fdt, int offset,
256 bool legacy_guest)
257{
258 CPUPPCState *env = &cpu->env;
259 uint8_t pa_features_206[] = { 6, 0,
260 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
261 uint8_t pa_features_207[] = { 24, 0,
262 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
263 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
264 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
265 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
266 uint8_t pa_features_300[] = { 66, 0,
267
268
269 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
270
271 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
272
273 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
274
275 0x80, 0x00, 0x80, 0x00, 0x00, 0x00,
276
277 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
278
279 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00,
280
281 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
282
283 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
284
285 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
286
287 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
288
289 0x80, 0x00, 0x80, 0x00, 0x00, 0x00,
290 };
291 uint8_t *pa_features = NULL;
292 size_t pa_size;
293
294 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) {
295 pa_features = pa_features_206;
296 pa_size = sizeof(pa_features_206);
297 }
298 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) {
299 pa_features = pa_features_207;
300 pa_size = sizeof(pa_features_207);
301 }
302 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) {
303 pa_features = pa_features_300;
304 pa_size = sizeof(pa_features_300);
305 }
306 if (!pa_features) {
307 return;
308 }
309
310 if (env->ci_large_pages) {
311
312
313
314
315
316
317
318 pa_features[3] |= 0x20;
319 }
320 if (kvmppc_has_cap_htm() && pa_size > 24) {
321 pa_features[24] |= 0x80;
322 }
323 if (legacy_guest && pa_size > 40) {
324
325
326
327 pa_features[40 + 2] &= ~0x80;
328 }
329
330 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
331}
332
333static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
334{
335 int ret = 0, offset, cpus_offset;
336 CPUState *cs;
337 char cpu_model[32];
338 int smt = kvmppc_smt_threads();
339 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
340
341 CPU_FOREACH(cs) {
342 PowerPCCPU *cpu = POWERPC_CPU(cs);
343 DeviceClass *dc = DEVICE_GET_CLASS(cs);
344 int index = ppc_get_vcpu_dt_id(cpu);
345 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu));
346
347 if ((index % smt) != 0) {
348 continue;
349 }
350
351 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
352
353 cpus_offset = fdt_path_offset(fdt, "/cpus");
354 if (cpus_offset < 0) {
355 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
356 "cpus");
357 if (cpus_offset < 0) {
358 return cpus_offset;
359 }
360 }
361 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
362 if (offset < 0) {
363 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
364 if (offset < 0) {
365 return offset;
366 }
367 }
368
369 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
370 pft_size_prop, sizeof(pft_size_prop));
371 if (ret < 0) {
372 return ret;
373 }
374
375 if (nb_numa_nodes > 1) {
376 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu);
377 if (ret < 0) {
378 return ret;
379 }
380 }
381
382 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt);
383 if (ret < 0) {
384 return ret;
385 }
386
387 spapr_populate_pa_features(cpu, fdt, offset,
388 spapr->cas_legacy_guest_workaround);
389 }
390 return ret;
391}
392
393static hwaddr spapr_node0_size(void)
394{
395 MachineState *machine = MACHINE(qdev_get_machine());
396
397 if (nb_numa_nodes) {
398 int i;
399 for (i = 0; i < nb_numa_nodes; ++i) {
400 if (numa_info[i].node_mem) {
401 return MIN(pow2floor(numa_info[i].node_mem),
402 machine->ram_size);
403 }
404 }
405 }
406 return machine->ram_size;
407}
408
409static void add_str(GString *s, const gchar *s1)
410{
411 g_string_append_len(s, s1, strlen(s1) + 1);
412}
413
414static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
415 hwaddr size)
416{
417 uint32_t associativity[] = {
418 cpu_to_be32(0x4),
419 cpu_to_be32(0x0), cpu_to_be32(0x0),
420 cpu_to_be32(0x0), cpu_to_be32(nodeid)
421 };
422 char mem_name[32];
423 uint64_t mem_reg_property[2];
424 int off;
425
426 mem_reg_property[0] = cpu_to_be64(start);
427 mem_reg_property[1] = cpu_to_be64(size);
428
429 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
430 off = fdt_add_subnode(fdt, 0, mem_name);
431 _FDT(off);
432 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
433 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
434 sizeof(mem_reg_property))));
435 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
436 sizeof(associativity))));
437 return off;
438}
439
440static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
441{
442 MachineState *machine = MACHINE(spapr);
443 hwaddr mem_start, node_size;
444 int i, nb_nodes = nb_numa_nodes;
445 NodeInfo *nodes = numa_info;
446 NodeInfo ramnode;
447
448
449 if (!nb_numa_nodes) {
450 nb_nodes = 1;
451 ramnode.node_mem = machine->ram_size;
452 nodes = &ramnode;
453 }
454
455 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
456 if (!nodes[i].node_mem) {
457 continue;
458 }
459 if (mem_start >= machine->ram_size) {
460 node_size = 0;
461 } else {
462 node_size = nodes[i].node_mem;
463 if (node_size > machine->ram_size - mem_start) {
464 node_size = machine->ram_size - mem_start;
465 }
466 }
467 if (!mem_start) {
468
469 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
470 mem_start += spapr->rma_size;
471 node_size -= spapr->rma_size;
472 }
473 for ( ; node_size; ) {
474 hwaddr sizetmp = pow2floor(node_size);
475
476
477 if (ctzl(mem_start) < ctzl(sizetmp)) {
478 sizetmp = 1ULL << ctzl(mem_start);
479 }
480
481 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
482 node_size -= sizetmp;
483 mem_start += sizetmp;
484 }
485 }
486
487 return 0;
488}
489
490static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
491 sPAPRMachineState *spapr)
492{
493 PowerPCCPU *cpu = POWERPC_CPU(cs);
494 CPUPPCState *env = &cpu->env;
495 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
496 int index = ppc_get_vcpu_dt_id(cpu);
497 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
498 0xffffffff, 0xffffffff};
499 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
500 : SPAPR_TIMEBASE_FREQ;
501 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
502 uint32_t page_sizes_prop[64];
503 size_t page_sizes_prop_size;
504 uint32_t vcpus_per_socket = smp_threads * smp_cores;
505 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
506 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu));
507 sPAPRDRConnector *drc;
508 int drc_index;
509 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ];
510 int i;
511
512 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index);
513 if (drc) {
514 drc_index = spapr_drc_index(drc);
515 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
516 }
517
518 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
519 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
520
521 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
522 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
523 env->dcache_line_size)));
524 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
525 env->dcache_line_size)));
526 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
527 env->icache_line_size)));
528 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
529 env->icache_line_size)));
530
531 if (pcc->l1_dcache_size) {
532 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
533 pcc->l1_dcache_size)));
534 } else {
535 warn_report("Unknown L1 dcache size for cpu");
536 }
537 if (pcc->l1_icache_size) {
538 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
539 pcc->l1_icache_size)));
540 } else {
541 warn_report("Unknown L1 icache size for cpu");
542 }
543
544 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
545 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
546 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr)));
547 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
548 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
549 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
550
551 if (env->spr_cb[SPR_PURR].oea_read) {
552 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
553 }
554
555 if (env->mmu_model & POWERPC_MMU_1TSEG) {
556 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
557 segs, sizeof(segs))));
558 }
559
560
561
562
563
564 if (env->insns_flags & PPC_ALTIVEC) {
565 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
566
567 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
568 }
569
570
571
572
573 if (env->insns_flags2 & PPC2_DFP) {
574 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
575 }
576
577 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
578 sizeof(page_sizes_prop));
579 if (page_sizes_prop_size) {
580 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
581 page_sizes_prop, page_sizes_prop_size)));
582 }
583
584 spapr_populate_pa_features(cpu, fdt, offset, false);
585
586 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
587 cs->cpu_index / vcpus_per_socket)));
588
589 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
590 pft_size_prop, sizeof(pft_size_prop))));
591
592 if (nb_numa_nodes > 1) {
593 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu));
594 }
595
596 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt));
597
598 if (pcc->radix_page_info) {
599 for (i = 0; i < pcc->radix_page_info->count; i++) {
600 radix_AP_encodings[i] =
601 cpu_to_be32(pcc->radix_page_info->entries[i]);
602 }
603 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings",
604 radix_AP_encodings,
605 pcc->radix_page_info->count *
606 sizeof(radix_AP_encodings[0]))));
607 }
608}
609
610static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
611{
612 CPUState *cs;
613 int cpus_offset;
614 char *nodename;
615 int smt = kvmppc_smt_threads();
616
617 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
618 _FDT(cpus_offset);
619 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
620 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
621
622
623
624
625
626
627 CPU_FOREACH_REVERSE(cs) {
628 PowerPCCPU *cpu = POWERPC_CPU(cs);
629 int index = ppc_get_vcpu_dt_id(cpu);
630 DeviceClass *dc = DEVICE_GET_CLASS(cs);
631 int offset;
632
633 if ((index % smt) != 0) {
634 continue;
635 }
636
637 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
638 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
639 g_free(nodename);
640 _FDT(offset);
641 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
642 }
643
644}
645
646
647
648
649
650
651static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
652{
653 MachineState *machine = MACHINE(spapr);
654 int ret, i, offset;
655 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
656 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
657 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size;
658 uint32_t nr_lmbs = (spapr->hotplug_memory.base +
659 memory_region_size(&spapr->hotplug_memory.mr)) /
660 lmb_size;
661 uint32_t *int_buf, *cur_index, buf_len;
662 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
663
664
665
666
667 if (machine->ram_size == machine->maxram_size) {
668 return 0;
669 }
670
671
672
673
674
675 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2)
676 * sizeof(uint32_t);
677 cur_index = int_buf = g_malloc0(buf_len);
678
679 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
680
681 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
682 sizeof(prop_lmb_size));
683 if (ret < 0) {
684 goto out;
685 }
686
687 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
688 if (ret < 0) {
689 goto out;
690 }
691
692 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
693 if (ret < 0) {
694 goto out;
695 }
696
697
698 int_buf[0] = cpu_to_be32(nr_lmbs);
699 cur_index++;
700 for (i = 0; i < nr_lmbs; i++) {
701 uint64_t addr = i * lmb_size;
702 uint32_t *dynamic_memory = cur_index;
703
704 if (i >= hotplug_lmb_start) {
705 sPAPRDRConnector *drc;
706
707 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i);
708 g_assert(drc);
709
710 dynamic_memory[0] = cpu_to_be32(addr >> 32);
711 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
712 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc));
713 dynamic_memory[3] = cpu_to_be32(0);
714 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL));
715 if (memory_region_present(get_system_memory(), addr)) {
716 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
717 } else {
718 dynamic_memory[5] = cpu_to_be32(0);
719 }
720 } else {
721
722
723
724
725
726 dynamic_memory[0] = cpu_to_be32(addr >> 32);
727 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
728 dynamic_memory[2] = cpu_to_be32(0);
729 dynamic_memory[3] = cpu_to_be32(0);
730 dynamic_memory[4] = cpu_to_be32(-1);
731 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
732 SPAPR_LMB_FLAGS_DRC_INVALID);
733 }
734
735 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
736 }
737 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
738 if (ret < 0) {
739 goto out;
740 }
741
742
743 cur_index = int_buf;
744 int_buf[0] = cpu_to_be32(nr_nodes);
745 int_buf[1] = cpu_to_be32(4);
746 cur_index += 2;
747 for (i = 0; i < nr_nodes; i++) {
748 uint32_t associativity[] = {
749 cpu_to_be32(0x0),
750 cpu_to_be32(0x0),
751 cpu_to_be32(0x0),
752 cpu_to_be32(i)
753 };
754 memcpy(cur_index, associativity, sizeof(associativity));
755 cur_index += 4;
756 }
757 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
758 (cur_index - int_buf) * sizeof(uint32_t));
759out:
760 g_free(int_buf);
761 return ret;
762}
763
764static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt,
765 sPAPROptionVector *ov5_updates)
766{
767 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
768 int ret = 0, offset;
769
770
771 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) {
772 g_assert(smc->dr_lmb_enabled);
773 ret = spapr_populate_drconf_memory(spapr, fdt);
774 if (ret) {
775 goto out;
776 }
777 }
778
779 offset = fdt_path_offset(fdt, "/chosen");
780 if (offset < 0) {
781 offset = fdt_add_subnode(fdt, 0, "chosen");
782 if (offset < 0) {
783 return offset;
784 }
785 }
786 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas,
787 "ibm,architecture-vec-5");
788
789out:
790 return ret;
791}
792
793static bool spapr_hotplugged_dev_before_cas(void)
794{
795 Object *drc_container, *obj;
796 ObjectProperty *prop;
797 ObjectPropertyIterator iter;
798
799 drc_container = container_get(object_get_root(), "/dr-connector");
800 object_property_iter_init(&iter, drc_container);
801 while ((prop = object_property_iter_next(&iter))) {
802 if (!strstart(prop->type, "link<", NULL)) {
803 continue;
804 }
805 obj = object_property_get_link(drc_container, prop->name, NULL);
806 if (spapr_drc_needed(obj)) {
807 return true;
808 }
809 }
810 return false;
811}
812
813int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
814 target_ulong addr, target_ulong size,
815 sPAPROptionVector *ov5_updates)
816{
817 void *fdt, *fdt_skel;
818 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
819
820 if (spapr_hotplugged_dev_before_cas()) {
821 return 1;
822 }
823
824 size -= sizeof(hdr);
825
826
827 fdt_skel = g_malloc0(size);
828 _FDT((fdt_create(fdt_skel, size)));
829 _FDT((fdt_begin_node(fdt_skel, "")));
830 _FDT((fdt_end_node(fdt_skel)));
831 _FDT((fdt_finish(fdt_skel)));
832 fdt = g_malloc0(size);
833 _FDT((fdt_open_into(fdt_skel, fdt, size)));
834 g_free(fdt_skel);
835
836
837 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
838
839 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) {
840 return -1;
841 }
842
843
844 _FDT((fdt_pack(fdt)));
845
846 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
847 trace_spapr_cas_failed(size);
848 return -1;
849 }
850
851 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
852 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
853 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
854 g_free(fdt);
855
856 return 0;
857}
858
859static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt)
860{
861 int rtas;
862 GString *hypertas = g_string_sized_new(256);
863 GString *qemu_hypertas = g_string_sized_new(256);
864 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
865 uint64_t max_hotplug_addr = spapr->hotplug_memory.base +
866 memory_region_size(&spapr->hotplug_memory.mr);
867 uint32_t lrdr_capacity[] = {
868 cpu_to_be32(max_hotplug_addr >> 32),
869 cpu_to_be32(max_hotplug_addr & 0xffffffff),
870 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE),
871 cpu_to_be32(max_cpus / smp_threads),
872 };
873
874 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas"));
875
876
877 add_str(hypertas, "hcall-pft");
878 add_str(hypertas, "hcall-term");
879 add_str(hypertas, "hcall-dabr");
880 add_str(hypertas, "hcall-interrupt");
881 add_str(hypertas, "hcall-tce");
882 add_str(hypertas, "hcall-vio");
883 add_str(hypertas, "hcall-splpar");
884 add_str(hypertas, "hcall-bulk");
885 add_str(hypertas, "hcall-set-mode");
886 add_str(hypertas, "hcall-sprg0");
887 add_str(hypertas, "hcall-copy");
888 add_str(hypertas, "hcall-debug");
889 add_str(qemu_hypertas, "hcall-memop1");
890
891 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
892 add_str(hypertas, "hcall-multi-tce");
893 }
894
895 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
896 add_str(hypertas, "hcall-hpt-resize");
897 }
898
899 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions",
900 hypertas->str, hypertas->len));
901 g_string_free(hypertas, TRUE);
902 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions",
903 qemu_hypertas->str, qemu_hypertas->len));
904 g_string_free(qemu_hypertas, TRUE);
905
906 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points",
907 refpoints, sizeof(refpoints)));
908
909 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max",
910 RTAS_ERROR_LOG_MAX));
911 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate",
912 RTAS_EVENT_SCAN_RATE));
913
914 if (msi_nonbroken) {
915 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0));
916 }
917
918
919
920
921
922
923
924
925 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0));
926
927 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity",
928 lrdr_capacity, sizeof(lrdr_capacity)));
929
930 spapr_dt_rtas_tokens(fdt, rtas);
931}
932
933
934
935
936static void spapr_dt_ov5_platform_support(void *fdt, int chosen)
937{
938 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
939
940 char val[2 * 4] = {
941 23, 0x00,
942 24, 0x00,
943 25, 0x00,
944 26, 0x40,
945 };
946
947 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0,
948 first_ppc_cpu->compat_pvr)) {
949
950 val[3] = 0x00;
951 } else if (kvm_enabled()) {
952 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
953 val[3] = 0x80;
954 } else if (kvmppc_has_cap_mmu_radix()) {
955 val[3] = 0x40;
956 } else {
957 val[3] = 0x00;
958 }
959 } else {
960
961 val[3] = 0xC0;
962 }
963 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support",
964 val, sizeof(val)));
965}
966
967static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt)
968{
969 MachineState *machine = MACHINE(spapr);
970 int chosen;
971 const char *boot_device = machine->boot_order;
972 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
973 size_t cb = 0;
974 char *bootlist = get_boot_devices_list(&cb, true);
975
976 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen"));
977
978 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline));
979 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start",
980 spapr->initrd_base));
981 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end",
982 spapr->initrd_base + spapr->initrd_size));
983
984 if (spapr->kernel_size) {
985 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
986 cpu_to_be64(spapr->kernel_size) };
987
988 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel",
989 &kprop, sizeof(kprop)));
990 if (spapr->kernel_le) {
991 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0));
992 }
993 }
994 if (boot_menu) {
995 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu)));
996 }
997 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width));
998 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height));
999 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth));
1000
1001 if (cb && bootlist) {
1002 int i;
1003
1004 for (i = 0; i < cb; i++) {
1005 if (bootlist[i] == '\n') {
1006 bootlist[i] = ' ';
1007 }
1008 }
1009 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist));
1010 }
1011
1012 if (boot_device && strlen(boot_device)) {
1013 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device));
1014 }
1015
1016 if (!spapr->has_graphics && stdout_path) {
1017 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path));
1018 }
1019
1020 spapr_dt_ov5_platform_support(fdt, chosen);
1021
1022 g_free(stdout_path);
1023 g_free(bootlist);
1024}
1025
1026static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt)
1027{
1028
1029
1030 int hypervisor;
1031 uint8_t hypercall[16];
1032
1033 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor"));
1034
1035 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm"));
1036 if (kvmppc_has_cap_fixup_hcalls()) {
1037
1038
1039
1040
1041 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
1042 sizeof(hypercall))) {
1043 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions",
1044 hypercall, sizeof(hypercall)));
1045 }
1046 }
1047}
1048
1049static void *spapr_build_fdt(sPAPRMachineState *spapr,
1050 hwaddr rtas_addr,
1051 hwaddr rtas_size)
1052{
1053 MachineState *machine = MACHINE(qdev_get_machine());
1054 MachineClass *mc = MACHINE_GET_CLASS(machine);
1055 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1056 int ret;
1057 void *fdt;
1058 sPAPRPHBState *phb;
1059 char *buf;
1060
1061 fdt = g_malloc0(FDT_MAX_SIZE);
1062 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
1063
1064
1065 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp"));
1066 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)"));
1067 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries"));
1068
1069
1070
1071
1072
1073 if (kvmppc_get_host_model(&buf)) {
1074 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf));
1075 g_free(buf);
1076 }
1077 if (kvmppc_get_host_serial(&buf)) {
1078 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf));
1079 g_free(buf);
1080 }
1081
1082 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
1083
1084 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf));
1085 if (qemu_uuid_set) {
1086 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf));
1087 }
1088 g_free(buf);
1089
1090 if (qemu_get_vm_name()) {
1091 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name",
1092 qemu_get_vm_name()));
1093 }
1094
1095 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2));
1096 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2));
1097
1098
1099 spapr_dt_xics(xics_max_server_number(), fdt, PHANDLE_XICP);
1100
1101 ret = spapr_populate_memory(spapr, fdt);
1102 if (ret < 0) {
1103 error_report("couldn't setup memory nodes in fdt");
1104 exit(1);
1105 }
1106
1107
1108 spapr_dt_vdevice(spapr->vio_bus, fdt);
1109
1110 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
1111 ret = spapr_rng_populate_dt(fdt);
1112 if (ret < 0) {
1113 error_report("could not set up rng device in the fdt");
1114 exit(1);
1115 }
1116 }
1117
1118 QLIST_FOREACH(phb, &spapr->phbs, list) {
1119 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
1120 if (ret < 0) {
1121 error_report("couldn't setup PCI devices in fdt");
1122 exit(1);
1123 }
1124 }
1125
1126
1127 spapr_populate_cpus_dt_node(fdt, spapr);
1128
1129 if (smc->dr_lmb_enabled) {
1130 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
1131 }
1132
1133 if (mc->has_hotpluggable_cpus) {
1134 int offset = fdt_path_offset(fdt, "/cpus");
1135 ret = spapr_drc_populate_dt(fdt, offset, NULL,
1136 SPAPR_DR_CONNECTOR_TYPE_CPU);
1137 if (ret < 0) {
1138 error_report("Couldn't set up CPU DR device tree properties");
1139 exit(1);
1140 }
1141 }
1142
1143
1144 spapr_dt_events(spapr, fdt);
1145
1146
1147 spapr_dt_rtas(spapr, fdt);
1148
1149
1150 spapr_dt_chosen(spapr, fdt);
1151
1152
1153 if (kvm_enabled()) {
1154 spapr_dt_hypervisor(spapr, fdt);
1155 }
1156
1157
1158 if (spapr->kernel_size) {
1159 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size)));
1160 }
1161 if (spapr->initrd_size) {
1162 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size)));
1163 }
1164
1165
1166 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas);
1167 if (ret < 0) {
1168 error_report("couldn't setup CAS properties fdt");
1169 exit(1);
1170 }
1171
1172 return fdt;
1173}
1174
1175static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1176{
1177 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1178}
1179
1180static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,
1181 PowerPCCPU *cpu)
1182{
1183 CPUPPCState *env = &cpu->env;
1184
1185
1186 g_assert(qemu_mutex_iothread_locked());
1187
1188 if (msr_pr) {
1189 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1190 env->gpr[3] = H_PRIVILEGE;
1191 } else {
1192 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1193 }
1194}
1195
1196static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp)
1197{
1198 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1199
1200 return spapr->patb_entry;
1201}
1202
1203#define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1204#define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1205#define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1206#define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1207#define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1208
1209
1210
1211
1212static int get_htab_fd(sPAPRMachineState *spapr)
1213{
1214 if (spapr->htab_fd >= 0) {
1215 return spapr->htab_fd;
1216 }
1217
1218 spapr->htab_fd = kvmppc_get_htab_fd(false);
1219 if (spapr->htab_fd < 0) {
1220 error_report("Unable to open fd for reading hash table from KVM: %s",
1221 strerror(errno));
1222 }
1223
1224 return spapr->htab_fd;
1225}
1226
1227void close_htab_fd(sPAPRMachineState *spapr)
1228{
1229 if (spapr->htab_fd >= 0) {
1230 close(spapr->htab_fd);
1231 }
1232 spapr->htab_fd = -1;
1233}
1234
1235static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp)
1236{
1237 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1238
1239 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1;
1240}
1241
1242static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp,
1243 hwaddr ptex, int n)
1244{
1245 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1246 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
1247
1248 if (!spapr->htab) {
1249
1250
1251
1252 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64);
1253 kvmppc_read_hptes(hptes, ptex, n);
1254 return hptes;
1255 }
1256
1257
1258
1259
1260
1261 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset);
1262}
1263
1264static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp,
1265 const ppc_hash_pte64_t *hptes,
1266 hwaddr ptex, int n)
1267{
1268 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1269
1270 if (!spapr->htab) {
1271 g_free((void *)hptes);
1272 }
1273
1274
1275}
1276
1277static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1278 uint64_t pte0, uint64_t pte1)
1279{
1280 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1281 hwaddr offset = ptex * HASH_PTE_SIZE_64;
1282
1283 if (!spapr->htab) {
1284 kvmppc_write_hpte(ptex, pte0, pte1);
1285 } else {
1286 stq_p(spapr->htab + offset, pte0);
1287 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1288 }
1289}
1290
1291int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1292{
1293 int shift;
1294
1295
1296
1297
1298 shift = ctz64(pow2ceil(ramsize)) - 7;
1299 shift = MAX(shift, 18);
1300 shift = MIN(shift, 46);
1301 return shift;
1302}
1303
1304void spapr_free_hpt(sPAPRMachineState *spapr)
1305{
1306 g_free(spapr->htab);
1307 spapr->htab = NULL;
1308 spapr->htab_shift = 0;
1309 close_htab_fd(spapr);
1310}
1311
1312void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
1313 Error **errp)
1314{
1315 long rc;
1316
1317
1318 spapr_free_hpt(spapr);
1319
1320 rc = kvmppc_reset_htab(shift);
1321 if (rc < 0) {
1322
1323 error_setg_errno(errp, errno,
1324 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1325 shift);
1326
1327
1328 } else if (rc > 0) {
1329
1330 if (rc != shift) {
1331 error_setg(errp,
1332 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1333 shift, rc);
1334 }
1335
1336 spapr->htab_shift = shift;
1337 spapr->htab = NULL;
1338 } else {
1339
1340 size_t size = 1ULL << shift;
1341 int i;
1342
1343 spapr->htab = qemu_memalign(size, size);
1344 if (!spapr->htab) {
1345 error_setg_errno(errp, errno,
1346 "Could not allocate HPT of order %d", shift);
1347 return;
1348 }
1349
1350 memset(spapr->htab, 0, size);
1351 spapr->htab_shift = shift;
1352
1353 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1354 DIRTY_HPTE(HPTE(spapr->htab, i));
1355 }
1356 }
1357}
1358
1359void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr)
1360{
1361 int hpt_shift;
1362
1363 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED)
1364 || (spapr->cas_reboot
1365 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) {
1366 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size);
1367 } else {
1368 uint64_t current_ram_size;
1369
1370 current_ram_size = MACHINE(spapr)->ram_size + pc_existing_dimms_capacity(&error_abort);
1371 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size);
1372 }
1373 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal);
1374
1375 if (spapr->vrma_adjust) {
1376 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(),
1377 spapr->htab_shift);
1378 }
1379
1380 spapr->patb_entry = 0;
1381}
1382
1383static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque)
1384{
1385 bool matched = false;
1386
1387 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
1388 matched = true;
1389 }
1390
1391 if (!matched) {
1392 error_report("Device %s is not supported by this machine yet.",
1393 qdev_fw_name(DEVICE(sbdev)));
1394 exit(1);
1395 }
1396}
1397
1398static int spapr_reset_drcs(Object *child, void *opaque)
1399{
1400 sPAPRDRConnector *drc =
1401 (sPAPRDRConnector *) object_dynamic_cast(child,
1402 TYPE_SPAPR_DR_CONNECTOR);
1403
1404 if (drc) {
1405 spapr_drc_reset(drc);
1406 }
1407
1408 return 0;
1409}
1410
1411static void ppc_spapr_reset(void)
1412{
1413 MachineState *machine = MACHINE(qdev_get_machine());
1414 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1415 PowerPCCPU *first_ppc_cpu;
1416 uint32_t rtas_limit;
1417 hwaddr rtas_addr, fdt_addr;
1418 void *fdt;
1419 int rc;
1420
1421
1422 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
1423
1424 first_ppc_cpu = POWERPC_CPU(first_cpu);
1425 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
1426 ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0,
1427 spapr->max_compat_pvr)) {
1428
1429
1430
1431 spapr->patb_entry = PATBE1_GR;
1432 } else {
1433 spapr_setup_hpt_and_vrma(spapr);
1434 }
1435
1436 qemu_devices_reset();
1437
1438
1439
1440
1441
1442
1443 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL);
1444
1445 spapr_clear_pending_events(spapr);
1446
1447
1448
1449
1450
1451
1452 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1453 rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1454 fdt_addr = rtas_addr - FDT_MAX_SIZE;
1455
1456
1457
1458 if (!spapr->cas_reboot) {
1459 spapr_ovec_cleanup(spapr->ov5_cas);
1460 spapr->ov5_cas = spapr_ovec_new();
1461
1462 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal);
1463 }
1464
1465 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size);
1466
1467 spapr_load_rtas(spapr, fdt, rtas_addr);
1468
1469 rc = fdt_pack(fdt);
1470
1471
1472 assert(rc == 0);
1473
1474 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
1475 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1476 fdt_totalsize(fdt), FDT_MAX_SIZE);
1477 exit(1);
1478 }
1479
1480
1481 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
1482 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1483 g_free(fdt);
1484
1485
1486 first_ppc_cpu->env.gpr[3] = fdt_addr;
1487 first_ppc_cpu->env.gpr[5] = 0;
1488 first_cpu->halted = 0;
1489 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT;
1490
1491 spapr->cas_reboot = false;
1492}
1493
1494static void spapr_create_nvram(sPAPRMachineState *spapr)
1495{
1496 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
1497 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1498
1499 if (dinfo) {
1500 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1501 &error_fatal);
1502 }
1503
1504 qdev_init_nofail(dev);
1505
1506 spapr->nvram = (struct sPAPRNVRAM *)dev;
1507}
1508
1509static void spapr_rtc_create(sPAPRMachineState *spapr)
1510{
1511 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC);
1512 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc),
1513 &error_fatal);
1514 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized",
1515 &error_fatal);
1516 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc),
1517 "date", &error_fatal);
1518}
1519
1520
1521static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1522{
1523 switch (vga_interface_type) {
1524 case VGA_NONE:
1525 return false;
1526 case VGA_DEVICE:
1527 return true;
1528 case VGA_STD:
1529 case VGA_VIRTIO:
1530 return pci_vga_init(pci_bus) != NULL;
1531 default:
1532 error_setg(errp,
1533 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1534 return false;
1535 }
1536}
1537
1538static int spapr_post_load(void *opaque, int version_id)
1539{
1540 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1541 int err = 0;
1542
1543 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) {
1544 CPUState *cs;
1545 CPU_FOREACH(cs) {
1546 PowerPCCPU *cpu = POWERPC_CPU(cs);
1547 icp_resend(ICP(cpu->intc));
1548 }
1549 }
1550
1551
1552
1553
1554
1555 if (version_id < 3) {
1556 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset);
1557 }
1558
1559 if (spapr->patb_entry) {
1560 PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
1561 bool radix = !!(spapr->patb_entry & PATBE1_GR);
1562 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE);
1563
1564 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry);
1565 if (err) {
1566 error_report("Process table config unsupported by the host");
1567 return -EINVAL;
1568 }
1569 }
1570
1571 return err;
1572}
1573
1574static bool version_before_3(void *opaque, int version_id)
1575{
1576 return version_id < 3;
1577}
1578
1579static bool spapr_pending_events_needed(void *opaque)
1580{
1581 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1582 return !QTAILQ_EMPTY(&spapr->pending_events);
1583}
1584
1585static const VMStateDescription vmstate_spapr_event_entry = {
1586 .name = "spapr_event_log_entry",
1587 .version_id = 1,
1588 .minimum_version_id = 1,
1589 .fields = (VMStateField[]) {
1590 VMSTATE_UINT32(summary, sPAPREventLogEntry),
1591 VMSTATE_UINT32(extended_length, sPAPREventLogEntry),
1592 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, sPAPREventLogEntry, 0,
1593 NULL, extended_length),
1594 VMSTATE_END_OF_LIST()
1595 },
1596};
1597
1598static const VMStateDescription vmstate_spapr_pending_events = {
1599 .name = "spapr_pending_events",
1600 .version_id = 1,
1601 .minimum_version_id = 1,
1602 .needed = spapr_pending_events_needed,
1603 .fields = (VMStateField[]) {
1604 VMSTATE_QTAILQ_V(pending_events, sPAPRMachineState, 1,
1605 vmstate_spapr_event_entry, sPAPREventLogEntry, next),
1606 VMSTATE_END_OF_LIST()
1607 },
1608};
1609
1610static bool spapr_ov5_cas_needed(void *opaque)
1611{
1612 sPAPRMachineState *spapr = opaque;
1613 sPAPROptionVector *ov5_mask = spapr_ovec_new();
1614 sPAPROptionVector *ov5_legacy = spapr_ovec_new();
1615 sPAPROptionVector *ov5_removed = spapr_ovec_new();
1616 bool cas_needed;
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY);
1643 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY);
1644
1645
1646
1647
1648
1649
1650 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask);
1651 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy);
1652
1653 spapr_ovec_cleanup(ov5_mask);
1654 spapr_ovec_cleanup(ov5_legacy);
1655 spapr_ovec_cleanup(ov5_removed);
1656
1657 return cas_needed;
1658}
1659
1660static const VMStateDescription vmstate_spapr_ov5_cas = {
1661 .name = "spapr_option_vector_ov5_cas",
1662 .version_id = 1,
1663 .minimum_version_id = 1,
1664 .needed = spapr_ov5_cas_needed,
1665 .fields = (VMStateField[]) {
1666 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1,
1667 vmstate_spapr_ovec, sPAPROptionVector),
1668 VMSTATE_END_OF_LIST()
1669 },
1670};
1671
1672static bool spapr_patb_entry_needed(void *opaque)
1673{
1674 sPAPRMachineState *spapr = opaque;
1675
1676 return !!spapr->patb_entry;
1677}
1678
1679static const VMStateDescription vmstate_spapr_patb_entry = {
1680 .name = "spapr_patb_entry",
1681 .version_id = 1,
1682 .minimum_version_id = 1,
1683 .needed = spapr_patb_entry_needed,
1684 .fields = (VMStateField[]) {
1685 VMSTATE_UINT64(patb_entry, sPAPRMachineState),
1686 VMSTATE_END_OF_LIST()
1687 },
1688};
1689
1690static const VMStateDescription vmstate_spapr = {
1691 .name = "spapr",
1692 .version_id = 3,
1693 .minimum_version_id = 1,
1694 .post_load = spapr_post_load,
1695 .fields = (VMStateField[]) {
1696
1697 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
1698
1699
1700 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
1701
1702 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
1703 VMSTATE_END_OF_LIST()
1704 },
1705 .subsections = (const VMStateDescription*[]) {
1706 &vmstate_spapr_ov5_cas,
1707 &vmstate_spapr_patb_entry,
1708 &vmstate_spapr_pending_events,
1709 NULL
1710 }
1711};
1712
1713static int htab_save_setup(QEMUFile *f, void *opaque)
1714{
1715 sPAPRMachineState *spapr = opaque;
1716
1717
1718 if (!spapr->htab_shift) {
1719 qemu_put_be32(f, -1);
1720 } else {
1721 qemu_put_be32(f, spapr->htab_shift);
1722 }
1723
1724 if (spapr->htab) {
1725 spapr->htab_save_index = 0;
1726 spapr->htab_first_pass = true;
1727 } else {
1728 if (spapr->htab_shift) {
1729 assert(kvm_enabled());
1730 }
1731 }
1732
1733
1734 return 0;
1735}
1736
1737static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr,
1738 int64_t max_ns)
1739{
1740 bool has_timeout = max_ns != -1;
1741 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1742 int index = spapr->htab_save_index;
1743 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1744
1745 assert(spapr->htab_first_pass);
1746
1747 do {
1748 int chunkstart;
1749
1750
1751 while ((index < htabslots)
1752 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1753 CLEAN_HPTE(HPTE(spapr->htab, index));
1754 index++;
1755 }
1756
1757
1758 chunkstart = index;
1759 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1760 && HPTE_VALID(HPTE(spapr->htab, index))) {
1761 CLEAN_HPTE(HPTE(spapr->htab, index));
1762 index++;
1763 }
1764
1765 if (index > chunkstart) {
1766 int n_valid = index - chunkstart;
1767
1768 qemu_put_be32(f, chunkstart);
1769 qemu_put_be16(f, n_valid);
1770 qemu_put_be16(f, 0);
1771 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1772 HASH_PTE_SIZE_64 * n_valid);
1773
1774 if (has_timeout &&
1775 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1776 break;
1777 }
1778 }
1779 } while ((index < htabslots) && !qemu_file_rate_limit(f));
1780
1781 if (index >= htabslots) {
1782 assert(index == htabslots);
1783 index = 0;
1784 spapr->htab_first_pass = false;
1785 }
1786 spapr->htab_save_index = index;
1787}
1788
1789static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr,
1790 int64_t max_ns)
1791{
1792 bool final = max_ns < 0;
1793 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1794 int examined = 0, sent = 0;
1795 int index = spapr->htab_save_index;
1796 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1797
1798 assert(!spapr->htab_first_pass);
1799
1800 do {
1801 int chunkstart, invalidstart;
1802
1803
1804 while ((index < htabslots)
1805 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
1806 index++;
1807 examined++;
1808 }
1809
1810 chunkstart = index;
1811
1812 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1813 && HPTE_DIRTY(HPTE(spapr->htab, index))
1814 && HPTE_VALID(HPTE(spapr->htab, index))) {
1815 CLEAN_HPTE(HPTE(spapr->htab, index));
1816 index++;
1817 examined++;
1818 }
1819
1820 invalidstart = index;
1821
1822 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
1823 && HPTE_DIRTY(HPTE(spapr->htab, index))
1824 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1825 CLEAN_HPTE(HPTE(spapr->htab, index));
1826 index++;
1827 examined++;
1828 }
1829
1830 if (index > chunkstart) {
1831 int n_valid = invalidstart - chunkstart;
1832 int n_invalid = index - invalidstart;
1833
1834 qemu_put_be32(f, chunkstart);
1835 qemu_put_be16(f, n_valid);
1836 qemu_put_be16(f, n_invalid);
1837 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1838 HASH_PTE_SIZE_64 * n_valid);
1839 sent += index - chunkstart;
1840
1841 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1842 break;
1843 }
1844 }
1845
1846 if (examined >= htabslots) {
1847 break;
1848 }
1849
1850 if (index >= htabslots) {
1851 assert(index == htabslots);
1852 index = 0;
1853 }
1854 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
1855
1856 if (index >= htabslots) {
1857 assert(index == htabslots);
1858 index = 0;
1859 }
1860
1861 spapr->htab_save_index = index;
1862
1863 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
1864}
1865
1866#define MAX_ITERATION_NS 5000000
1867#define MAX_KVM_BUF_SIZE 2048
1868
1869static int htab_save_iterate(QEMUFile *f, void *opaque)
1870{
1871 sPAPRMachineState *spapr = opaque;
1872 int fd;
1873 int rc = 0;
1874
1875
1876 if (!spapr->htab_shift) {
1877 qemu_put_be32(f, -1);
1878 return 1;
1879 } else {
1880 qemu_put_be32(f, 0);
1881 }
1882
1883 if (!spapr->htab) {
1884 assert(kvm_enabled());
1885
1886 fd = get_htab_fd(spapr);
1887 if (fd < 0) {
1888 return fd;
1889 }
1890
1891 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
1892 if (rc < 0) {
1893 return rc;
1894 }
1895 } else if (spapr->htab_first_pass) {
1896 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
1897 } else {
1898 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
1899 }
1900
1901
1902 qemu_put_be32(f, 0);
1903 qemu_put_be16(f, 0);
1904 qemu_put_be16(f, 0);
1905
1906 return rc;
1907}
1908
1909static int htab_save_complete(QEMUFile *f, void *opaque)
1910{
1911 sPAPRMachineState *spapr = opaque;
1912 int fd;
1913
1914
1915 if (!spapr->htab_shift) {
1916 qemu_put_be32(f, -1);
1917 return 0;
1918 } else {
1919 qemu_put_be32(f, 0);
1920 }
1921
1922 if (!spapr->htab) {
1923 int rc;
1924
1925 assert(kvm_enabled());
1926
1927 fd = get_htab_fd(spapr);
1928 if (fd < 0) {
1929 return fd;
1930 }
1931
1932 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
1933 if (rc < 0) {
1934 return rc;
1935 }
1936 } else {
1937 if (spapr->htab_first_pass) {
1938 htab_save_first_pass(f, spapr, -1);
1939 }
1940 htab_save_later_pass(f, spapr, -1);
1941 }
1942
1943
1944 qemu_put_be32(f, 0);
1945 qemu_put_be16(f, 0);
1946 qemu_put_be16(f, 0);
1947
1948 return 0;
1949}
1950
1951static int htab_load(QEMUFile *f, void *opaque, int version_id)
1952{
1953 sPAPRMachineState *spapr = opaque;
1954 uint32_t section_hdr;
1955 int fd = -1;
1956
1957 if (version_id < 1 || version_id > 1) {
1958 error_report("htab_load() bad version");
1959 return -EINVAL;
1960 }
1961
1962 section_hdr = qemu_get_be32(f);
1963
1964 if (section_hdr == -1) {
1965 spapr_free_hpt(spapr);
1966 return 0;
1967 }
1968
1969 if (section_hdr) {
1970 Error *local_err = NULL;
1971
1972
1973 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
1974 if (local_err) {
1975 error_report_err(local_err);
1976 return -EINVAL;
1977 }
1978 return 0;
1979 }
1980
1981 if (!spapr->htab) {
1982 assert(kvm_enabled());
1983
1984 fd = kvmppc_get_htab_fd(true);
1985 if (fd < 0) {
1986 error_report("Unable to open fd to restore KVM hash table: %s",
1987 strerror(errno));
1988 }
1989 }
1990
1991 while (true) {
1992 uint32_t index;
1993 uint16_t n_valid, n_invalid;
1994
1995 index = qemu_get_be32(f);
1996 n_valid = qemu_get_be16(f);
1997 n_invalid = qemu_get_be16(f);
1998
1999 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
2000
2001 break;
2002 }
2003
2004 if ((index + n_valid + n_invalid) >
2005 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
2006
2007 error_report(
2008 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2009 index, n_valid, n_invalid, spapr->htab_shift);
2010 return -EINVAL;
2011 }
2012
2013 if (spapr->htab) {
2014 if (n_valid) {
2015 qemu_get_buffer(f, HPTE(spapr->htab, index),
2016 HASH_PTE_SIZE_64 * n_valid);
2017 }
2018 if (n_invalid) {
2019 memset(HPTE(spapr->htab, index + n_valid), 0,
2020 HASH_PTE_SIZE_64 * n_invalid);
2021 }
2022 } else {
2023 int rc;
2024
2025 assert(fd >= 0);
2026
2027 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
2028 if (rc < 0) {
2029 return rc;
2030 }
2031 }
2032 }
2033
2034 if (!spapr->htab) {
2035 assert(fd >= 0);
2036 close(fd);
2037 }
2038
2039 return 0;
2040}
2041
2042static void htab_save_cleanup(void *opaque)
2043{
2044 sPAPRMachineState *spapr = opaque;
2045
2046 close_htab_fd(spapr);
2047}
2048
2049static SaveVMHandlers savevm_htab_handlers = {
2050 .save_setup = htab_save_setup,
2051 .save_live_iterate = htab_save_iterate,
2052 .save_live_complete_precopy = htab_save_complete,
2053 .save_cleanup = htab_save_cleanup,
2054 .load_state = htab_load,
2055};
2056
2057static void spapr_boot_set(void *opaque, const char *boot_device,
2058 Error **errp)
2059{
2060 MachineState *machine = MACHINE(qdev_get_machine());
2061 machine->boot_order = g_strdup(boot_device);
2062}
2063
2064static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
2065{
2066 MachineState *machine = MACHINE(spapr);
2067 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
2068 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
2069 int i;
2070
2071 for (i = 0; i < nr_lmbs; i++) {
2072 uint64_t addr;
2073
2074 addr = i * lmb_size + spapr->hotplug_memory.base;
2075 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB,
2076 addr / lmb_size);
2077 }
2078}
2079
2080
2081
2082
2083
2084
2085static void spapr_validate_node_memory(MachineState *machine, Error **errp)
2086{
2087 int i;
2088
2089 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2090 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
2091 " is not aligned to %llu MiB",
2092 machine->ram_size,
2093 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
2094 return;
2095 }
2096
2097 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2098 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
2099 " is not aligned to %llu MiB",
2100 machine->ram_size,
2101 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
2102 return;
2103 }
2104
2105 for (i = 0; i < nb_numa_nodes; i++) {
2106 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
2107 error_setg(errp,
2108 "Node %d memory size 0x%" PRIx64
2109 " is not aligned to %llu MiB",
2110 i, numa_info[i].node_mem,
2111 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
2112 return;
2113 }
2114 }
2115}
2116
2117
2118static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
2119{
2120 int index = id / smp_threads;
2121
2122 if (index >= ms->possible_cpus->len) {
2123 return NULL;
2124 }
2125 if (idx) {
2126 *idx = index;
2127 }
2128 return &ms->possible_cpus->cpus[index];
2129}
2130
2131static void spapr_init_cpus(sPAPRMachineState *spapr)
2132{
2133 MachineState *machine = MACHINE(spapr);
2134 MachineClass *mc = MACHINE_GET_CLASS(machine);
2135 char *type = spapr_get_cpu_core_type(machine->cpu_model);
2136 int smt = kvmppc_smt_threads();
2137 const CPUArchIdList *possible_cpus;
2138 int boot_cores_nr = smp_cpus / smp_threads;
2139 int i;
2140
2141 if (!type) {
2142 error_report("Unable to find sPAPR CPU Core definition");
2143 exit(1);
2144 }
2145
2146 possible_cpus = mc->possible_cpu_arch_ids(machine);
2147 if (mc->has_hotpluggable_cpus) {
2148 if (smp_cpus % smp_threads) {
2149 error_report("smp_cpus (%u) must be multiple of threads (%u)",
2150 smp_cpus, smp_threads);
2151 exit(1);
2152 }
2153 if (max_cpus % smp_threads) {
2154 error_report("max_cpus (%u) must be multiple of threads (%u)",
2155 max_cpus, smp_threads);
2156 exit(1);
2157 }
2158 } else {
2159 if (max_cpus != smp_cpus) {
2160 error_report("This machine version does not support CPU hotplug");
2161 exit(1);
2162 }
2163 boot_cores_nr = possible_cpus->len;
2164 }
2165
2166 for (i = 0; i < possible_cpus->len; i++) {
2167 int core_id = i * smp_threads;
2168
2169 if (mc->has_hotpluggable_cpus) {
2170 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU,
2171 (core_id / smp_threads) * smt);
2172 }
2173
2174 if (i < boot_cores_nr) {
2175 Object *core = object_new(type);
2176 int nr_threads = smp_threads;
2177
2178
2179 if ((i + 1) * smp_threads >= smp_cpus) {
2180 nr_threads = smp_cpus - i * smp_threads;
2181 }
2182
2183 object_property_set_int(core, nr_threads, "nr-threads",
2184 &error_fatal);
2185 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
2186 &error_fatal);
2187 object_property_set_bool(core, true, "realized", &error_fatal);
2188 }
2189 }
2190 g_free(type);
2191}
2192
2193
2194static void ppc_spapr_init(MachineState *machine)
2195{
2196 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
2197 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2198 const char *kernel_filename = machine->kernel_filename;
2199 const char *initrd_filename = machine->initrd_filename;
2200 PCIHostState *phb;
2201 int i;
2202 MemoryRegion *sysmem = get_system_memory();
2203 MemoryRegion *ram = g_new(MemoryRegion, 1);
2204 MemoryRegion *rma_region;
2205 void *rma = NULL;
2206 hwaddr rma_alloc_size;
2207 hwaddr node0_size = spapr_node0_size();
2208 long load_limit, fw_size;
2209 char *filename;
2210 Error *resize_hpt_err = NULL;
2211
2212 msi_nonbroken = true;
2213
2214 QLIST_INIT(&spapr->phbs);
2215 QTAILQ_INIT(&spapr->pending_dimm_unplugs);
2216
2217
2218 kvmppc_check_papr_resize_hpt(&resize_hpt_err);
2219 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) {
2220
2221
2222
2223
2224
2225
2226 if (resize_hpt_err) {
2227 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
2228 error_free(resize_hpt_err);
2229 resize_hpt_err = NULL;
2230 } else {
2231 spapr->resize_hpt = smc->resize_hpt_default;
2232 }
2233 }
2234
2235 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT);
2236
2237 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) {
2238
2239
2240
2241 error_report_err(resize_hpt_err);
2242 exit(1);
2243 }
2244
2245
2246 rma_alloc_size = kvmppc_alloc_rma(&rma);
2247
2248 if (rma_alloc_size == -1) {
2249 error_report("Unable to create RMA");
2250 exit(1);
2251 }
2252
2253 if (rma_alloc_size && (rma_alloc_size < node0_size)) {
2254 spapr->rma_size = rma_alloc_size;
2255 } else {
2256 spapr->rma_size = node0_size;
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267 if (kvm_enabled()) {
2268 spapr->vrma_adjust = 1;
2269 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
2270 }
2271
2272
2273
2274
2275
2276
2277 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull);
2278 }
2279
2280 if (spapr->rma_size > node0_size) {
2281 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
2282 spapr->rma_size);
2283 exit(1);
2284 }
2285
2286
2287 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
2288
2289
2290 xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal);
2291
2292
2293 spapr->ov5 = spapr_ovec_new();
2294 spapr->ov5_cas = spapr_ovec_new();
2295
2296 if (smc->dr_lmb_enabled) {
2297 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY);
2298 spapr_validate_node_memory(machine, &error_fatal);
2299 }
2300
2301 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY);
2302 if (!kvm_enabled() || kvmppc_has_cap_mmu_radix()) {
2303
2304 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE);
2305 }
2306
2307
2308
2309 if (spapr->use_hotplug_event_source) {
2310 spapr_ovec_set(spapr->ov5, OV5_HP_EVT);
2311 }
2312
2313
2314 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
2315 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE);
2316 }
2317
2318
2319 if (machine->cpu_model == NULL) {
2320 machine->cpu_model = kvm_enabled() ? "host" : smc->tcg_default_cpu;
2321 }
2322
2323 spapr_cpu_parse_features(spapr);
2324
2325 spapr_init_cpus(spapr);
2326
2327 if (kvm_enabled()) {
2328
2329 kvmppc_enable_logical_ci_hcalls();
2330 kvmppc_enable_set_mode_hcall();
2331
2332
2333 kvmppc_enable_clear_ref_mod_hcalls();
2334 }
2335
2336
2337 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
2338 machine->ram_size);
2339 memory_region_add_subregion(sysmem, 0, ram);
2340
2341 if (rma_alloc_size && rma) {
2342 rma_region = g_new(MemoryRegion, 1);
2343 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma",
2344 rma_alloc_size, rma);
2345 vmstate_register_ram_global(rma_region);
2346 memory_region_add_subregion(sysmem, 0, rma_region);
2347 }
2348
2349
2350 if (machine->ram_size < machine->maxram_size) {
2351 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size;
2352
2353
2354
2355
2356
2357 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
2358 SPAPR_MAX_RAM_SLOTS;
2359
2360 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
2361 max_memslots = SPAPR_MAX_RAM_SLOTS;
2362 }
2363 if (machine->ram_slots > max_memslots) {
2364 error_report("Specified number of memory slots %"
2365 PRIu64" exceeds max supported %d",
2366 machine->ram_slots, max_memslots);
2367 exit(1);
2368 }
2369
2370 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size,
2371 SPAPR_HOTPLUG_MEM_ALIGN);
2372 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr),
2373 "hotplug-memory", hotplug_mem_size);
2374 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base,
2375 &spapr->hotplug_memory.mr);
2376 }
2377
2378 if (smc->dr_lmb_enabled) {
2379 spapr_create_lmb_dr_connectors(spapr);
2380 }
2381
2382 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
2383 if (!filename) {
2384 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
2385 exit(1);
2386 }
2387 spapr->rtas_size = get_image_size(filename);
2388 if (spapr->rtas_size < 0) {
2389 error_report("Could not get size of LPAR rtas '%s'", filename);
2390 exit(1);
2391 }
2392 spapr->rtas_blob = g_malloc(spapr->rtas_size);
2393 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
2394 error_report("Could not load LPAR rtas '%s'", filename);
2395 exit(1);
2396 }
2397 if (spapr->rtas_size > RTAS_MAX_SIZE) {
2398 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
2399 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
2400 exit(1);
2401 }
2402 g_free(filename);
2403
2404
2405 spapr_events_init(spapr);
2406
2407
2408 spapr_rtc_create(spapr);
2409
2410
2411 spapr->vio_bus = spapr_vio_bus_init();
2412
2413 for (i = 0; i < MAX_SERIAL_PORTS; i++) {
2414 if (serial_hds[i]) {
2415 spapr_vty_create(spapr->vio_bus, serial_hds[i]);
2416 }
2417 }
2418
2419
2420 spapr_create_nvram(spapr);
2421
2422
2423 spapr_pci_rtas_init();
2424
2425 phb = spapr_create_phb(spapr, 0);
2426
2427 for (i = 0; i < nb_nics; i++) {
2428 NICInfo *nd = &nd_table[i];
2429
2430 if (!nd->model) {
2431 nd->model = g_strdup("ibmveth");
2432 }
2433
2434 if (strcmp(nd->model, "ibmveth") == 0) {
2435 spapr_vlan_create(spapr->vio_bus, nd);
2436 } else {
2437 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
2438 }
2439 }
2440
2441 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
2442 spapr_vscsi_create(spapr->vio_bus);
2443 }
2444
2445
2446 if (spapr_vga_init(phb->bus, &error_fatal)) {
2447 spapr->has_graphics = true;
2448 machine->usb |= defaults_enabled() && !machine->usb_disabled;
2449 }
2450
2451 if (machine->usb) {
2452 if (smc->use_ohci_by_default) {
2453 pci_create_simple(phb->bus, -1, "pci-ohci");
2454 } else {
2455 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
2456 }
2457
2458 if (spapr->has_graphics) {
2459 USBBus *usb_bus = usb_bus_find(-1);
2460
2461 usb_create_simple(usb_bus, "usb-kbd");
2462 usb_create_simple(usb_bus, "usb-mouse");
2463 }
2464 }
2465
2466 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
2467 error_report(
2468 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
2469 MIN_RMA_SLOF);
2470 exit(1);
2471 }
2472
2473 if (kernel_filename) {
2474 uint64_t lowaddr = 0;
2475
2476 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address,
2477 NULL, NULL, &lowaddr, NULL, 1,
2478 PPC_ELF_MACHINE, 0, 0);
2479 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) {
2480 spapr->kernel_size = load_elf(kernel_filename,
2481 translate_kernel_address, NULL, NULL,
2482 &lowaddr, NULL, 0, PPC_ELF_MACHINE,
2483 0, 0);
2484 spapr->kernel_le = spapr->kernel_size > 0;
2485 }
2486 if (spapr->kernel_size < 0) {
2487 error_report("error loading %s: %s", kernel_filename,
2488 load_elf_strerror(spapr->kernel_size));
2489 exit(1);
2490 }
2491
2492
2493 if (initrd_filename) {
2494
2495
2496
2497 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size
2498 + 0x1ffff) & ~0xffff;
2499 spapr->initrd_size = load_image_targphys(initrd_filename,
2500 spapr->initrd_base,
2501 load_limit
2502 - spapr->initrd_base);
2503 if (spapr->initrd_size < 0) {
2504 error_report("could not load initial ram disk '%s'",
2505 initrd_filename);
2506 exit(1);
2507 }
2508 }
2509 }
2510
2511 if (bios_name == NULL) {
2512 bios_name = FW_FILE_NAME;
2513 }
2514 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
2515 if (!filename) {
2516 error_report("Could not find LPAR firmware '%s'", bios_name);
2517 exit(1);
2518 }
2519 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
2520 if (fw_size <= 0) {
2521 error_report("Could not load LPAR firmware '%s'", filename);
2522 exit(1);
2523 }
2524 g_free(filename);
2525
2526
2527
2528
2529 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
2530 register_savevm_live(NULL, "spapr/htab", -1, 1,
2531 &savevm_htab_handlers, spapr);
2532
2533 qemu_register_boot_set(spapr_boot_set, spapr);
2534
2535 if (kvm_enabled()) {
2536
2537 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change,
2538 &spapr->tb);
2539
2540 kvmppc_spapr_enable_inkernel_multitce();
2541 }
2542}
2543
2544static int spapr_kvm_type(const char *vm_type)
2545{
2546 if (!vm_type) {
2547 return 0;
2548 }
2549
2550 if (!strcmp(vm_type, "HV")) {
2551 return 1;
2552 }
2553
2554 if (!strcmp(vm_type, "PR")) {
2555 return 2;
2556 }
2557
2558 error_report("Unknown kvm-type specified '%s'", vm_type);
2559 exit(1);
2560}
2561
2562
2563
2564
2565
2566static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
2567 DeviceState *dev)
2568{
2569#define CAST(type, obj, name) \
2570 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2571 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
2572 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
2573 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON);
2574
2575 if (d) {
2576 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
2577 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
2578 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
2579
2580 if (spapr) {
2581
2582
2583
2584
2585
2586 unsigned id = 0x8000 | (d->id << 8) | d->lun;
2587 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2588 (uint64_t)id << 48);
2589 } else if (virtio) {
2590
2591
2592
2593
2594
2595
2596
2597 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
2598 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2599 (uint64_t)id << 32);
2600 } else if (usb) {
2601
2602
2603
2604
2605 unsigned usb_port = atoi(usb->port->path);
2606 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
2607 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2608 (uint64_t)id << 32);
2609 }
2610 }
2611
2612
2613
2614
2615
2616
2617
2618 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) {
2619 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE);
2620 if (usb_host_dev_is_scsi_storage(usbdev)) {
2621 return g_strdup_printf("storage@%s/disk", usbdev->port->path);
2622 }
2623 }
2624
2625 if (phb) {
2626
2627 return g_strdup_printf("pci@%"PRIX64, phb->buid);
2628 }
2629
2630 if (vsc) {
2631
2632 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun;
2633 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32);
2634 }
2635
2636 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) {
2637
2638 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE);
2639 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn));
2640 }
2641
2642 return NULL;
2643}
2644
2645static char *spapr_get_kvm_type(Object *obj, Error **errp)
2646{
2647 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2648
2649 return g_strdup(spapr->kvm_type);
2650}
2651
2652static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
2653{
2654 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2655
2656 g_free(spapr->kvm_type);
2657 spapr->kvm_type = g_strdup(value);
2658}
2659
2660static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp)
2661{
2662 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2663
2664 return spapr->use_hotplug_event_source;
2665}
2666
2667static void spapr_set_modern_hotplug_events(Object *obj, bool value,
2668 Error **errp)
2669{
2670 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2671
2672 spapr->use_hotplug_event_source = value;
2673}
2674
2675static char *spapr_get_resize_hpt(Object *obj, Error **errp)
2676{
2677 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2678
2679 switch (spapr->resize_hpt) {
2680 case SPAPR_RESIZE_HPT_DEFAULT:
2681 return g_strdup("default");
2682 case SPAPR_RESIZE_HPT_DISABLED:
2683 return g_strdup("disabled");
2684 case SPAPR_RESIZE_HPT_ENABLED:
2685 return g_strdup("enabled");
2686 case SPAPR_RESIZE_HPT_REQUIRED:
2687 return g_strdup("required");
2688 }
2689 g_assert_not_reached();
2690}
2691
2692static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp)
2693{
2694 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2695
2696 if (strcmp(value, "default") == 0) {
2697 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT;
2698 } else if (strcmp(value, "disabled") == 0) {
2699 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
2700 } else if (strcmp(value, "enabled") == 0) {
2701 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED;
2702 } else if (strcmp(value, "required") == 0) {
2703 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED;
2704 } else {
2705 error_setg(errp, "Bad value for \"resize-hpt\" property");
2706 }
2707}
2708
2709static void spapr_machine_initfn(Object *obj)
2710{
2711 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2712
2713 spapr->htab_fd = -1;
2714 spapr->use_hotplug_event_source = true;
2715 object_property_add_str(obj, "kvm-type",
2716 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
2717 object_property_set_description(obj, "kvm-type",
2718 "Specifies the KVM virtualization mode (HV, PR)",
2719 NULL);
2720 object_property_add_bool(obj, "modern-hotplug-events",
2721 spapr_get_modern_hotplug_events,
2722 spapr_set_modern_hotplug_events,
2723 NULL);
2724 object_property_set_description(obj, "modern-hotplug-events",
2725 "Use dedicated hotplug event mechanism in"
2726 " place of standard EPOW events when possible"
2727 " (required for memory hot-unplug support)",
2728 NULL);
2729
2730 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr,
2731 "Maximum permitted CPU compatibility mode",
2732 &error_fatal);
2733
2734 object_property_add_str(obj, "resize-hpt",
2735 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL);
2736 object_property_set_description(obj, "resize-hpt",
2737 "Resizing of the Hash Page Table (enabled, disabled, required)",
2738 NULL);
2739}
2740
2741static void spapr_machine_finalizefn(Object *obj)
2742{
2743 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2744
2745 g_free(spapr->kvm_type);
2746}
2747
2748void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg)
2749{
2750 cpu_synchronize_state(cs);
2751 ppc_cpu_do_system_reset(cs);
2752}
2753
2754static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
2755{
2756 CPUState *cs;
2757
2758 CPU_FOREACH(cs) {
2759 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
2760 }
2761}
2762
2763static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size,
2764 uint32_t node, bool dedicated_hp_event_source,
2765 Error **errp)
2766{
2767 sPAPRDRConnector *drc;
2768 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
2769 int i, fdt_offset, fdt_size;
2770 void *fdt;
2771 uint64_t addr = addr_start;
2772 bool hotplugged = spapr_drc_hotplugged(dev);
2773 Error *local_err = NULL;
2774
2775 for (i = 0; i < nr_lmbs; i++) {
2776 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
2777 addr / SPAPR_MEMORY_BLOCK_SIZE);
2778 g_assert(drc);
2779
2780 fdt = create_device_tree(&fdt_size);
2781 fdt_offset = spapr_populate_memory_node(fdt, node, addr,
2782 SPAPR_MEMORY_BLOCK_SIZE);
2783
2784 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err);
2785 if (local_err) {
2786 while (addr > addr_start) {
2787 addr -= SPAPR_MEMORY_BLOCK_SIZE;
2788 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
2789 addr / SPAPR_MEMORY_BLOCK_SIZE);
2790 spapr_drc_detach(drc);
2791 }
2792 g_free(fdt);
2793 error_propagate(errp, local_err);
2794 return;
2795 }
2796 if (!hotplugged) {
2797 spapr_drc_reset(drc);
2798 }
2799 addr += SPAPR_MEMORY_BLOCK_SIZE;
2800 }
2801
2802
2803
2804 if (hotplugged) {
2805 if (dedicated_hp_event_source) {
2806 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
2807 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
2808 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
2809 nr_lmbs,
2810 spapr_drc_index(drc));
2811 } else {
2812 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB,
2813 nr_lmbs);
2814 }
2815 }
2816}
2817
2818static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2819 uint32_t node, Error **errp)
2820{
2821 Error *local_err = NULL;
2822 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
2823 PCDIMMDevice *dimm = PC_DIMM(dev);
2824 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2825 MemoryRegion *mr;
2826 uint64_t align, size, addr;
2827
2828 mr = ddc->get_memory_region(dimm, &local_err);
2829 if (local_err) {
2830 goto out;
2831 }
2832 align = memory_region_get_alignment(mr);
2833 size = memory_region_size(mr);
2834
2835 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err);
2836 if (local_err) {
2837 goto out;
2838 }
2839
2840 addr = object_property_get_uint(OBJECT(dimm),
2841 PC_DIMM_ADDR_PROP, &local_err);
2842 if (local_err) {
2843 goto out_unplug;
2844 }
2845
2846 spapr_add_lmbs(dev, addr, size, node,
2847 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT),
2848 &local_err);
2849 if (local_err) {
2850 goto out_unplug;
2851 }
2852
2853 return;
2854
2855out_unplug:
2856 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
2857out:
2858 error_propagate(errp, local_err);
2859}
2860
2861static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2862 Error **errp)
2863{
2864 PCDIMMDevice *dimm = PC_DIMM(dev);
2865 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2866 MemoryRegion *mr;
2867 uint64_t size;
2868 char *mem_dev;
2869
2870 mr = ddc->get_memory_region(dimm, errp);
2871 if (!mr) {
2872 return;
2873 }
2874 size = memory_region_size(mr);
2875
2876 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
2877 error_setg(errp, "Hotplugged memory size must be a multiple of "
2878 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
2879 return;
2880 }
2881
2882 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL);
2883 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) {
2884 error_setg(errp, "Memory backend has bad page size. "
2885 "Use 'memory-backend-file' with correct mem-path.");
2886 goto out;
2887 }
2888
2889out:
2890 g_free(mem_dev);
2891}
2892
2893struct sPAPRDIMMState {
2894 PCDIMMDevice *dimm;
2895 uint32_t nr_lmbs;
2896 QTAILQ_ENTRY(sPAPRDIMMState) next;
2897};
2898
2899static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s,
2900 PCDIMMDevice *dimm)
2901{
2902 sPAPRDIMMState *dimm_state = NULL;
2903
2904 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) {
2905 if (dimm_state->dimm == dimm) {
2906 break;
2907 }
2908 }
2909 return dimm_state;
2910}
2911
2912static sPAPRDIMMState *spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr,
2913 uint32_t nr_lmbs,
2914 PCDIMMDevice *dimm)
2915{
2916 sPAPRDIMMState *ds = NULL;
2917
2918
2919
2920
2921
2922
2923
2924 ds = spapr_pending_dimm_unplugs_find(spapr, dimm);
2925 if (!ds) {
2926 ds = g_malloc0(sizeof(sPAPRDIMMState));
2927 ds->nr_lmbs = nr_lmbs;
2928 ds->dimm = dimm;
2929 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next);
2930 }
2931 return ds;
2932}
2933
2934static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr,
2935 sPAPRDIMMState *dimm_state)
2936{
2937 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next);
2938 g_free(dimm_state);
2939}
2940
2941static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms,
2942 PCDIMMDevice *dimm)
2943{
2944 sPAPRDRConnector *drc;
2945 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2946 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort);
2947 uint64_t size = memory_region_size(mr);
2948 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
2949 uint32_t avail_lmbs = 0;
2950 uint64_t addr_start, addr;
2951 int i;
2952
2953 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP,
2954 &error_abort);
2955
2956 addr = addr_start;
2957 for (i = 0; i < nr_lmbs; i++) {
2958 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
2959 addr / SPAPR_MEMORY_BLOCK_SIZE);
2960 g_assert(drc);
2961 if (drc->dev) {
2962 avail_lmbs++;
2963 }
2964 addr += SPAPR_MEMORY_BLOCK_SIZE;
2965 }
2966
2967 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm);
2968}
2969
2970
2971void spapr_lmb_release(DeviceState *dev)
2972{
2973 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_hotplug_handler(dev));
2974 PCDIMMDevice *dimm = PC_DIMM(dev);
2975 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2976 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort);
2977 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev));
2978
2979
2980
2981 if (ds == NULL) {
2982 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev));
2983 g_assert(ds);
2984
2985 g_assert(ds->nr_lmbs);
2986 }
2987
2988 if (--ds->nr_lmbs) {
2989 return;
2990 }
2991
2992 spapr_pending_dimm_unplugs_remove(spapr, ds);
2993
2994
2995
2996
2997
2998 pc_dimm_memory_unplug(dev, &spapr->hotplug_memory, mr);
2999 object_unparent(OBJECT(dev));
3000}
3001
3002static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev,
3003 DeviceState *dev, Error **errp)
3004{
3005 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3006 Error *local_err = NULL;
3007 PCDIMMDevice *dimm = PC_DIMM(dev);
3008 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
3009 MemoryRegion *mr;
3010 uint32_t nr_lmbs;
3011 uint64_t size, addr_start, addr;
3012 int i;
3013 sPAPRDRConnector *drc;
3014
3015 mr = ddc->get_memory_region(dimm, &local_err);
3016 if (local_err) {
3017 goto out;
3018 }
3019 size = memory_region_size(mr);
3020 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
3021
3022 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP,
3023 &local_err);
3024 if (local_err) {
3025 goto out;
3026 }
3027
3028 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm);
3029
3030 addr = addr_start;
3031 for (i = 0; i < nr_lmbs; i++) {
3032 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3033 addr / SPAPR_MEMORY_BLOCK_SIZE);
3034 g_assert(drc);
3035
3036 spapr_drc_detach(drc);
3037 addr += SPAPR_MEMORY_BLOCK_SIZE;
3038 }
3039
3040 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3041 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
3042 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
3043 nr_lmbs, spapr_drc_index(drc));
3044out:
3045 error_propagate(errp, local_err);
3046}
3047
3048static void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
3049 sPAPRMachineState *spapr)
3050{
3051 PowerPCCPU *cpu = POWERPC_CPU(cs);
3052 DeviceClass *dc = DEVICE_GET_CLASS(cs);
3053 int id = ppc_get_vcpu_dt_id(cpu);
3054 void *fdt;
3055 int offset, fdt_size;
3056 char *nodename;
3057
3058 fdt = create_device_tree(&fdt_size);
3059 nodename = g_strdup_printf("%s@%x", dc->fw_name, id);
3060 offset = fdt_add_subnode(fdt, 0, nodename);
3061
3062 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
3063 g_free(nodename);
3064
3065 *fdt_offset = offset;
3066 return fdt;
3067}
3068
3069
3070void spapr_core_release(DeviceState *dev)
3071{
3072 MachineState *ms = MACHINE(qdev_get_hotplug_handler(dev));
3073 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms);
3074 CPUCore *cc = CPU_CORE(dev);
3075 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL);
3076
3077 if (smc->pre_2_10_has_unused_icps) {
3078 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
3079 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(cc));
3080 const char *typename = object_class_get_name(scc->cpu_class);
3081 size_t size = object_type_get_instance_size(typename);
3082 int i;
3083
3084 for (i = 0; i < cc->nr_threads; i++) {
3085 CPUState *cs = CPU(sc->threads + i * size);
3086
3087 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index);
3088 }
3089 }
3090
3091 assert(core_slot);
3092 core_slot->cpu = NULL;
3093 object_unparent(OBJECT(dev));
3094}
3095
3096static
3097void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev,
3098 Error **errp)
3099{
3100 int index;
3101 sPAPRDRConnector *drc;
3102 CPUCore *cc = CPU_CORE(dev);
3103 int smt = kvmppc_smt_threads();
3104
3105 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) {
3106 error_setg(errp, "Unable to find CPU core with core-id: %d",
3107 cc->core_id);
3108 return;
3109 }
3110 if (index == 0) {
3111 error_setg(errp, "Boot CPU core may not be unplugged");
3112 return;
3113 }
3114
3115 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index * smt);
3116 g_assert(drc);
3117
3118 spapr_drc_detach(drc);
3119
3120 spapr_hotplug_req_remove_by_index(drc);
3121}
3122
3123static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3124 Error **errp)
3125{
3126 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3127 MachineClass *mc = MACHINE_GET_CLASS(spapr);
3128 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3129 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev));
3130 CPUCore *cc = CPU_CORE(dev);
3131 CPUState *cs = CPU(core->threads);
3132 sPAPRDRConnector *drc;
3133 Error *local_err = NULL;
3134 int smt = kvmppc_smt_threads();
3135 CPUArchId *core_slot;
3136 int index;
3137 bool hotplugged = spapr_drc_hotplugged(dev);
3138
3139 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3140 if (!core_slot) {
3141 error_setg(errp, "Unable to find CPU core with core-id: %d",
3142 cc->core_id);
3143 return;
3144 }
3145 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index * smt);
3146
3147 g_assert(drc || !mc->has_hotpluggable_cpus);
3148
3149 if (drc) {
3150 void *fdt;
3151 int fdt_offset;
3152
3153 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr);
3154
3155 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err);
3156 if (local_err) {
3157 g_free(fdt);
3158 error_propagate(errp, local_err);
3159 return;
3160 }
3161
3162 if (hotplugged) {
3163
3164
3165
3166
3167 spapr_hotplug_req_add_by_index(drc);
3168 } else {
3169 spapr_drc_reset(drc);
3170 }
3171 }
3172
3173 core_slot->cpu = OBJECT(dev);
3174
3175 if (smc->pre_2_10_has_unused_icps) {
3176 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(cc));
3177 const char *typename = object_class_get_name(scc->cpu_class);
3178 size_t size = object_type_get_instance_size(typename);
3179 int i;
3180
3181 for (i = 0; i < cc->nr_threads; i++) {
3182 sPAPRCPUCore *sc = SPAPR_CPU_CORE(dev);
3183 void *obj = sc->threads + i * size;
3184
3185 cs = CPU(obj);
3186 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index);
3187 }
3188 }
3189}
3190
3191static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3192 Error **errp)
3193{
3194 MachineState *machine = MACHINE(OBJECT(hotplug_dev));
3195 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
3196 Error *local_err = NULL;
3197 CPUCore *cc = CPU_CORE(dev);
3198 char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model);
3199 const char *type = object_get_typename(OBJECT(dev));
3200 CPUArchId *core_slot;
3201 int index;
3202
3203 if (dev->hotplugged && !mc->has_hotpluggable_cpus) {
3204 error_setg(&local_err, "CPU hotplug not supported for this machine");
3205 goto out;
3206 }
3207
3208 if (strcmp(base_core_type, type)) {
3209 error_setg(&local_err, "CPU core type should be %s", base_core_type);
3210 goto out;
3211 }
3212
3213 if (cc->core_id % smp_threads) {
3214 error_setg(&local_err, "invalid core id %d", cc->core_id);
3215 goto out;
3216 }
3217
3218
3219
3220
3221
3222
3223
3224 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) {
3225 error_setg(&local_err, "invalid nr-threads %d, must be %d",
3226 cc->nr_threads, smp_threads);
3227 goto out;
3228 }
3229
3230 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3231 if (!core_slot) {
3232 error_setg(&local_err, "core id %d out of range", cc->core_id);
3233 goto out;
3234 }
3235
3236 if (core_slot->cpu) {
3237 error_setg(&local_err, "core %d already populated", cc->core_id);
3238 goto out;
3239 }
3240
3241 numa_cpu_pre_plug(core_slot, dev, &local_err);
3242
3243out:
3244 g_free(base_core_type);
3245 error_propagate(errp, local_err);
3246}
3247
3248static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
3249 DeviceState *dev, Error **errp)
3250{
3251 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
3252
3253 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3254 int node;
3255
3256 if (!smc->dr_lmb_enabled) {
3257 error_setg(errp, "Memory hotplug not supported for this machine");
3258 return;
3259 }
3260 node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP, errp);
3261 if (*errp) {
3262 return;
3263 }
3264 if (node < 0 || node >= MAX_NODES) {
3265 error_setg(errp, "Invaild node %d", node);
3266 return;
3267 }
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285 if (nb_numa_nodes && !numa_info[node].node_mem) {
3286 error_setg(errp, "Can't hotplug memory to memory-less node %d",
3287 node);
3288 return;
3289 }
3290
3291 spapr_memory_plug(hotplug_dev, dev, node, errp);
3292 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3293 spapr_core_plug(hotplug_dev, dev, errp);
3294 }
3295}
3296
3297static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev,
3298 DeviceState *dev, Error **errp)
3299{
3300 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine());
3301 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
3302
3303 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3304 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) {
3305 spapr_memory_unplug_request(hotplug_dev, dev, errp);
3306 } else {
3307
3308
3309
3310
3311
3312
3313 error_setg(errp, "Memory hot unplug not supported for this guest");
3314 }
3315 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3316 if (!mc->has_hotpluggable_cpus) {
3317 error_setg(errp, "CPU hot unplug not supported on this machine");
3318 return;
3319 }
3320 spapr_core_unplug_request(hotplug_dev, dev, errp);
3321 }
3322}
3323
3324static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev,
3325 DeviceState *dev, Error **errp)
3326{
3327 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3328 spapr_memory_pre_plug(hotplug_dev, dev, errp);
3329 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3330 spapr_core_pre_plug(hotplug_dev, dev, errp);
3331 }
3332}
3333
3334static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine,
3335 DeviceState *dev)
3336{
3337 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
3338 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3339 return HOTPLUG_HANDLER(machine);
3340 }
3341 return NULL;
3342}
3343
3344static CpuInstanceProperties
3345spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index)
3346{
3347 CPUArchId *core_slot;
3348 MachineClass *mc = MACHINE_GET_CLASS(machine);
3349
3350
3351 mc->possible_cpu_arch_ids(machine);
3352
3353 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL);
3354 assert(core_slot);
3355 return core_slot->props;
3356}
3357
3358static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine)
3359{
3360 int i;
3361 int spapr_max_cores = max_cpus / smp_threads;
3362 MachineClass *mc = MACHINE_GET_CLASS(machine);
3363
3364 if (!mc->has_hotpluggable_cpus) {
3365 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads;
3366 }
3367 if (machine->possible_cpus) {
3368 assert(machine->possible_cpus->len == spapr_max_cores);
3369 return machine->possible_cpus;
3370 }
3371
3372 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
3373 sizeof(CPUArchId) * spapr_max_cores);
3374 machine->possible_cpus->len = spapr_max_cores;
3375 for (i = 0; i < machine->possible_cpus->len; i++) {
3376 int core_id = i * smp_threads;
3377
3378 machine->possible_cpus->cpus[i].vcpus_count = smp_threads;
3379 machine->possible_cpus->cpus[i].arch_id = core_id;
3380 machine->possible_cpus->cpus[i].props.has_core_id = true;
3381 machine->possible_cpus->cpus[i].props.core_id = core_id;
3382
3383
3384 if (nb_numa_nodes) {
3385
3386
3387
3388 machine->possible_cpus->cpus[i].props.node_id =
3389 core_id / smp_threads / smp_cores % nb_numa_nodes;
3390 }
3391 }
3392 return machine->possible_cpus;
3393}
3394
3395static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index,
3396 uint64_t *buid, hwaddr *pio,
3397 hwaddr *mmio32, hwaddr *mmio64,
3398 unsigned n_dma, uint32_t *liobns, Error **errp)
3399{
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415 const uint64_t base_buid = 0x800000020000000ULL;
3416#define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \
3417 SPAPR_PCI_MEM64_WIN_SIZE - 1)
3418 int i;
3419
3420
3421 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
3422 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
3423 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0);
3424 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0);
3425
3426 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) >
3427 SPAPR_PCI_MEM32_WIN_SIZE);
3428 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) >
3429 SPAPR_PCI_MEM64_WIN_SIZE);
3430
3431 if (index >= SPAPR_MAX_PHBS) {
3432 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)",
3433 SPAPR_MAX_PHBS - 1);
3434 return;
3435 }
3436
3437 *buid = base_buid + index;
3438 for (i = 0; i < n_dma; ++i) {
3439 liobns[i] = SPAPR_PCI_LIOBN(index, i);
3440 }
3441
3442 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE;
3443 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE;
3444 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE;
3445}
3446
3447static ICSState *spapr_ics_get(XICSFabric *dev, int irq)
3448{
3449 sPAPRMachineState *spapr = SPAPR_MACHINE(dev);
3450
3451 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL;
3452}
3453
3454static void spapr_ics_resend(XICSFabric *dev)
3455{
3456 sPAPRMachineState *spapr = SPAPR_MACHINE(dev);
3457
3458 ics_resend(spapr->ics);
3459}
3460
3461static ICPState *spapr_icp_get(XICSFabric *xi, int cpu_dt_id)
3462{
3463 PowerPCCPU *cpu = ppc_get_vcpu_by_dt_id(cpu_dt_id);
3464
3465 return cpu ? ICP(cpu->intc) : NULL;
3466}
3467
3468static void spapr_pic_print_info(InterruptStatsProvider *obj,
3469 Monitor *mon)
3470{
3471 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3472 CPUState *cs;
3473
3474 CPU_FOREACH(cs) {
3475 PowerPCCPU *cpu = POWERPC_CPU(cs);
3476
3477 icp_pic_print_info(ICP(cpu->intc), mon);
3478 }
3479
3480 ics_pic_print_info(spapr->ics, mon);
3481}
3482
3483static void spapr_machine_class_init(ObjectClass *oc, void *data)
3484{
3485 MachineClass *mc = MACHINE_CLASS(oc);
3486 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
3487 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
3488 NMIClass *nc = NMI_CLASS(oc);
3489 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
3490 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc);
3491 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
3492 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
3493
3494 mc->desc = "pSeries Logical Partition (PAPR compliant)";
3495
3496
3497
3498
3499
3500
3501 mc->init = ppc_spapr_init;
3502 mc->reset = ppc_spapr_reset;
3503 mc->block_default_type = IF_SCSI;
3504 mc->max_cpus = 1024;
3505 mc->no_parallel = 1;
3506 mc->default_boot_order = "";
3507 mc->default_ram_size = 512 * M_BYTE;
3508 mc->kvm_type = spapr_kvm_type;
3509 mc->has_dynamic_sysbus = true;
3510 mc->pci_allow_0_address = true;
3511 mc->get_hotplug_handler = spapr_get_hotplug_handler;
3512 hc->pre_plug = spapr_machine_device_pre_plug;
3513 hc->plug = spapr_machine_device_plug;
3514 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props;
3515 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids;
3516 hc->unplug_request = spapr_machine_device_unplug_request;
3517
3518 smc->dr_lmb_enabled = true;
3519 smc->tcg_default_cpu = "POWER8";
3520 mc->has_hotpluggable_cpus = true;
3521 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED;
3522 fwc->get_dev_path = spapr_get_fw_dev_path;
3523 nc->nmi_monitor_handler = spapr_nmi;
3524 smc->phb_placement = spapr_phb_placement;
3525 vhc->hypercall = emulate_spapr_hypercall;
3526 vhc->hpt_mask = spapr_hpt_mask;
3527 vhc->map_hptes = spapr_map_hptes;
3528 vhc->unmap_hptes = spapr_unmap_hptes;
3529 vhc->store_hpte = spapr_store_hpte;
3530 vhc->get_patbe = spapr_get_patbe;
3531 xic->ics_get = spapr_ics_get;
3532 xic->ics_resend = spapr_ics_resend;
3533 xic->icp_get = spapr_icp_get;
3534 ispc->print_info = spapr_pic_print_info;
3535
3536
3537
3538
3539 mc->numa_mem_align_shift = 28;
3540}
3541
3542static const TypeInfo spapr_machine_info = {
3543 .name = TYPE_SPAPR_MACHINE,
3544 .parent = TYPE_MACHINE,
3545 .abstract = true,
3546 .instance_size = sizeof(sPAPRMachineState),
3547 .instance_init = spapr_machine_initfn,
3548 .instance_finalize = spapr_machine_finalizefn,
3549 .class_size = sizeof(sPAPRMachineClass),
3550 .class_init = spapr_machine_class_init,
3551 .interfaces = (InterfaceInfo[]) {
3552 { TYPE_FW_PATH_PROVIDER },
3553 { TYPE_NMI },
3554 { TYPE_HOTPLUG_HANDLER },
3555 { TYPE_PPC_VIRTUAL_HYPERVISOR },
3556 { TYPE_XICS_FABRIC },
3557 { TYPE_INTERRUPT_STATS_PROVIDER },
3558 { }
3559 },
3560};
3561
3562#define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
3563 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
3564 void *data) \
3565 { \
3566 MachineClass *mc = MACHINE_CLASS(oc); \
3567 spapr_machine_##suffix##_class_options(mc); \
3568 if (latest) { \
3569 mc->alias = "pseries"; \
3570 mc->is_default = 1; \
3571 } \
3572 } \
3573 static void spapr_machine_##suffix##_instance_init(Object *obj) \
3574 { \
3575 MachineState *machine = MACHINE(obj); \
3576 spapr_machine_##suffix##_instance_options(machine); \
3577 } \
3578 static const TypeInfo spapr_machine_##suffix##_info = { \
3579 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
3580 .parent = TYPE_SPAPR_MACHINE, \
3581 .class_init = spapr_machine_##suffix##_class_init, \
3582 .instance_init = spapr_machine_##suffix##_instance_init, \
3583 }; \
3584 static void spapr_machine_register_##suffix(void) \
3585 { \
3586 type_register(&spapr_machine_##suffix##_info); \
3587 } \
3588 type_init(spapr_machine_register_##suffix)
3589
3590
3591
3592
3593static void spapr_machine_2_10_instance_options(MachineState *machine)
3594{
3595}
3596
3597static void spapr_machine_2_10_class_options(MachineClass *mc)
3598{
3599
3600}
3601
3602DEFINE_SPAPR_MACHINE(2_10, "2.10", true);
3603
3604
3605
3606
3607#define SPAPR_COMPAT_2_9 \
3608 HW_COMPAT_2_9 \
3609 { \
3610 .driver = TYPE_POWERPC_CPU, \
3611 .property = "pre-2.10-migration", \
3612 .value = "on", \
3613 }, \
3614
3615static void spapr_machine_2_9_instance_options(MachineState *machine)
3616{
3617 spapr_machine_2_10_instance_options(machine);
3618}
3619
3620static void spapr_machine_2_9_class_options(MachineClass *mc)
3621{
3622 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3623
3624 spapr_machine_2_10_class_options(mc);
3625 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9);
3626 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram;
3627 smc->pre_2_10_has_unused_icps = true;
3628 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED;
3629}
3630
3631DEFINE_SPAPR_MACHINE(2_9, "2.9", false);
3632
3633
3634
3635
3636#define SPAPR_COMPAT_2_8 \
3637 HW_COMPAT_2_8 \
3638 { \
3639 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3640 .property = "pcie-extended-configuration-space", \
3641 .value = "off", \
3642 },
3643
3644static void spapr_machine_2_8_instance_options(MachineState *machine)
3645{
3646 spapr_machine_2_9_instance_options(machine);
3647}
3648
3649static void spapr_machine_2_8_class_options(MachineClass *mc)
3650{
3651 spapr_machine_2_9_class_options(mc);
3652 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8);
3653 mc->numa_mem_align_shift = 23;
3654}
3655
3656DEFINE_SPAPR_MACHINE(2_8, "2.8", false);
3657
3658
3659
3660
3661#define SPAPR_COMPAT_2_7 \
3662 HW_COMPAT_2_7 \
3663 { \
3664 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3665 .property = "mem_win_size", \
3666 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\
3667 }, \
3668 { \
3669 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3670 .property = "mem64_win_size", \
3671 .value = "0", \
3672 }, \
3673 { \
3674 .driver = TYPE_POWERPC_CPU, \
3675 .property = "pre-2.8-migration", \
3676 .value = "on", \
3677 }, \
3678 { \
3679 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3680 .property = "pre-2.8-migration", \
3681 .value = "on", \
3682 },
3683
3684static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index,
3685 uint64_t *buid, hwaddr *pio,
3686 hwaddr *mmio32, hwaddr *mmio64,
3687 unsigned n_dma, uint32_t *liobns, Error **errp)
3688{
3689
3690 const uint64_t base_buid = 0x800000020000000ULL;
3691 const hwaddr phb_spacing = 0x1000000000ULL;
3692 const hwaddr mmio_offset = 0xa0000000;
3693 const hwaddr pio_offset = 0x80000000;
3694 const uint32_t max_index = 255;
3695 const hwaddr phb0_alignment = 0x10000000000ULL;
3696
3697 uint64_t ram_top = MACHINE(spapr)->ram_size;
3698 hwaddr phb0_base, phb_base;
3699 int i;
3700
3701
3702 if (MACHINE(spapr)->maxram_size > ram_top) {
3703
3704
3705
3706 ram_top = spapr->hotplug_memory.base +
3707 memory_region_size(&spapr->hotplug_memory.mr);
3708 }
3709
3710 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment);
3711
3712 if (index > max_index) {
3713 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)",
3714 max_index);
3715 return;
3716 }
3717
3718 *buid = base_buid + index;
3719 for (i = 0; i < n_dma; ++i) {
3720 liobns[i] = SPAPR_PCI_LIOBN(index, i);
3721 }
3722
3723 phb_base = phb0_base + index * phb_spacing;
3724 *pio = phb_base + pio_offset;
3725 *mmio32 = phb_base + mmio_offset;
3726
3727
3728
3729
3730
3731}
3732
3733static void spapr_machine_2_7_instance_options(MachineState *machine)
3734{
3735 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
3736
3737 spapr_machine_2_8_instance_options(machine);
3738 spapr->use_hotplug_event_source = false;
3739}
3740
3741static void spapr_machine_2_7_class_options(MachineClass *mc)
3742{
3743 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3744
3745 spapr_machine_2_8_class_options(mc);
3746 smc->tcg_default_cpu = "POWER7";
3747 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7);
3748 smc->phb_placement = phb_placement_2_7;
3749}
3750
3751DEFINE_SPAPR_MACHINE(2_7, "2.7", false);
3752
3753
3754
3755
3756#define SPAPR_COMPAT_2_6 \
3757 HW_COMPAT_2_6 \
3758 { \
3759 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
3760 .property = "ddw",\
3761 .value = stringify(off),\
3762 },
3763
3764static void spapr_machine_2_6_instance_options(MachineState *machine)
3765{
3766 spapr_machine_2_7_instance_options(machine);
3767}
3768
3769static void spapr_machine_2_6_class_options(MachineClass *mc)
3770{
3771 spapr_machine_2_7_class_options(mc);
3772 mc->has_hotpluggable_cpus = false;
3773 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6);
3774}
3775
3776DEFINE_SPAPR_MACHINE(2_6, "2.6", false);
3777
3778
3779
3780
3781#define SPAPR_COMPAT_2_5 \
3782 HW_COMPAT_2_5 \
3783 { \
3784 .driver = "spapr-vlan", \
3785 .property = "use-rx-buffer-pools", \
3786 .value = "off", \
3787 },
3788
3789static void spapr_machine_2_5_instance_options(MachineState *machine)
3790{
3791 spapr_machine_2_6_instance_options(machine);
3792}
3793
3794static void spapr_machine_2_5_class_options(MachineClass *mc)
3795{
3796 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3797
3798 spapr_machine_2_6_class_options(mc);
3799 smc->use_ohci_by_default = true;
3800 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5);
3801}
3802
3803DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
3804
3805
3806
3807
3808#define SPAPR_COMPAT_2_4 \
3809 HW_COMPAT_2_4
3810
3811static void spapr_machine_2_4_instance_options(MachineState *machine)
3812{
3813 spapr_machine_2_5_instance_options(machine);
3814}
3815
3816static void spapr_machine_2_4_class_options(MachineClass *mc)
3817{
3818 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3819
3820 spapr_machine_2_5_class_options(mc);
3821 smc->dr_lmb_enabled = false;
3822 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4);
3823}
3824
3825DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
3826
3827
3828
3829
3830#define SPAPR_COMPAT_2_3 \
3831 HW_COMPAT_2_3 \
3832 {\
3833 .driver = "spapr-pci-host-bridge",\
3834 .property = "dynamic-reconfiguration",\
3835 .value = "off",\
3836 },
3837
3838static void spapr_machine_2_3_instance_options(MachineState *machine)
3839{
3840 spapr_machine_2_4_instance_options(machine);
3841}
3842
3843static void spapr_machine_2_3_class_options(MachineClass *mc)
3844{
3845 spapr_machine_2_4_class_options(mc);
3846 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3);
3847}
3848DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
3849
3850
3851
3852
3853
3854#define SPAPR_COMPAT_2_2 \
3855 HW_COMPAT_2_2 \
3856 {\
3857 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
3858 .property = "mem_win_size",\
3859 .value = "0x20000000",\
3860 },
3861
3862static void spapr_machine_2_2_instance_options(MachineState *machine)
3863{
3864 spapr_machine_2_3_instance_options(machine);
3865 machine->suppress_vmdesc = true;
3866}
3867
3868static void spapr_machine_2_2_class_options(MachineClass *mc)
3869{
3870 spapr_machine_2_3_class_options(mc);
3871 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2);
3872}
3873DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
3874
3875
3876
3877
3878#define SPAPR_COMPAT_2_1 \
3879 HW_COMPAT_2_1
3880
3881static void spapr_machine_2_1_instance_options(MachineState *machine)
3882{
3883 spapr_machine_2_2_instance_options(machine);
3884}
3885
3886static void spapr_machine_2_1_class_options(MachineClass *mc)
3887{
3888 spapr_machine_2_2_class_options(mc);
3889 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1);
3890}
3891DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
3892
3893static void spapr_machine_register_types(void)
3894{
3895 type_register_static(&spapr_machine_info);
3896}
3897
3898type_init(spapr_machine_register_types)
3899