qemu/hw/sh4/r2d.c
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   1/*
   2 * Renesas SH7751R R2D-PLUS emulation
   3 *
   4 * Copyright (c) 2007 Magnus Damm
   5 * Copyright (c) 2008 Paul Mundt
   6 *
   7 * Permission is hereby granted, free of charge, to any person obtaining a copy
   8 * of this software and associated documentation files (the "Software"), to deal
   9 * in the Software without restriction, including without limitation the rights
  10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11 * copies of the Software, and to permit persons to whom the Software is
  12 * furnished to do so, subject to the following conditions:
  13 *
  14 * The above copyright notice and this permission notice shall be included in
  15 * all copies or substantial portions of the Software.
  16 *
  17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23 * THE SOFTWARE.
  24 */
  25
  26#include "qemu/osdep.h"
  27#include "qapi/error.h"
  28#include "qemu-common.h"
  29#include "cpu.h"
  30#include "hw/sysbus.h"
  31#include "hw/hw.h"
  32#include "hw/sh4/sh.h"
  33#include "hw/devices.h"
  34#include "sysemu/sysemu.h"
  35#include "hw/boards.h"
  36#include "hw/pci/pci.h"
  37#include "net/net.h"
  38#include "sh7750_regs.h"
  39#include "hw/ide.h"
  40#include "hw/loader.h"
  41#include "hw/usb.h"
  42#include "hw/block/flash.h"
  43#include "sysemu/block-backend.h"
  44#include "exec/address-spaces.h"
  45
  46#define FLASH_BASE 0x00000000
  47#define FLASH_SIZE 0x02000000
  48
  49#define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */
  50#define SDRAM_SIZE 0x04000000
  51
  52#define SM501_VRAM_SIZE 0x800000
  53
  54#define BOOT_PARAMS_OFFSET 0x0010000
  55/* CONFIG_BOOT_LINK_OFFSET of Linux kernel */
  56#define LINUX_LOAD_OFFSET  0x0800000
  57#define INITRD_LOAD_OFFSET 0x1800000
  58
  59#define PA_IRLMSK       0x00
  60#define PA_POWOFF       0x30
  61#define PA_VERREG       0x32
  62#define PA_OUTPORT      0x36
  63
  64typedef struct {
  65    uint16_t bcr;
  66    uint16_t irlmsk;
  67    uint16_t irlmon;
  68    uint16_t cfctl;
  69    uint16_t cfpow;
  70    uint16_t dispctl;
  71    uint16_t sdmpow;
  72    uint16_t rtcce;
  73    uint16_t pcicd;
  74    uint16_t voyagerrts;
  75    uint16_t cfrst;
  76    uint16_t admrts;
  77    uint16_t extrst;
  78    uint16_t cfcdintclr;
  79    uint16_t keyctlclr;
  80    uint16_t pad0;
  81    uint16_t pad1;
  82    uint16_t verreg;
  83    uint16_t inport;
  84    uint16_t outport;
  85    uint16_t bverreg;
  86
  87/* output pin */
  88    qemu_irq irl;
  89    MemoryRegion iomem;
  90} r2d_fpga_t;
  91
  92enum r2d_fpga_irq {
  93    PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T,
  94    SDCARD, PCI_INTA, PCI_INTB, EXT, TP,
  95    NR_IRQS
  96};
  97
  98static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = {
  99    [CF_IDE]    = {  1, 1<<9 },
 100    [CF_CD]     = {  2, 1<<8 },
 101    [PCI_INTA]  = {  9, 1<<14 },
 102    [PCI_INTB]  = { 10, 1<<13 },
 103    [PCI_INTC]  = {  3, 1<<12 },
 104    [PCI_INTD]  = {  0, 1<<11 },
 105    [SM501]     = {  4, 1<<10 },
 106    [KEY]       = {  5, 1<<6 },
 107    [RTC_A]     = {  6, 1<<5 },
 108    [RTC_T]     = {  7, 1<<4 },
 109    [SDCARD]    = {  8, 1<<7 },
 110    [EXT]       = { 11, 1<<0 },
 111    [TP]        = { 12, 1<<15 },
 112};
 113
 114static void update_irl(r2d_fpga_t *fpga)
 115{
 116    int i, irl = 15;
 117    for (i = 0; i < NR_IRQS; i++)
 118        if (fpga->irlmon & fpga->irlmsk & irqtab[i].msk)
 119            if (irqtab[i].irl < irl)
 120                irl = irqtab[i].irl;
 121    qemu_set_irq(fpga->irl, irl ^ 15);
 122}
 123
 124static void r2d_fpga_irq_set(void *opaque, int n, int level)
 125{
 126    r2d_fpga_t *fpga = opaque;
 127    if (level)
 128        fpga->irlmon |= irqtab[n].msk;
 129    else
 130        fpga->irlmon &= ~irqtab[n].msk;
 131    update_irl(fpga);
 132}
 133
 134static uint64_t r2d_fpga_read(void *opaque, hwaddr addr, unsigned int size)
 135{
 136    r2d_fpga_t *s = opaque;
 137
 138    switch (addr) {
 139    case PA_IRLMSK:
 140        return s->irlmsk;
 141    case PA_OUTPORT:
 142        return s->outport;
 143    case PA_POWOFF:
 144        return 0x00;
 145    case PA_VERREG:
 146        return 0x10;
 147    }
 148
 149    return 0;
 150}
 151
 152static void
 153r2d_fpga_write(void *opaque, hwaddr addr, uint64_t value, unsigned int size)
 154{
 155    r2d_fpga_t *s = opaque;
 156
 157    switch (addr) {
 158    case PA_IRLMSK:
 159        s->irlmsk = value;
 160        update_irl(s);
 161        break;
 162    case PA_OUTPORT:
 163        s->outport = value;
 164        break;
 165    case PA_POWOFF:
 166        if (value & 1) {
 167            qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
 168        }
 169        break;
 170    case PA_VERREG:
 171        /* Discard writes */
 172        break;
 173    }
 174}
 175
 176static const MemoryRegionOps r2d_fpga_ops = {
 177    .read = r2d_fpga_read,
 178    .write = r2d_fpga_write,
 179    .impl.min_access_size = 2,
 180    .impl.max_access_size = 2,
 181    .endianness = DEVICE_NATIVE_ENDIAN,
 182};
 183
 184static qemu_irq *r2d_fpga_init(MemoryRegion *sysmem,
 185                               hwaddr base, qemu_irq irl)
 186{
 187    r2d_fpga_t *s;
 188
 189    s = g_malloc0(sizeof(r2d_fpga_t));
 190
 191    s->irl = irl;
 192
 193    memory_region_init_io(&s->iomem, NULL, &r2d_fpga_ops, s, "r2d-fpga", 0x40);
 194    memory_region_add_subregion(sysmem, base, &s->iomem);
 195    return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
 196}
 197
 198typedef struct ResetData {
 199    SuperHCPU *cpu;
 200    uint32_t vector;
 201} ResetData;
 202
 203static void main_cpu_reset(void *opaque)
 204{
 205    ResetData *s = (ResetData *)opaque;
 206    CPUSH4State *env = &s->cpu->env;
 207
 208    cpu_reset(CPU(s->cpu));
 209    env->pc = s->vector;
 210}
 211
 212static struct QEMU_PACKED
 213{
 214    int mount_root_rdonly;
 215    int ramdisk_flags;
 216    int orig_root_dev;
 217    int loader_type;
 218    int initrd_start;
 219    int initrd_size;
 220
 221    char pad[232];
 222
 223    char kernel_cmdline[256];
 224} boot_params;
 225
 226static void r2d_init(MachineState *machine)
 227{
 228    const char *cpu_model = machine->cpu_model;
 229    const char *kernel_filename = machine->kernel_filename;
 230    const char *kernel_cmdline = machine->kernel_cmdline;
 231    const char *initrd_filename = machine->initrd_filename;
 232    SuperHCPU *cpu;
 233    CPUSH4State *env;
 234    ResetData *reset_info;
 235    struct SH7750State *s;
 236    MemoryRegion *sdram = g_new(MemoryRegion, 1);
 237    qemu_irq *irq;
 238    DriveInfo *dinfo;
 239    int i;
 240    DeviceState *dev;
 241    SysBusDevice *busdev;
 242    MemoryRegion *address_space_mem = get_system_memory();
 243    PCIBus *pci_bus;
 244
 245    if (cpu_model == NULL) {
 246        cpu_model = "SH7751R";
 247    }
 248
 249    cpu = cpu_sh4_init(cpu_model);
 250    if (cpu == NULL) {
 251        fprintf(stderr, "Unable to find CPU definition\n");
 252        exit(1);
 253    }
 254    env = &cpu->env;
 255
 256    reset_info = g_malloc0(sizeof(ResetData));
 257    reset_info->cpu = cpu;
 258    reset_info->vector = env->pc;
 259    qemu_register_reset(main_cpu_reset, reset_info);
 260
 261    /* Allocate memory space */
 262    memory_region_init_ram(sdram, NULL, "r2d.sdram", SDRAM_SIZE, &error_fatal);
 263    memory_region_add_subregion(address_space_mem, SDRAM_BASE, sdram);
 264    /* Register peripherals */
 265    s = sh7750_init(cpu, address_space_mem);
 266    irq = r2d_fpga_init(address_space_mem, 0x04000000, sh7750_irl(s));
 267
 268    dev = qdev_create(NULL, "sh_pci");
 269    busdev = SYS_BUS_DEVICE(dev);
 270    qdev_init_nofail(dev);
 271    pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci"));
 272    sysbus_mmio_map(busdev, 0, P4ADDR(0x1e200000));
 273    sysbus_mmio_map(busdev, 1, A7ADDR(0x1e200000));
 274    sysbus_connect_irq(busdev, 0, irq[PCI_INTA]);
 275    sysbus_connect_irq(busdev, 1, irq[PCI_INTB]);
 276    sysbus_connect_irq(busdev, 2, irq[PCI_INTC]);
 277    sysbus_connect_irq(busdev, 3, irq[PCI_INTD]);
 278
 279    dev = qdev_create(NULL, "sysbus-sm501");
 280    busdev = SYS_BUS_DEVICE(dev);
 281    qdev_prop_set_uint32(dev, "vram-size", SM501_VRAM_SIZE);
 282    qdev_prop_set_uint32(dev, "base", 0x10000000);
 283    qdev_prop_set_ptr(dev, "chr-state", serial_hds[2]);
 284    qdev_init_nofail(dev);
 285    sysbus_mmio_map(busdev, 0, 0x10000000);
 286    sysbus_mmio_map(busdev, 1, 0x13e00000);
 287    sysbus_connect_irq(busdev, 0, irq[SM501]);
 288
 289    /* onboard CF (True IDE mode, Master only). */
 290    dinfo = drive_get(IF_IDE, 0, 0);
 291    dev = qdev_create(NULL, "mmio-ide");
 292    busdev = SYS_BUS_DEVICE(dev);
 293    sysbus_connect_irq(busdev, 0, irq[CF_IDE]);
 294    qdev_prop_set_uint32(dev, "shift", 1);
 295    qdev_init_nofail(dev);
 296    sysbus_mmio_map(busdev, 0, 0x14001000);
 297    sysbus_mmio_map(busdev, 1, 0x1400080c);
 298    mmio_ide_init_drives(dev, dinfo, NULL);
 299
 300    /* onboard flash memory */
 301    dinfo = drive_get(IF_PFLASH, 0, 0);
 302    pflash_cfi02_register(0x0, NULL, "r2d.flash", FLASH_SIZE,
 303                          dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
 304                          (16 * 1024), FLASH_SIZE >> 16,
 305                          1, 4, 0x0000, 0x0000, 0x0000, 0x0000,
 306                          0x555, 0x2aa, 0);
 307
 308    /* NIC: rtl8139 on-board, and 2 slots. */
 309    for (i = 0; i < nb_nics; i++)
 310        pci_nic_init_nofail(&nd_table[i], pci_bus,
 311                            "rtl8139", i==0 ? "2" : NULL);
 312
 313    /* USB keyboard */
 314    usb_create_simple(usb_bus_find(-1), "usb-kbd");
 315
 316    /* Todo: register on board registers */
 317    memset(&boot_params, 0, sizeof(boot_params));
 318
 319    if (kernel_filename) {
 320        int kernel_size;
 321
 322        kernel_size = load_image_targphys(kernel_filename,
 323                                          SDRAM_BASE + LINUX_LOAD_OFFSET,
 324                                          INITRD_LOAD_OFFSET - LINUX_LOAD_OFFSET);
 325        if (kernel_size < 0) {
 326          fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
 327          exit(1);
 328        }
 329
 330        /* initialization which should be done by firmware */
 331        address_space_stl(&address_space_memory, SH7750_BCR1, 1 << 3,
 332                          MEMTXATTRS_UNSPECIFIED, NULL); /* cs3 SDRAM */
 333        address_space_stw(&address_space_memory, SH7750_BCR2, 3 << (3 * 2),
 334                          MEMTXATTRS_UNSPECIFIED, NULL); /* cs3 32bit */
 335        reset_info->vector = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000; /* Start from P2 area */
 336    }
 337
 338    if (initrd_filename) {
 339        int initrd_size;
 340
 341        initrd_size = load_image_targphys(initrd_filename,
 342                                          SDRAM_BASE + INITRD_LOAD_OFFSET,
 343                                          SDRAM_SIZE - INITRD_LOAD_OFFSET);
 344
 345        if (initrd_size < 0) {
 346          fprintf(stderr, "qemu: could not load initrd '%s'\n", initrd_filename);
 347          exit(1);
 348        }
 349
 350        /* initialization which should be done by firmware */
 351        boot_params.loader_type = tswap32(1);
 352        boot_params.initrd_start = tswap32(INITRD_LOAD_OFFSET);
 353        boot_params.initrd_size = tswap32(initrd_size);
 354    }
 355
 356    if (kernel_cmdline) {
 357        /* I see no evidence that this .kernel_cmdline buffer requires
 358           NUL-termination, so using strncpy should be ok. */
 359        strncpy(boot_params.kernel_cmdline, kernel_cmdline,
 360                sizeof(boot_params.kernel_cmdline));
 361    }
 362
 363    rom_add_blob_fixed("boot_params", &boot_params, sizeof(boot_params),
 364                       SDRAM_BASE + BOOT_PARAMS_OFFSET);
 365}
 366
 367static void r2d_machine_init(MachineClass *mc)
 368{
 369    mc->desc = "r2d-plus board";
 370    mc->init = r2d_init;
 371    mc->block_default_type = IF_IDE;
 372}
 373
 374DEFINE_MACHINE("r2d", r2d_machine_init)
 375