LXR qemu/include/hw/arm/armv7m

   1/*
   2 * ARMv7M NVIC object
   3 *
   4 * Copyright (c) 2017 Linaro Ltd
   5 * Written by Peter Maydell <peter.maydell@linaro.org>
   6 *
   7 * This code is licensed under the GPL version 2 or later.
   8 */
   9
  10#ifndef HW_ARM_ARMV7M_NVIC_H
  11#define HW_ARM_ARMV7M_NVIC_H
  12
  13#include "target/arm/cpu.h"
  14#include "hw/sysbus.h"
  15#include "hw/timer/armv7m_systick.h"
  16
  17#define TYPE_NVIC "armv7m_nvic"
  18
  19#define NVIC(obj) \
  20    OBJECT_CHECK(NVICState, (obj), TYPE_NVIC)
  21
  22/* Highest permitted number of exceptions (architectural limit) */
  23#define NVIC_MAX_VECTORS 512
  24
  25typedef struct VecInfo {
  26    /* Exception priorities can range from -3 to 255; only the unmodifiable
  27     * priority values for RESET, NMI and HardFault can be negative.
  28     */
  29    int16_t prio;
  30    uint8_t enabled;
  31    uint8_t pending;
  32    uint8_t active;
  33    uint8_t level; /* exceptions <=15 never set level */
  34} VecInfo;
  35
  36typedef struct NVICState {
  37    /*< private >*/
  38    SysBusDevice parent_obj;
  39    /*< public >*/
  40
  41    ARMCPU *cpu;
  42
  43    VecInfo vectors[NVIC_MAX_VECTORS];
  44    uint32_t prigroup;
  45
  46    /* vectpending and exception_prio are both cached state that can
  47     * be recalculated from the vectors[] array and the prigroup field.
  48     */
  49    unsigned int vectpending; /* highest prio pending enabled exception */
  50    int exception_prio; /* group prio of the highest prio active exception */
  51
  52    MemoryRegion sysregmem;
  53    MemoryRegion container;
  54
  55    uint32_t num_irq;
  56    qemu_irq excpout;
  57    qemu_irq sysresetreq;
  58
  59    SysTickState systick;
  60} NVICState;
  61
  62#endif
  63