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25#include "tcg-be-null.h"
26
27#ifdef CONFIG_DEBUG_TCG
28static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
29 "%g0",
30 "%g1",
31 "%g2",
32 "%g3",
33 "%g4",
34 "%g5",
35 "%g6",
36 "%g7",
37 "%o0",
38 "%o1",
39 "%o2",
40 "%o3",
41 "%o4",
42 "%o5",
43 "%o6",
44 "%o7",
45 "%l0",
46 "%l1",
47 "%l2",
48 "%l3",
49 "%l4",
50 "%l5",
51 "%l6",
52 "%l7",
53 "%i0",
54 "%i1",
55 "%i2",
56 "%i3",
57 "%i4",
58 "%i5",
59 "%i6",
60 "%i7",
61};
62#endif
63
64#ifdef __arch64__
65# define SPARC64 1
66#else
67# define SPARC64 0
68#endif
69
70
71
72
73
74
75
76#if SPARC64
77# define ALL_64 0xffffffffu
78#else
79# define ALL_64 0xffffu
80#endif
81
82
83#define TCG_REG_T1 TCG_REG_G1
84#define TCG_REG_T2 TCG_REG_O7
85
86#ifndef CONFIG_SOFTMMU
87# define TCG_GUEST_BASE_REG TCG_REG_I5
88#endif
89
90static const int tcg_target_reg_alloc_order[] = {
91 TCG_REG_L0,
92 TCG_REG_L1,
93 TCG_REG_L2,
94 TCG_REG_L3,
95 TCG_REG_L4,
96 TCG_REG_L5,
97 TCG_REG_L6,
98 TCG_REG_L7,
99
100 TCG_REG_I0,
101 TCG_REG_I1,
102 TCG_REG_I2,
103 TCG_REG_I3,
104 TCG_REG_I4,
105 TCG_REG_I5,
106
107 TCG_REG_G2,
108 TCG_REG_G3,
109 TCG_REG_G4,
110 TCG_REG_G5,
111
112 TCG_REG_O0,
113 TCG_REG_O1,
114 TCG_REG_O2,
115 TCG_REG_O3,
116 TCG_REG_O4,
117 TCG_REG_O5,
118};
119
120static const int tcg_target_call_iarg_regs[6] = {
121 TCG_REG_O0,
122 TCG_REG_O1,
123 TCG_REG_O2,
124 TCG_REG_O3,
125 TCG_REG_O4,
126 TCG_REG_O5,
127};
128
129static const int tcg_target_call_oarg_regs[] = {
130 TCG_REG_O0,
131 TCG_REG_O1,
132 TCG_REG_O2,
133 TCG_REG_O3,
134};
135
136#define INSN_OP(x) ((x) << 30)
137#define INSN_OP2(x) ((x) << 22)
138#define INSN_OP3(x) ((x) << 19)
139#define INSN_OPF(x) ((x) << 5)
140#define INSN_RD(x) ((x) << 25)
141#define INSN_RS1(x) ((x) << 14)
142#define INSN_RS2(x) (x)
143#define INSN_ASI(x) ((x) << 5)
144
145#define INSN_IMM10(x) ((1 << 13) | ((x) & 0x3ff))
146#define INSN_IMM11(x) ((1 << 13) | ((x) & 0x7ff))
147#define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff))
148#define INSN_OFF16(x) ((((x) >> 2) & 0x3fff) | ((((x) >> 16) & 3) << 20))
149#define INSN_OFF19(x) (((x) >> 2) & 0x07ffff)
150#define INSN_COND(x) ((x) << 25)
151
152#define COND_N 0x0
153#define COND_E 0x1
154#define COND_LE 0x2
155#define COND_L 0x3
156#define COND_LEU 0x4
157#define COND_CS 0x5
158#define COND_NEG 0x6
159#define COND_VS 0x7
160#define COND_A 0x8
161#define COND_NE 0x9
162#define COND_G 0xa
163#define COND_GE 0xb
164#define COND_GU 0xc
165#define COND_CC 0xd
166#define COND_POS 0xe
167#define COND_VC 0xf
168#define BA (INSN_OP(0) | INSN_COND(COND_A) | INSN_OP2(0x2))
169
170#define RCOND_Z 1
171#define RCOND_LEZ 2
172#define RCOND_LZ 3
173#define RCOND_NZ 5
174#define RCOND_GZ 6
175#define RCOND_GEZ 7
176
177#define MOVCC_ICC (1 << 18)
178#define MOVCC_XCC (1 << 18 | 1 << 12)
179
180#define BPCC_ICC 0
181#define BPCC_XCC (2 << 20)
182#define BPCC_PT (1 << 19)
183#define BPCC_PN 0
184#define BPCC_A (1 << 29)
185
186#define BPR_PT BPCC_PT
187
188#define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00))
189#define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10))
190#define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01))
191#define ARITH_ANDN (INSN_OP(2) | INSN_OP3(0x05))
192#define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02))
193#define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12))
194#define ARITH_ORN (INSN_OP(2) | INSN_OP3(0x06))
195#define ARITH_XOR (INSN_OP(2) | INSN_OP3(0x03))
196#define ARITH_SUB (INSN_OP(2) | INSN_OP3(0x04))
197#define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14))
198#define ARITH_ADDC (INSN_OP(2) | INSN_OP3(0x08))
199#define ARITH_SUBC (INSN_OP(2) | INSN_OP3(0x0c))
200#define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a))
201#define ARITH_SMUL (INSN_OP(2) | INSN_OP3(0x0b))
202#define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e))
203#define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f))
204#define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09))
205#define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d))
206#define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d))
207#define ARITH_MOVCC (INSN_OP(2) | INSN_OP3(0x2c))
208#define ARITH_MOVR (INSN_OP(2) | INSN_OP3(0x2f))
209
210#define ARITH_ADDXC (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x11))
211#define ARITH_UMULXHI (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x16))
212
213#define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25))
214#define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26))
215#define SHIFT_SRA (INSN_OP(2) | INSN_OP3(0x27))
216
217#define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12))
218#define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12))
219#define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12))
220
221#define RDY (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(0))
222#define WRY (INSN_OP(2) | INSN_OP3(0x30) | INSN_RD(0))
223#define JMPL (INSN_OP(2) | INSN_OP3(0x38))
224#define RETURN (INSN_OP(2) | INSN_OP3(0x39))
225#define SAVE (INSN_OP(2) | INSN_OP3(0x3c))
226#define RESTORE (INSN_OP(2) | INSN_OP3(0x3d))
227#define SETHI (INSN_OP(0) | INSN_OP2(0x4))
228#define CALL INSN_OP(1)
229#define LDUB (INSN_OP(3) | INSN_OP3(0x01))
230#define LDSB (INSN_OP(3) | INSN_OP3(0x09))
231#define LDUH (INSN_OP(3) | INSN_OP3(0x02))
232#define LDSH (INSN_OP(3) | INSN_OP3(0x0a))
233#define LDUW (INSN_OP(3) | INSN_OP3(0x00))
234#define LDSW (INSN_OP(3) | INSN_OP3(0x08))
235#define LDX (INSN_OP(3) | INSN_OP3(0x0b))
236#define STB (INSN_OP(3) | INSN_OP3(0x05))
237#define STH (INSN_OP(3) | INSN_OP3(0x06))
238#define STW (INSN_OP(3) | INSN_OP3(0x04))
239#define STX (INSN_OP(3) | INSN_OP3(0x0e))
240#define LDUBA (INSN_OP(3) | INSN_OP3(0x11))
241#define LDSBA (INSN_OP(3) | INSN_OP3(0x19))
242#define LDUHA (INSN_OP(3) | INSN_OP3(0x12))
243#define LDSHA (INSN_OP(3) | INSN_OP3(0x1a))
244#define LDUWA (INSN_OP(3) | INSN_OP3(0x10))
245#define LDSWA (INSN_OP(3) | INSN_OP3(0x18))
246#define LDXA (INSN_OP(3) | INSN_OP3(0x1b))
247#define STBA (INSN_OP(3) | INSN_OP3(0x15))
248#define STHA (INSN_OP(3) | INSN_OP3(0x16))
249#define STWA (INSN_OP(3) | INSN_OP3(0x14))
250#define STXA (INSN_OP(3) | INSN_OP3(0x1e))
251
252#define MEMBAR (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(15) | (1 << 13))
253
254#ifndef ASI_PRIMARY_LITTLE
255#define ASI_PRIMARY_LITTLE 0x88
256#endif
257
258#define LDUH_LE (LDUHA | INSN_ASI(ASI_PRIMARY_LITTLE))
259#define LDSH_LE (LDSHA | INSN_ASI(ASI_PRIMARY_LITTLE))
260#define LDUW_LE (LDUWA | INSN_ASI(ASI_PRIMARY_LITTLE))
261#define LDSW_LE (LDSWA | INSN_ASI(ASI_PRIMARY_LITTLE))
262#define LDX_LE (LDXA | INSN_ASI(ASI_PRIMARY_LITTLE))
263
264#define STH_LE (STHA | INSN_ASI(ASI_PRIMARY_LITTLE))
265#define STW_LE (STWA | INSN_ASI(ASI_PRIMARY_LITTLE))
266#define STX_LE (STXA | INSN_ASI(ASI_PRIMARY_LITTLE))
267
268#ifndef use_vis3_instructions
269bool use_vis3_instructions;
270#endif
271
272static inline int check_fit_i64(int64_t val, unsigned int bits)
273{
274 return val == sextract64(val, 0, bits);
275}
276
277static inline int check_fit_i32(int32_t val, unsigned int bits)
278{
279 return val == sextract32(val, 0, bits);
280}
281
282#define check_fit_tl check_fit_i64
283#if SPARC64
284# define check_fit_ptr check_fit_i64
285#else
286# define check_fit_ptr check_fit_i32
287#endif
288
289static void patch_reloc(tcg_insn_unit *code_ptr, int type,
290 intptr_t value, intptr_t addend)
291{
292 uint32_t insn;
293
294 tcg_debug_assert(addend == 0);
295 value = tcg_ptr_byte_diff((tcg_insn_unit *)value, code_ptr);
296
297 switch (type) {
298 case R_SPARC_WDISP16:
299 if (!check_fit_ptr(value >> 2, 16)) {
300 tcg_abort();
301 }
302 insn = *code_ptr;
303 insn &= ~INSN_OFF16(-1);
304 insn |= INSN_OFF16(value);
305 *code_ptr = insn;
306 break;
307 case R_SPARC_WDISP19:
308 if (!check_fit_ptr(value >> 2, 19)) {
309 tcg_abort();
310 }
311 insn = *code_ptr;
312 insn &= ~INSN_OFF19(-1);
313 insn |= INSN_OFF19(value);
314 *code_ptr = insn;
315 break;
316 default:
317 tcg_abort();
318 }
319}
320
321
322static const char *target_parse_constraint(TCGArgConstraint *ct,
323 const char *ct_str, TCGType type)
324{
325 switch (*ct_str++) {
326 case 'r':
327 ct->ct |= TCG_CT_REG;
328 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
329 break;
330 case 'R':
331 ct->ct |= TCG_CT_REG;
332 tcg_regset_set32(ct->u.regs, 0, ALL_64);
333 break;
334 case 'A':
335 ct->ct |= TCG_CT_REG;
336 tcg_regset_set32(ct->u.regs, 0,
337 TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff);
338 reserve_helpers:
339 tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0);
340 tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1);
341 tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2);
342 break;
343 case 's':
344 ct->ct |= TCG_CT_REG;
345 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
346 goto reserve_helpers;
347 case 'S':
348 ct->ct |= TCG_CT_REG;
349 tcg_regset_set32(ct->u.regs, 0, ALL_64);
350 goto reserve_helpers;
351 case 'I':
352 ct->ct |= TCG_CT_CONST_S11;
353 break;
354 case 'J':
355 ct->ct |= TCG_CT_CONST_S13;
356 break;
357 case 'Z':
358 ct->ct |= TCG_CT_CONST_ZERO;
359 break;
360 default:
361 return NULL;
362 }
363 return ct_str;
364}
365
366
367static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
368 const TCGArgConstraint *arg_ct)
369{
370 int ct = arg_ct->ct;
371
372 if (ct & TCG_CT_CONST) {
373 return 1;
374 }
375
376 if (type == TCG_TYPE_I32) {
377 val = (int32_t)val;
378 }
379
380 if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
381 return 1;
382 } else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11)) {
383 return 1;
384 } else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13)) {
385 return 1;
386 } else {
387 return 0;
388 }
389}
390
391static inline void tcg_out_arith(TCGContext *s, TCGReg rd, TCGReg rs1,
392 TCGReg rs2, int op)
393{
394 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | INSN_RS2(rs2));
395}
396
397static inline void tcg_out_arithi(TCGContext *s, TCGReg rd, TCGReg rs1,
398 int32_t offset, int op)
399{
400 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | INSN_IMM13(offset));
401}
402
403static void tcg_out_arithc(TCGContext *s, TCGReg rd, TCGReg rs1,
404 int32_t val2, int val2const, int op)
405{
406 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1)
407 | (val2const ? INSN_IMM13(val2) : INSN_RS2(val2)));
408}
409
410static inline void tcg_out_mov(TCGContext *s, TCGType type,
411 TCGReg ret, TCGReg arg)
412{
413 if (ret != arg) {
414 tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR);
415 }
416}
417
418static inline void tcg_out_sethi(TCGContext *s, TCGReg ret, uint32_t arg)
419{
420 tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10));
421}
422
423static inline void tcg_out_movi_imm13(TCGContext *s, TCGReg ret, int32_t arg)
424{
425 tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR);
426}
427
428static void tcg_out_movi(TCGContext *s, TCGType type,
429 TCGReg ret, tcg_target_long arg)
430{
431 tcg_target_long hi, lo = (int32_t)arg;
432
433
434 if (type == TCG_TYPE_I32) {
435 arg = lo;
436 }
437
438
439 if (check_fit_tl(arg, 13)) {
440 tcg_out_movi_imm13(s, ret, arg);
441 return;
442 }
443
444
445 if (type == TCG_TYPE_I32 || arg == (uint32_t)arg) {
446 tcg_out_sethi(s, ret, arg);
447 if (arg & 0x3ff) {
448 tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR);
449 }
450 return;
451 }
452
453
454 if (arg == lo) {
455 tcg_out_sethi(s, ret, ~arg);
456 tcg_out_arithi(s, ret, ret, (arg & 0x3ff) | -0x400, ARITH_XOR);
457 return;
458 }
459
460
461 if (check_fit_i32(lo, 13)) {
462 hi = (arg - lo) >> 32;
463 tcg_out_movi(s, TCG_TYPE_I32, ret, hi);
464 tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX);
465 tcg_out_arithi(s, ret, ret, lo, ARITH_ADD);
466 } else {
467 hi = arg >> 32;
468 tcg_out_movi(s, TCG_TYPE_I32, ret, hi);
469 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_T2, lo);
470 tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX);
471 tcg_out_arith(s, ret, ret, TCG_REG_T2, ARITH_OR);
472 }
473}
474
475static inline void tcg_out_ldst_rr(TCGContext *s, TCGReg data, TCGReg a1,
476 TCGReg a2, int op)
477{
478 tcg_out32(s, op | INSN_RD(data) | INSN_RS1(a1) | INSN_RS2(a2));
479}
480
481static void tcg_out_ldst(TCGContext *s, TCGReg ret, TCGReg addr,
482 intptr_t offset, int op)
483{
484 if (check_fit_ptr(offset, 13)) {
485 tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) |
486 INSN_IMM13(offset));
487 } else {
488 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, offset);
489 tcg_out_ldst_rr(s, ret, addr, TCG_REG_T1, op);
490 }
491}
492
493static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
494 TCGReg arg1, intptr_t arg2)
495{
496 tcg_out_ldst(s, ret, arg1, arg2, (type == TCG_TYPE_I32 ? LDUW : LDX));
497}
498
499static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
500 TCGReg arg1, intptr_t arg2)
501{
502 tcg_out_ldst(s, arg, arg1, arg2, (type == TCG_TYPE_I32 ? STW : STX));
503}
504
505static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
506 TCGReg base, intptr_t ofs)
507{
508 if (val == 0) {
509 tcg_out_st(s, type, TCG_REG_G0, base, ofs);
510 return true;
511 }
512 return false;
513}
514
515static void tcg_out_ld_ptr(TCGContext *s, TCGReg ret, uintptr_t arg)
516{
517 tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ff);
518 tcg_out_ld(s, TCG_TYPE_PTR, ret, ret, arg & 0x3ff);
519}
520
521static inline void tcg_out_sety(TCGContext *s, TCGReg rs)
522{
523 tcg_out32(s, WRY | INSN_RS1(TCG_REG_G0) | INSN_RS2(rs));
524}
525
526static inline void tcg_out_rdy(TCGContext *s, TCGReg rd)
527{
528 tcg_out32(s, RDY | INSN_RD(rd));
529}
530
531static void tcg_out_div32(TCGContext *s, TCGReg rd, TCGReg rs1,
532 int32_t val2, int val2const, int uns)
533{
534
535 if (uns) {
536 tcg_out_sety(s, TCG_REG_G0);
537 } else {
538 tcg_out_arithi(s, TCG_REG_T1, rs1, 31, SHIFT_SRA);
539 tcg_out_sety(s, TCG_REG_T1);
540 }
541
542 tcg_out_arithc(s, rd, rs1, val2, val2const,
543 uns ? ARITH_UDIV : ARITH_SDIV);
544}
545
546static inline void tcg_out_nop(TCGContext *s)
547{
548 tcg_out_sethi(s, TCG_REG_G0, 0);
549}
550
551static const uint8_t tcg_cond_to_bcond[] = {
552 [TCG_COND_EQ] = COND_E,
553 [TCG_COND_NE] = COND_NE,
554 [TCG_COND_LT] = COND_L,
555 [TCG_COND_GE] = COND_GE,
556 [TCG_COND_LE] = COND_LE,
557 [TCG_COND_GT] = COND_G,
558 [TCG_COND_LTU] = COND_CS,
559 [TCG_COND_GEU] = COND_CC,
560 [TCG_COND_LEU] = COND_LEU,
561 [TCG_COND_GTU] = COND_GU,
562};
563
564static const uint8_t tcg_cond_to_rcond[] = {
565 [TCG_COND_EQ] = RCOND_Z,
566 [TCG_COND_NE] = RCOND_NZ,
567 [TCG_COND_LT] = RCOND_LZ,
568 [TCG_COND_GT] = RCOND_GZ,
569 [TCG_COND_LE] = RCOND_LEZ,
570 [TCG_COND_GE] = RCOND_GEZ
571};
572
573static void tcg_out_bpcc0(TCGContext *s, int scond, int flags, int off19)
574{
575 tcg_out32(s, INSN_OP(0) | INSN_OP2(1) | INSN_COND(scond) | flags | off19);
576}
577
578static void tcg_out_bpcc(TCGContext *s, int scond, int flags, TCGLabel *l)
579{
580 int off19;
581
582 if (l->has_value) {
583 off19 = INSN_OFF19(tcg_pcrel_diff(s, l->u.value_ptr));
584 } else {
585
586 off19 = *s->code_ptr & INSN_OFF19(-1);
587 tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP19, l, 0);
588 }
589 tcg_out_bpcc0(s, scond, flags, off19);
590}
591
592static void tcg_out_cmp(TCGContext *s, TCGReg c1, int32_t c2, int c2const)
593{
594 tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const, ARITH_SUBCC);
595}
596
597static void tcg_out_brcond_i32(TCGContext *s, TCGCond cond, TCGReg arg1,
598 int32_t arg2, int const_arg2, TCGLabel *l)
599{
600 tcg_out_cmp(s, arg1, arg2, const_arg2);
601 tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_ICC | BPCC_PT, l);
602 tcg_out_nop(s);
603}
604
605static void tcg_out_movcc(TCGContext *s, TCGCond cond, int cc, TCGReg ret,
606 int32_t v1, int v1const)
607{
608 tcg_out32(s, ARITH_MOVCC | cc | INSN_RD(ret)
609 | INSN_RS1(tcg_cond_to_bcond[cond])
610 | (v1const ? INSN_IMM11(v1) : INSN_RS2(v1)));
611}
612
613static void tcg_out_movcond_i32(TCGContext *s, TCGCond cond, TCGReg ret,
614 TCGReg c1, int32_t c2, int c2const,
615 int32_t v1, int v1const)
616{
617 tcg_out_cmp(s, c1, c2, c2const);
618 tcg_out_movcc(s, cond, MOVCC_ICC, ret, v1, v1const);
619}
620
621static void tcg_out_brcond_i64(TCGContext *s, TCGCond cond, TCGReg arg1,
622 int32_t arg2, int const_arg2, TCGLabel *l)
623{
624
625 if (arg2 == 0 && !is_unsigned_cond(cond)) {
626 int off16;
627
628 if (l->has_value) {
629 off16 = INSN_OFF16(tcg_pcrel_diff(s, l->u.value_ptr));
630 } else {
631
632 off16 = *s->code_ptr & INSN_OFF16(-1);
633 tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP16, l, 0);
634 }
635 tcg_out32(s, INSN_OP(0) | INSN_OP2(3) | BPR_PT | INSN_RS1(arg1)
636 | INSN_COND(tcg_cond_to_rcond[cond]) | off16);
637 } else {
638 tcg_out_cmp(s, arg1, arg2, const_arg2);
639 tcg_out_bpcc(s, tcg_cond_to_bcond[cond], BPCC_XCC | BPCC_PT, l);
640 }
641 tcg_out_nop(s);
642}
643
644static void tcg_out_movr(TCGContext *s, TCGCond cond, TCGReg ret, TCGReg c1,
645 int32_t v1, int v1const)
646{
647 tcg_out32(s, ARITH_MOVR | INSN_RD(ret) | INSN_RS1(c1)
648 | (tcg_cond_to_rcond[cond] << 10)
649 | (v1const ? INSN_IMM10(v1) : INSN_RS2(v1)));
650}
651
652static void tcg_out_movcond_i64(TCGContext *s, TCGCond cond, TCGReg ret,
653 TCGReg c1, int32_t c2, int c2const,
654 int32_t v1, int v1const)
655{
656
657
658
659 if (c2 == 0 && !is_unsigned_cond(cond)
660 && (!v1const || check_fit_i32(v1, 10))) {
661 tcg_out_movr(s, cond, ret, c1, v1, v1const);
662 } else {
663 tcg_out_cmp(s, c1, c2, c2const);
664 tcg_out_movcc(s, cond, MOVCC_XCC, ret, v1, v1const);
665 }
666}
667
668static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGReg ret,
669 TCGReg c1, int32_t c2, int c2const)
670{
671
672 switch (cond) {
673 case TCG_COND_LTU:
674 case TCG_COND_GEU:
675
676 break;
677
678 case TCG_COND_EQ:
679 case TCG_COND_NE:
680
681 if (c2 != 0) {
682 tcg_out_arithc(s, TCG_REG_T1, c1, c2, c2const, ARITH_XOR);
683 c2 = TCG_REG_T1;
684 } else {
685 c2 = c1;
686 }
687 c1 = TCG_REG_G0, c2const = 0;
688 cond = (cond == TCG_COND_EQ ? TCG_COND_GEU : TCG_COND_LTU);
689 break;
690
691 case TCG_COND_GTU:
692 case TCG_COND_LEU:
693
694
695
696 if (!c2const || c2 == 0) {
697 TCGReg t = c1;
698 c1 = c2;
699 c2 = t;
700 c2const = 0;
701 cond = tcg_swap_cond(cond);
702 break;
703 }
704
705
706 default:
707 tcg_out_cmp(s, c1, c2, c2const);
708 tcg_out_movi_imm13(s, ret, 0);
709 tcg_out_movcc(s, cond, MOVCC_ICC, ret, 1, 1);
710 return;
711 }
712
713 tcg_out_cmp(s, c1, c2, c2const);
714 if (cond == TCG_COND_LTU) {
715 tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_ADDC);
716 } else {
717 tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH_SUBC);
718 }
719}
720
721static void tcg_out_setcond_i64(TCGContext *s, TCGCond cond, TCGReg ret,
722 TCGReg c1, int32_t c2, int c2const)
723{
724 if (use_vis3_instructions) {
725 switch (cond) {
726 case TCG_COND_NE:
727 if (c2 != 0) {
728 break;
729 }
730 c2 = c1, c2const = 0, c1 = TCG_REG_G0;
731
732 case TCG_COND_LTU:
733 tcg_out_cmp(s, c1, c2, c2const);
734 tcg_out_arith(s, ret, TCG_REG_G0, TCG_REG_G0, ARITH_ADDXC);
735 return;
736 default:
737 break;
738 }
739 }
740
741
742
743 if (c2 == 0 && !is_unsigned_cond(cond) && c1 != ret) {
744 tcg_out_movi_imm13(s, ret, 0);
745 tcg_out_movr(s, cond, ret, c1, 1, 1);
746 } else {
747 tcg_out_cmp(s, c1, c2, c2const);
748 tcg_out_movi_imm13(s, ret, 0);
749 tcg_out_movcc(s, cond, MOVCC_XCC, ret, 1, 1);
750 }
751}
752
753static void tcg_out_addsub2_i32(TCGContext *s, TCGReg rl, TCGReg rh,
754 TCGReg al, TCGReg ah, int32_t bl, int blconst,
755 int32_t bh, int bhconst, int opl, int oph)
756{
757 TCGReg tmp = TCG_REG_T1;
758
759
760 if (rl != ah && (bhconst || rl != bh)) {
761 tmp = rl;
762 }
763
764 tcg_out_arithc(s, tmp, al, bl, blconst, opl);
765 tcg_out_arithc(s, rh, ah, bh, bhconst, oph);
766 tcg_out_mov(s, TCG_TYPE_I32, rl, tmp);
767}
768
769static void tcg_out_addsub2_i64(TCGContext *s, TCGReg rl, TCGReg rh,
770 TCGReg al, TCGReg ah, int32_t bl, int blconst,
771 int32_t bh, int bhconst, bool is_sub)
772{
773 TCGReg tmp = TCG_REG_T1;
774
775
776 if (rl != ah && (bhconst || rl != bh)) {
777 tmp = rl;
778 }
779
780 tcg_out_arithc(s, tmp, al, bl, blconst, is_sub ? ARITH_SUBCC : ARITH_ADDCC);
781
782 if (use_vis3_instructions && !is_sub) {
783
784 if (bhconst && bh != 0) {
785 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_T2, bh);
786 bh = TCG_REG_T2;
787 }
788 tcg_out_arith(s, rh, ah, bh, ARITH_ADDXC);
789 } else if (bh == TCG_REG_G0) {
790
791
792 if (rh == ah) {
793 tcg_out_arithi(s, TCG_REG_T2, ah, 1,
794 is_sub ? ARITH_SUB : ARITH_ADD);
795 tcg_out_movcc(s, TCG_COND_LTU, MOVCC_XCC, rh, TCG_REG_T2, 0);
796 } else {
797 tcg_out_arithi(s, rh, ah, 1, is_sub ? ARITH_SUB : ARITH_ADD);
798 tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, rh, ah, 0);
799 }
800 } else {
801
802 if (bhconst) {
803 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_T2, bh + (is_sub ? -1 : 1));
804 } else {
805 tcg_out_arithi(s, TCG_REG_T2, bh, 1,
806 is_sub ? ARITH_SUB : ARITH_ADD);
807 }
808
809 tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, TCG_REG_T2, bh, bhconst);
810
811 tcg_out_arith(s, rh, ah, TCG_REG_T2, is_sub ? ARITH_SUB : ARITH_ADD);
812 }
813
814 tcg_out_mov(s, TCG_TYPE_I64, rl, tmp);
815}
816
817static void tcg_out_call_nodelay(TCGContext *s, tcg_insn_unit *dest)
818{
819 ptrdiff_t disp = tcg_pcrel_diff(s, dest);
820
821 if (disp == (int32_t)disp) {
822 tcg_out32(s, CALL | (uint32_t)disp >> 2);
823 } else {
824 uintptr_t desti = (uintptr_t)dest;
825 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, desti & ~0xfff);
826 tcg_out_arithi(s, TCG_REG_O7, TCG_REG_T1, desti & 0xfff, JMPL);
827 }
828}
829
830static void tcg_out_call(TCGContext *s, tcg_insn_unit *dest)
831{
832 tcg_out_call_nodelay(s, dest);
833 tcg_out_nop(s);
834}
835
836static void tcg_out_mb(TCGContext *s, TCGArg a0)
837{
838
839 tcg_out32(s, MEMBAR | (a0 & TCG_MO_ALL));
840}
841
842#ifdef CONFIG_SOFTMMU
843static tcg_insn_unit *qemu_ld_trampoline[16];
844static tcg_insn_unit *qemu_st_trampoline[16];
845
846static void emit_extend(TCGContext *s, TCGReg r, int op)
847{
848
849
850
851 switch (op & MO_SIZE) {
852 case MO_8:
853 tcg_out_arithi(s, r, r, 0xff, ARITH_AND);
854 break;
855 case MO_16:
856 tcg_out_arithi(s, r, r, 16, SHIFT_SLL);
857 tcg_out_arithi(s, r, r, 16, SHIFT_SRL);
858 break;
859 case MO_32:
860 if (SPARC64) {
861 tcg_out_arith(s, r, r, 0, SHIFT_SRL);
862 }
863 break;
864 case MO_64:
865 break;
866 }
867}
868
869static void build_trampolines(TCGContext *s)
870{
871 static void * const qemu_ld_helpers[16] = {
872 [MO_UB] = helper_ret_ldub_mmu,
873 [MO_SB] = helper_ret_ldsb_mmu,
874 [MO_LEUW] = helper_le_lduw_mmu,
875 [MO_LESW] = helper_le_ldsw_mmu,
876 [MO_LEUL] = helper_le_ldul_mmu,
877 [MO_LEQ] = helper_le_ldq_mmu,
878 [MO_BEUW] = helper_be_lduw_mmu,
879 [MO_BESW] = helper_be_ldsw_mmu,
880 [MO_BEUL] = helper_be_ldul_mmu,
881 [MO_BEQ] = helper_be_ldq_mmu,
882 };
883 static void * const qemu_st_helpers[16] = {
884 [MO_UB] = helper_ret_stb_mmu,
885 [MO_LEUW] = helper_le_stw_mmu,
886 [MO_LEUL] = helper_le_stl_mmu,
887 [MO_LEQ] = helper_le_stq_mmu,
888 [MO_BEUW] = helper_be_stw_mmu,
889 [MO_BEUL] = helper_be_stl_mmu,
890 [MO_BEQ] = helper_be_stq_mmu,
891 };
892
893 int i;
894 TCGReg ra;
895
896 for (i = 0; i < 16; ++i) {
897 if (qemu_ld_helpers[i] == NULL) {
898 continue;
899 }
900
901
902 while ((uintptr_t)s->code_ptr & 15) {
903 tcg_out_nop(s);
904 }
905 qemu_ld_trampoline[i] = s->code_ptr;
906
907 if (SPARC64 || TARGET_LONG_BITS == 32) {
908 ra = TCG_REG_O3;
909 } else {
910
911 tcg_out_arithi(s, TCG_REG_O1, TCG_REG_O2, 32, SHIFT_SRLX);
912 ra = TCG_REG_O4;
913 }
914
915
916 tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7);
917
918 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O0, TCG_AREG0);
919
920 tcg_out_call_nodelay(s, qemu_ld_helpers[i]);
921 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra);
922 }
923
924 for (i = 0; i < 16; ++i) {
925 if (qemu_st_helpers[i] == NULL) {
926 continue;
927 }
928
929
930 while ((uintptr_t)s->code_ptr & 15) {
931 tcg_out_nop(s);
932 }
933 qemu_st_trampoline[i] = s->code_ptr;
934
935 if (SPARC64) {
936 emit_extend(s, TCG_REG_O2, i);
937 ra = TCG_REG_O4;
938 } else {
939 ra = TCG_REG_O1;
940 if (TARGET_LONG_BITS == 64) {
941
942 tcg_out_arithi(s, ra, ra + 1, 32, SHIFT_SRLX);
943 ra += 2;
944 } else {
945 ra += 1;
946 }
947 if ((i & MO_SIZE) == MO_64) {
948
949 tcg_out_arithi(s, ra, ra + 1, 32, SHIFT_SRLX);
950 ra += 2;
951 } else {
952 emit_extend(s, ra, i);
953 ra += 1;
954 }
955
956 ra += 1;
957 }
958
959
960 if (ra >= TCG_REG_O6) {
961 tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_O7, TCG_REG_CALL_STACK,
962 TCG_TARGET_CALL_STACK_OFFSET);
963 ra = TCG_REG_G1;
964 }
965 tcg_out_mov(s, TCG_TYPE_PTR, ra, TCG_REG_O7);
966
967 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O0, TCG_AREG0);
968
969 tcg_out_call_nodelay(s, qemu_st_helpers[i]);
970 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra);
971 }
972}
973#endif
974
975
976static void tcg_target_qemu_prologue(TCGContext *s)
977{
978 int tmp_buf_size, frame_size;
979
980
981
982 tmp_buf_size = CPU_TEMP_BUF_NLONGS * (int)sizeof(long);
983 tcg_set_frame(s, TCG_REG_I6, TCG_TARGET_STACK_BIAS - tmp_buf_size,
984 tmp_buf_size);
985
986
987
988 frame_size = TCG_TARGET_CALL_STACK_OFFSET - TCG_TARGET_STACK_BIAS;
989 frame_size += TCG_STATIC_CALL_ARGS_SIZE + tmp_buf_size;
990 frame_size += TCG_TARGET_STACK_ALIGN - 1;
991 frame_size &= -TCG_TARGET_STACK_ALIGN;
992 tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) |
993 INSN_IMM13(-frame_size));
994
995#ifndef CONFIG_SOFTMMU
996 if (guest_base != 0) {
997 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
998 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
999 }
1000#endif
1001
1002 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I1, 0, JMPL);
1003
1004 tcg_out_nop(s);
1005
1006
1007 s->code_gen_epilogue = s->code_ptr;
1008 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN);
1009
1010 tcg_out_movi_imm13(s, TCG_REG_O0, 0);
1011
1012#ifdef CONFIG_SOFTMMU
1013 build_trampolines(s);
1014#endif
1015}
1016
1017#if defined(CONFIG_SOFTMMU)
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, int mem_index,
1032 TCGMemOp opc, int which)
1033{
1034 const TCGReg r0 = TCG_REG_O0;
1035 const TCGReg r1 = TCG_REG_O1;
1036 const TCGReg r2 = TCG_REG_O2;
1037 unsigned s_bits = opc & MO_SIZE;
1038 unsigned a_bits = get_alignment_bits(opc);
1039 int tlb_ofs;
1040
1041
1042 tcg_out_arithi(s, r1, addr, TARGET_PAGE_BITS, SHIFT_SRL);
1043
1044
1045
1046 if (a_bits < s_bits) {
1047 a_bits = s_bits;
1048 }
1049 tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_T1,
1050 TARGET_PAGE_MASK | ((1 << a_bits) - 1));
1051
1052
1053 tcg_out_arithi(s, r1, r1, CPU_TLB_SIZE - 1, ARITH_AND);
1054
1055
1056 tcg_out_arith(s, r0, addr, TCG_REG_T1, ARITH_AND);
1057
1058
1059 tcg_out_arithi(s, r1, r1, CPU_TLB_ENTRY_BITS, SHIFT_SLL);
1060
1061
1062 tcg_out_arith(s, r1, TCG_AREG0, r1, ARITH_ADD);
1063
1064
1065 tlb_ofs = offsetof(CPUArchState, tlb_table[mem_index][0]);
1066 if (!check_fit_ptr(tlb_ofs + sizeof(CPUTLBEntry), 13)) {
1067 if (tlb_ofs & ~0x3ff) {
1068 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, tlb_ofs & ~0x3ff);
1069 tcg_out_arith(s, r1, r1, TCG_REG_T1, ARITH_ADD);
1070 }
1071 tlb_ofs &= 0x3ff;
1072 }
1073
1074
1075 tcg_out_ld(s, TCG_TYPE_TL, r2, r1, tlb_ofs + which);
1076 tcg_out_ld(s, TCG_TYPE_PTR, r1, r1, tlb_ofs+offsetof(CPUTLBEntry, addend));
1077
1078
1079 tcg_out_cmp(s, r0, r2, 0);
1080
1081
1082 if (SPARC64 && TARGET_LONG_BITS == 32) {
1083 tcg_out_arithi(s, r0, addr, 0, SHIFT_SRL);
1084 return r0;
1085 }
1086 return addr;
1087}
1088#endif
1089
1090static const int qemu_ld_opc[16] = {
1091 [MO_UB] = LDUB,
1092 [MO_SB] = LDSB,
1093
1094 [MO_BEUW] = LDUH,
1095 [MO_BESW] = LDSH,
1096 [MO_BEUL] = LDUW,
1097 [MO_BESL] = LDSW,
1098 [MO_BEQ] = LDX,
1099
1100 [MO_LEUW] = LDUH_LE,
1101 [MO_LESW] = LDSH_LE,
1102 [MO_LEUL] = LDUW_LE,
1103 [MO_LESL] = LDSW_LE,
1104 [MO_LEQ] = LDX_LE,
1105};
1106
1107static const int qemu_st_opc[16] = {
1108 [MO_UB] = STB,
1109
1110 [MO_BEUW] = STH,
1111 [MO_BEUL] = STW,
1112 [MO_BEQ] = STX,
1113
1114 [MO_LEUW] = STH_LE,
1115 [MO_LEUL] = STW_LE,
1116 [MO_LEQ] = STX_LE,
1117};
1118
1119static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr,
1120 TCGMemOpIdx oi, bool is_64)
1121{
1122 TCGMemOp memop = get_memop(oi);
1123#ifdef CONFIG_SOFTMMU
1124 unsigned memi = get_mmuidx(oi);
1125 TCGReg addrz, param;
1126 tcg_insn_unit *func;
1127 tcg_insn_unit *label_ptr;
1128
1129 addrz = tcg_out_tlb_load(s, addr, memi, memop,
1130 offsetof(CPUTLBEntry, addr_read));
1131
1132
1133
1134
1135
1136
1137 label_ptr = s->code_ptr;
1138 tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT
1139 | (TARGET_LONG_BITS == 64 ? BPCC_XCC : BPCC_ICC), 0);
1140
1141 tcg_out_ldst_rr(s, data, addrz, TCG_REG_O1,
1142 qemu_ld_opc[memop & (MO_BSWAP | MO_SSIZE)]);
1143
1144
1145
1146 param = TCG_REG_O1;
1147 if (!SPARC64 && TARGET_LONG_BITS == 64) {
1148
1149 param++;
1150 }
1151 tcg_out_mov(s, TCG_TYPE_REG, param++, addrz);
1152
1153
1154
1155 if ((memop & MO_SSIZE) == MO_SL) {
1156 func = qemu_ld_trampoline[memop & (MO_BSWAP | MO_SIZE)];
1157 } else {
1158 func = qemu_ld_trampoline[memop & (MO_BSWAP | MO_SSIZE)];
1159 }
1160 tcg_debug_assert(func != NULL);
1161 tcg_out_call_nodelay(s, func);
1162
1163 tcg_out_movi(s, TCG_TYPE_I32, param, oi);
1164
1165
1166
1167 if (SPARC64) {
1168
1169 if (is_64 && (memop & MO_SSIZE) == MO_SL) {
1170 tcg_out_arithi(s, data, TCG_REG_O0, 0, SHIFT_SRA);
1171 } else {
1172 tcg_out_mov(s, TCG_TYPE_REG, data, TCG_REG_O0);
1173 }
1174 } else {
1175 if ((memop & MO_SIZE) == MO_64) {
1176 tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, 32, SHIFT_SLLX);
1177 tcg_out_arithi(s, TCG_REG_O1, TCG_REG_O1, 0, SHIFT_SRL);
1178 tcg_out_arith(s, data, TCG_REG_O0, TCG_REG_O1, ARITH_OR);
1179 } else if (is_64) {
1180
1181
1182 tcg_out_arithi(s, data, TCG_REG_O1, 0,
1183 memop & MO_SIGN ? SHIFT_SRA : SHIFT_SRL);
1184 } else {
1185 tcg_out_mov(s, TCG_TYPE_I32, data, TCG_REG_O1);
1186 }
1187 }
1188
1189 *label_ptr |= INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr));
1190#else
1191 if (SPARC64 && TARGET_LONG_BITS == 32) {
1192 tcg_out_arithi(s, TCG_REG_T1, addr, 0, SHIFT_SRL);
1193 addr = TCG_REG_T1;
1194 }
1195 tcg_out_ldst_rr(s, data, addr,
1196 (guest_base ? TCG_GUEST_BASE_REG : TCG_REG_G0),
1197 qemu_ld_opc[memop & (MO_BSWAP | MO_SSIZE)]);
1198#endif
1199}
1200
1201static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr,
1202 TCGMemOpIdx oi)
1203{
1204 TCGMemOp memop = get_memop(oi);
1205#ifdef CONFIG_SOFTMMU
1206 unsigned memi = get_mmuidx(oi);
1207 TCGReg addrz, param;
1208 tcg_insn_unit *func;
1209 tcg_insn_unit *label_ptr;
1210
1211 addrz = tcg_out_tlb_load(s, addr, memi, memop,
1212 offsetof(CPUTLBEntry, addr_write));
1213
1214
1215
1216
1217 label_ptr = s->code_ptr;
1218 tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT
1219 | (TARGET_LONG_BITS == 64 ? BPCC_XCC : BPCC_ICC), 0);
1220
1221 tcg_out_ldst_rr(s, data, addrz, TCG_REG_O1,
1222 qemu_st_opc[memop & (MO_BSWAP | MO_SIZE)]);
1223
1224
1225
1226 param = TCG_REG_O1;
1227 if (!SPARC64 && TARGET_LONG_BITS == 64) {
1228
1229 param++;
1230 }
1231 tcg_out_mov(s, TCG_TYPE_REG, param++, addrz);
1232 if (!SPARC64 && (memop & MO_SIZE) == MO_64) {
1233
1234 param++;
1235 }
1236 tcg_out_mov(s, TCG_TYPE_REG, param++, data);
1237
1238 func = qemu_st_trampoline[memop & (MO_BSWAP | MO_SIZE)];
1239 tcg_debug_assert(func != NULL);
1240 tcg_out_call_nodelay(s, func);
1241
1242 tcg_out_movi(s, TCG_TYPE_I32, param, oi);
1243
1244 *label_ptr |= INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr));
1245#else
1246 if (SPARC64 && TARGET_LONG_BITS == 32) {
1247 tcg_out_arithi(s, TCG_REG_T1, addr, 0, SHIFT_SRL);
1248 addr = TCG_REG_T1;
1249 }
1250 tcg_out_ldst_rr(s, data, addr,
1251 (guest_base ? TCG_GUEST_BASE_REG : TCG_REG_G0),
1252 qemu_st_opc[memop & (MO_BSWAP | MO_SIZE)]);
1253#endif
1254}
1255
1256static void tcg_out_op(TCGContext *s, TCGOpcode opc,
1257 const TCGArg args[TCG_MAX_OP_ARGS],
1258 const int const_args[TCG_MAX_OP_ARGS])
1259{
1260 TCGArg a0, a1, a2;
1261 int c, c2;
1262
1263
1264 a0 = args[0];
1265 a1 = args[1];
1266 a2 = args[2];
1267 c2 = const_args[2];
1268
1269 switch (opc) {
1270 case INDEX_op_exit_tb:
1271 if (check_fit_ptr(a0, 13)) {
1272 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN);
1273 tcg_out_movi_imm13(s, TCG_REG_O0, a0);
1274 } else {
1275 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, a0 & ~0x3ff);
1276 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN);
1277 tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, a0 & 0x3ff, ARITH_OR);
1278 }
1279 break;
1280 case INDEX_op_goto_tb:
1281 if (s->tb_jmp_insn_offset) {
1282
1283 s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s);
1284
1285 tcg_out32(s, CALL | (*s->code_ptr & ~INSN_OP(-1)));
1286 } else {
1287
1288 tcg_out_ld_ptr(s, TCG_REG_T1,
1289 (uintptr_t)(s->tb_jmp_target_addr + a0));
1290 tcg_out_arithi(s, TCG_REG_G0, TCG_REG_T1, 0, JMPL);
1291 }
1292 tcg_out_nop(s);
1293 s->tb_jmp_reset_offset[a0] = tcg_current_code_size(s);
1294 break;
1295 case INDEX_op_goto_ptr:
1296 tcg_out_arithi(s, TCG_REG_G0, a0, 0, JMPL);
1297 tcg_out_nop(s);
1298 break;
1299 case INDEX_op_br:
1300 tcg_out_bpcc(s, COND_A, BPCC_PT, arg_label(a0));
1301 tcg_out_nop(s);
1302 break;
1303
1304#define OP_32_64(x) \
1305 glue(glue(case INDEX_op_, x), _i32): \
1306 glue(glue(case INDEX_op_, x), _i64)
1307
1308 OP_32_64(ld8u):
1309 tcg_out_ldst(s, a0, a1, a2, LDUB);
1310 break;
1311 OP_32_64(ld8s):
1312 tcg_out_ldst(s, a0, a1, a2, LDSB);
1313 break;
1314 OP_32_64(ld16u):
1315 tcg_out_ldst(s, a0, a1, a2, LDUH);
1316 break;
1317 OP_32_64(ld16s):
1318 tcg_out_ldst(s, a0, a1, a2, LDSH);
1319 break;
1320 case INDEX_op_ld_i32:
1321 case INDEX_op_ld32u_i64:
1322 tcg_out_ldst(s, a0, a1, a2, LDUW);
1323 break;
1324 OP_32_64(st8):
1325 tcg_out_ldst(s, a0, a1, a2, STB);
1326 break;
1327 OP_32_64(st16):
1328 tcg_out_ldst(s, a0, a1, a2, STH);
1329 break;
1330 case INDEX_op_st_i32:
1331 case INDEX_op_st32_i64:
1332 tcg_out_ldst(s, a0, a1, a2, STW);
1333 break;
1334 OP_32_64(add):
1335 c = ARITH_ADD;
1336 goto gen_arith;
1337 OP_32_64(sub):
1338 c = ARITH_SUB;
1339 goto gen_arith;
1340 OP_32_64(and):
1341 c = ARITH_AND;
1342 goto gen_arith;
1343 OP_32_64(andc):
1344 c = ARITH_ANDN;
1345 goto gen_arith;
1346 OP_32_64(or):
1347 c = ARITH_OR;
1348 goto gen_arith;
1349 OP_32_64(orc):
1350 c = ARITH_ORN;
1351 goto gen_arith;
1352 OP_32_64(xor):
1353 c = ARITH_XOR;
1354 goto gen_arith;
1355 case INDEX_op_shl_i32:
1356 c = SHIFT_SLL;
1357 do_shift32:
1358
1359 tcg_out_arithc(s, a0, a1, a2 & 31, c2, c);
1360 break;
1361 case INDEX_op_shr_i32:
1362 c = SHIFT_SRL;
1363 goto do_shift32;
1364 case INDEX_op_sar_i32:
1365 c = SHIFT_SRA;
1366 goto do_shift32;
1367 case INDEX_op_mul_i32:
1368 c = ARITH_UMUL;
1369 goto gen_arith;
1370
1371 OP_32_64(neg):
1372 c = ARITH_SUB;
1373 goto gen_arith1;
1374 OP_32_64(not):
1375 c = ARITH_ORN;
1376 goto gen_arith1;
1377
1378 case INDEX_op_div_i32:
1379 tcg_out_div32(s, a0, a1, a2, c2, 0);
1380 break;
1381 case INDEX_op_divu_i32:
1382 tcg_out_div32(s, a0, a1, a2, c2, 1);
1383 break;
1384
1385 case INDEX_op_brcond_i32:
1386 tcg_out_brcond_i32(s, a2, a0, a1, const_args[1], arg_label(args[3]));
1387 break;
1388 case INDEX_op_setcond_i32:
1389 tcg_out_setcond_i32(s, args[3], a0, a1, a2, c2);
1390 break;
1391 case INDEX_op_movcond_i32:
1392 tcg_out_movcond_i32(s, args[5], a0, a1, a2, c2, args[3], const_args[3]);
1393 break;
1394
1395 case INDEX_op_add2_i32:
1396 tcg_out_addsub2_i32(s, args[0], args[1], args[2], args[3],
1397 args[4], const_args[4], args[5], const_args[5],
1398 ARITH_ADDCC, ARITH_ADDC);
1399 break;
1400 case INDEX_op_sub2_i32:
1401 tcg_out_addsub2_i32(s, args[0], args[1], args[2], args[3],
1402 args[4], const_args[4], args[5], const_args[5],
1403 ARITH_SUBCC, ARITH_SUBC);
1404 break;
1405 case INDEX_op_mulu2_i32:
1406 c = ARITH_UMUL;
1407 goto do_mul2;
1408 case INDEX_op_muls2_i32:
1409 c = ARITH_SMUL;
1410 do_mul2:
1411
1412
1413 tcg_out_arithc(s, a0, a2, args[3], const_args[3], c);
1414 if (SPARC64 || a0 <= TCG_REG_O7) {
1415 tcg_out_arithi(s, a1, a0, 32, SHIFT_SRLX);
1416 } else {
1417 tcg_out_rdy(s, a1);
1418 }
1419 break;
1420
1421 case INDEX_op_qemu_ld_i32:
1422 tcg_out_qemu_ld(s, a0, a1, a2, false);
1423 break;
1424 case INDEX_op_qemu_ld_i64:
1425 tcg_out_qemu_ld(s, a0, a1, a2, true);
1426 break;
1427 case INDEX_op_qemu_st_i32:
1428 case INDEX_op_qemu_st_i64:
1429 tcg_out_qemu_st(s, a0, a1, a2);
1430 break;
1431
1432 case INDEX_op_ld32s_i64:
1433 tcg_out_ldst(s, a0, a1, a2, LDSW);
1434 break;
1435 case INDEX_op_ld_i64:
1436 tcg_out_ldst(s, a0, a1, a2, LDX);
1437 break;
1438 case INDEX_op_st_i64:
1439 tcg_out_ldst(s, a0, a1, a2, STX);
1440 break;
1441 case INDEX_op_shl_i64:
1442 c = SHIFT_SLLX;
1443 do_shift64:
1444
1445 tcg_out_arithc(s, a0, a1, a2 & 63, c2, c);
1446 break;
1447 case INDEX_op_shr_i64:
1448 c = SHIFT_SRLX;
1449 goto do_shift64;
1450 case INDEX_op_sar_i64:
1451 c = SHIFT_SRAX;
1452 goto do_shift64;
1453 case INDEX_op_mul_i64:
1454 c = ARITH_MULX;
1455 goto gen_arith;
1456 case INDEX_op_div_i64:
1457 c = ARITH_SDIVX;
1458 goto gen_arith;
1459 case INDEX_op_divu_i64:
1460 c = ARITH_UDIVX;
1461 goto gen_arith;
1462 case INDEX_op_ext_i32_i64:
1463 case INDEX_op_ext32s_i64:
1464 tcg_out_arithi(s, a0, a1, 0, SHIFT_SRA);
1465 break;
1466 case INDEX_op_extu_i32_i64:
1467 case INDEX_op_ext32u_i64:
1468 tcg_out_arithi(s, a0, a1, 0, SHIFT_SRL);
1469 break;
1470 case INDEX_op_extrl_i64_i32:
1471 tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
1472 break;
1473 case INDEX_op_extrh_i64_i32:
1474 tcg_out_arithi(s, a0, a1, 32, SHIFT_SRLX);
1475 break;
1476
1477 case INDEX_op_brcond_i64:
1478 tcg_out_brcond_i64(s, a2, a0, a1, const_args[1], arg_label(args[3]));
1479 break;
1480 case INDEX_op_setcond_i64:
1481 tcg_out_setcond_i64(s, args[3], a0, a1, a2, c2);
1482 break;
1483 case INDEX_op_movcond_i64:
1484 tcg_out_movcond_i64(s, args[5], a0, a1, a2, c2, args[3], const_args[3]);
1485 break;
1486 case INDEX_op_add2_i64:
1487 tcg_out_addsub2_i64(s, args[0], args[1], args[2], args[3], args[4],
1488 const_args[4], args[5], const_args[5], false);
1489 break;
1490 case INDEX_op_sub2_i64:
1491 tcg_out_addsub2_i64(s, args[0], args[1], args[2], args[3], args[4],
1492 const_args[4], args[5], const_args[5], true);
1493 break;
1494 case INDEX_op_muluh_i64:
1495 tcg_out_arith(s, args[0], args[1], args[2], ARITH_UMULXHI);
1496 break;
1497
1498 gen_arith:
1499 tcg_out_arithc(s, a0, a1, a2, c2, c);
1500 break;
1501
1502 gen_arith1:
1503 tcg_out_arithc(s, a0, TCG_REG_G0, a1, const_args[1], c);
1504 break;
1505
1506 case INDEX_op_mb:
1507 tcg_out_mb(s, a0);
1508 break;
1509
1510 case INDEX_op_mov_i32:
1511 case INDEX_op_mov_i64:
1512 case INDEX_op_movi_i32:
1513 case INDEX_op_movi_i64:
1514 case INDEX_op_call:
1515 default:
1516 tcg_abort();
1517 }
1518}
1519
1520static const TCGTargetOpDef sparc_op_defs[] = {
1521 { INDEX_op_exit_tb, { } },
1522 { INDEX_op_goto_tb, { } },
1523 { INDEX_op_br, { } },
1524 { INDEX_op_goto_ptr, { "r" } },
1525
1526 { INDEX_op_ld8u_i32, { "r", "r" } },
1527 { INDEX_op_ld8s_i32, { "r", "r" } },
1528 { INDEX_op_ld16u_i32, { "r", "r" } },
1529 { INDEX_op_ld16s_i32, { "r", "r" } },
1530 { INDEX_op_ld_i32, { "r", "r" } },
1531 { INDEX_op_st8_i32, { "rZ", "r" } },
1532 { INDEX_op_st16_i32, { "rZ", "r" } },
1533 { INDEX_op_st_i32, { "rZ", "r" } },
1534
1535 { INDEX_op_add_i32, { "r", "rZ", "rJ" } },
1536 { INDEX_op_mul_i32, { "r", "rZ", "rJ" } },
1537 { INDEX_op_div_i32, { "r", "rZ", "rJ" } },
1538 { INDEX_op_divu_i32, { "r", "rZ", "rJ" } },
1539 { INDEX_op_sub_i32, { "r", "rZ", "rJ" } },
1540 { INDEX_op_and_i32, { "r", "rZ", "rJ" } },
1541 { INDEX_op_andc_i32, { "r", "rZ", "rJ" } },
1542 { INDEX_op_or_i32, { "r", "rZ", "rJ" } },
1543 { INDEX_op_orc_i32, { "r", "rZ", "rJ" } },
1544 { INDEX_op_xor_i32, { "r", "rZ", "rJ" } },
1545
1546 { INDEX_op_shl_i32, { "r", "rZ", "rJ" } },
1547 { INDEX_op_shr_i32, { "r", "rZ", "rJ" } },
1548 { INDEX_op_sar_i32, { "r", "rZ", "rJ" } },
1549
1550 { INDEX_op_neg_i32, { "r", "rJ" } },
1551 { INDEX_op_not_i32, { "r", "rJ" } },
1552
1553 { INDEX_op_brcond_i32, { "rZ", "rJ" } },
1554 { INDEX_op_setcond_i32, { "r", "rZ", "rJ" } },
1555 { INDEX_op_movcond_i32, { "r", "rZ", "rJ", "rI", "0" } },
1556
1557 { INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rJ", "rJ" } },
1558 { INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rJ", "rJ" } },
1559 { INDEX_op_mulu2_i32, { "r", "r", "rZ", "rJ" } },
1560 { INDEX_op_muls2_i32, { "r", "r", "rZ", "rJ" } },
1561
1562 { INDEX_op_ld8u_i64, { "R", "r" } },
1563 { INDEX_op_ld8s_i64, { "R", "r" } },
1564 { INDEX_op_ld16u_i64, { "R", "r" } },
1565 { INDEX_op_ld16s_i64, { "R", "r" } },
1566 { INDEX_op_ld32u_i64, { "R", "r" } },
1567 { INDEX_op_ld32s_i64, { "R", "r" } },
1568 { INDEX_op_ld_i64, { "R", "r" } },
1569 { INDEX_op_st8_i64, { "RZ", "r" } },
1570 { INDEX_op_st16_i64, { "RZ", "r" } },
1571 { INDEX_op_st32_i64, { "RZ", "r" } },
1572 { INDEX_op_st_i64, { "RZ", "r" } },
1573
1574 { INDEX_op_add_i64, { "R", "RZ", "RJ" } },
1575 { INDEX_op_mul_i64, { "R", "RZ", "RJ" } },
1576 { INDEX_op_div_i64, { "R", "RZ", "RJ" } },
1577 { INDEX_op_divu_i64, { "R", "RZ", "RJ" } },
1578 { INDEX_op_sub_i64, { "R", "RZ", "RJ" } },
1579 { INDEX_op_and_i64, { "R", "RZ", "RJ" } },
1580 { INDEX_op_andc_i64, { "R", "RZ", "RJ" } },
1581 { INDEX_op_or_i64, { "R", "RZ", "RJ" } },
1582 { INDEX_op_orc_i64, { "R", "RZ", "RJ" } },
1583 { INDEX_op_xor_i64, { "R", "RZ", "RJ" } },
1584
1585 { INDEX_op_shl_i64, { "R", "RZ", "RJ" } },
1586 { INDEX_op_shr_i64, { "R", "RZ", "RJ" } },
1587 { INDEX_op_sar_i64, { "R", "RZ", "RJ" } },
1588
1589 { INDEX_op_neg_i64, { "R", "RJ" } },
1590 { INDEX_op_not_i64, { "R", "RJ" } },
1591
1592 { INDEX_op_ext32s_i64, { "R", "R" } },
1593 { INDEX_op_ext32u_i64, { "R", "R" } },
1594 { INDEX_op_ext_i32_i64, { "R", "r" } },
1595 { INDEX_op_extu_i32_i64, { "R", "r" } },
1596 { INDEX_op_extrl_i64_i32, { "r", "R" } },
1597 { INDEX_op_extrh_i64_i32, { "r", "R" } },
1598
1599 { INDEX_op_brcond_i64, { "RZ", "RJ" } },
1600 { INDEX_op_setcond_i64, { "R", "RZ", "RJ" } },
1601 { INDEX_op_movcond_i64, { "R", "RZ", "RJ", "RI", "0" } },
1602
1603 { INDEX_op_add2_i64, { "R", "R", "RZ", "RZ", "RJ", "RI" } },
1604 { INDEX_op_sub2_i64, { "R", "R", "RZ", "RZ", "RJ", "RI" } },
1605 { INDEX_op_muluh_i64, { "R", "RZ", "RZ" } },
1606
1607 { INDEX_op_qemu_ld_i32, { "r", "A" } },
1608 { INDEX_op_qemu_ld_i64, { "R", "A" } },
1609 { INDEX_op_qemu_st_i32, { "sZ", "A" } },
1610 { INDEX_op_qemu_st_i64, { "SZ", "A" } },
1611
1612 { INDEX_op_mb, { } },
1613 { -1 },
1614};
1615
1616static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
1617{
1618 int i, n = ARRAY_SIZE(sparc_op_defs);
1619
1620 for (i = 0; i < n; ++i) {
1621 if (sparc_op_defs[i].op == op) {
1622 return &sparc_op_defs[i];
1623 }
1624 }
1625 return NULL;
1626}
1627
1628static void tcg_target_init(TCGContext *s)
1629{
1630
1631
1632#ifndef use_vis3_instructions
1633 {
1634 unsigned long hwcap = qemu_getauxval(AT_HWCAP);
1635 use_vis3_instructions = (hwcap & HWCAP_SPARC_VIS3) != 0;
1636 }
1637#endif
1638
1639 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1640 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, ALL_64);
1641
1642 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1643 (1 << TCG_REG_G1) |
1644 (1 << TCG_REG_G2) |
1645 (1 << TCG_REG_G3) |
1646 (1 << TCG_REG_G4) |
1647 (1 << TCG_REG_G5) |
1648 (1 << TCG_REG_G6) |
1649 (1 << TCG_REG_G7) |
1650 (1 << TCG_REG_O0) |
1651 (1 << TCG_REG_O1) |
1652 (1 << TCG_REG_O2) |
1653 (1 << TCG_REG_O3) |
1654 (1 << TCG_REG_O4) |
1655 (1 << TCG_REG_O5) |
1656 (1 << TCG_REG_O7));
1657
1658 tcg_regset_clear(s->reserved_regs);
1659 tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0);
1660 tcg_regset_set_reg(s->reserved_regs, TCG_REG_G6);
1661 tcg_regset_set_reg(s->reserved_regs, TCG_REG_G7);
1662 tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6);
1663 tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7);
1664 tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6);
1665 tcg_regset_set_reg(s->reserved_regs, TCG_REG_T1);
1666 tcg_regset_set_reg(s->reserved_regs, TCG_REG_T2);
1667}
1668
1669#if SPARC64
1670# define ELF_HOST_MACHINE EM_SPARCV9
1671#else
1672# define ELF_HOST_MACHINE EM_SPARC32PLUS
1673# define ELF_HOST_FLAGS EF_SPARC_32PLUS
1674#endif
1675
1676typedef struct {
1677 DebugFrameHeader h;
1678 uint8_t fde_def_cfa[SPARC64 ? 4 : 2];
1679 uint8_t fde_win_save;
1680 uint8_t fde_ret_save[3];
1681} DebugFrame;
1682
1683static const DebugFrame debug_frame = {
1684 .h.cie.len = sizeof(DebugFrameCIE)-4,
1685 .h.cie.id = -1,
1686 .h.cie.version = 1,
1687 .h.cie.code_align = 1,
1688 .h.cie.data_align = -sizeof(void *) & 0x7f,
1689 .h.cie.return_column = 15,
1690
1691
1692 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
1693
1694 .fde_def_cfa = {
1695#if SPARC64
1696 12, 30,
1697 (2047 & 0x7f) | 0x80, (2047 >> 7)
1698#else
1699 13, 30
1700#endif
1701 },
1702 .fde_win_save = 0x2d,
1703 .fde_ret_save = { 9, 15, 31 },
1704};
1705
1706void tcg_register_jit(void *buf, size_t buf_size)
1707{
1708 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
1709}
1710
1711void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
1712{
1713 uint32_t *ptr = (uint32_t *)jmp_addr;
1714 uintptr_t disp = addr - jmp_addr;
1715
1716
1717
1718 tcg_debug_assert(disp == (int32_t)disp);
1719
1720 atomic_set(ptr, deposit32(CALL, 0, 30, disp >> 2));
1721 flush_icache_range(jmp_addr, jmp_addr + 4);
1722}
1723